JP2000175199A - Image processor, image processing method and providing medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly generate an address in the case of reading a prediction macro block from a frame memory. SOLUTION: A controller 14 calculates an address used to read a prediction macro block from a frame memory 5 for each motion compensation prediction mode and reference memories 8-1-8-n store the address in advance. Addresses corresponding to a motion vector fed from a variable length decoding section 31 are read from the reference memories 8-1-8-n and a switch 9 selects a prescribed address among them corresponding to a motion compensation prediction mode outputted from the variable length decoding section 31 and the selected address is fed to the frame memory 5. The frame memory 5 reads data of a predicted macro block stored in the received address and allows a prediction buffer 7b of a cache memory 7 to store the data. The predicted macro block data written in the prediction buffer 7b and data of a target macro block transformed by an inverse DCT transform section 38 are summed and stored in a slice output buffer 7a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method, and a providing medium, and more particularly to a method for quickly generating predicted image data necessary for decoding image data compressed by the MPEG system. The present invention relates to an image processing apparatus and method, and a providing medium as described above.

[0002]

2. Description of the Related Art Recently, MPEG2 (Moving Picture Experts
Image compression technology represented by Group 2) has advanced and is being used in various fields. The decoding (expansion) of the image data encoded (compressed) by the MPEG2 system is performed for each macroblock. DCT coefficients are separated from the image data of the macroblock of interest that has been subjected to the variable-length decoding, and in the case of a non-intra macroblock, a motion vector is further separated. In the case of an intra macro block, the DCT coefficient is subjected to an inverse DCT transform process, thereby obtaining an original image. On the other hand, in the case of a non-intra macro block, a predicted macro block corresponding to each macro block of interest is generated based on a motion vector. The predicted macroblock is added to the inverse DCT-transformed image data of the corresponding macroblock of interest.

[0003]

When reading out a predicted macroblock corresponding to a motion vector of one macroblock from the frame memory, an address of the frame memory is required. Therefore, (x,
It is necessary to determine the offset value from the (x, y) coordinate of the frame memory from the y) coordinate, the image type, the prediction type, and the motion vector for each of the luminance and the dye.

[0004] However, the image type includes information such as a frame structure or a field structure, an interlaced system or a progressive system, and an image size. When the frame type is a frame structure, the prediction type includes frame prediction, field prediction, And dual prime prediction, and for field structure, field prediction, 16
* 8 field prediction and dual prime prediction are included.

When the decoding process is performed by a software program, it is necessary to calculate the offset address on the frame memory by the software program. At this time, vector calculation must be performed while checking the current image type and prediction type for each macroblock. Not only the number of conditional statements on software increases, but also the amount of calculation increases, and There is a problem that the line processing becomes difficult and the processing time increases.

[0006] The present invention has been made in view of such circumstances, and enables an offset address of a frame memory to be obtained more quickly, thereby enabling a faster decoding process.

[0007]

According to a first aspect of the present invention, there is provided an image processing apparatus comprising: an extracting unit for extracting at least image data, a type, and a motion vector from input image data, and an image extracted by the extracting unit. Conversion means for converting the data into original image data by referring to the predicted image data; first storage means for storing image data for generating the predicted image data; and a motion vector extracted by the extraction means. Corresponding second storage means for storing the address of the first storage means for generating predicted image data, and second storage means for causing the first storage means to generate predicted image data. Reading means for reading out the stored address of the first storage means based on the type extracted by the extraction means.

According to a third aspect of the present invention, at least image data, type,
An extraction step of extracting the image data extracted in the extraction step, a conversion step of converting the image data extracted in the extraction step into original image data with reference to the prediction image data, and an image data for generating the prediction image data. A first memory step of storing the predicted image data corresponding to the motion vector extracted in the extracting step, the first memory address corresponding to the motion vector extracted in the extracting step, and a second memory address stored in the second memory. And a reading step of reading an address of the first memory stored in the second memory based on the type extracted in the extracting step, for causing the first memory to generate predicted image data. And characterized in that:

According to a fourth aspect of the present invention, there is provided the providing medium, comprising: an extracting step of extracting at least image data, a type, and a motion vector from the input image data; A conversion step of referencing and converting to original image data, a first storage step of storing image data for generating predicted image data in a first memory, and a motion vector extracted in the extraction step. A second storage step of storing an address of the first memory for generating predicted image data in a second memory, and a second memory for generating predicted image data in the first memory. A reading step of reading an address of the first memory stored in the memory based on the type extracted in the extracting step. Computer to execute sense apparatus and providing a readable program.

[0010] The image processing apparatus according to claim 1, and claim 3.
In the image processing method described in the above, the address for generating the predicted image data is stored in advance, and the address is read out based on the extracted type and the motion vector. It is.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, When the features of the present invention are described by adding the corresponding embodiments (however, examples) in parentheses after the means, the following is obtained.
However, of course, this description does not mean that each means is limited to those described.

[0012] The image processing apparatus according to the first aspect of the present invention, based on the input image data, at least image data, type,
And extraction means for extracting motion vectors (for example, FIG.
A variable-length decoding unit 31) and a conversion unit (for example, the inverse DCT conversion unit 3 in FIG. 2) that converts the image data extracted by the extraction unit into the original image data with reference to the predicted image data.
3), first storage means (for example, the frame memory 5 in FIG. 2) for storing image data for generating predicted image data, and predicted image data corresponding to the motion vector extracted by the extraction means. A second storage unit (for example, the reference memory 8 in FIG. 2) for storing an address of the first storage unit for generating, and a second storage unit for causing the first storage unit to generate predicted image data. Reading means for reading the address of the first storage means stored in the storage means based on the type extracted by the extraction means (for example,
And the switch 9) of FIG.

[0013] The image processing apparatus according to the second aspect of the present invention is a detecting means for detecting a change in type (for example, step S in FIG. 8)
1) and a change unit (for example, step S2 in FIG. 8) for changing an address read from the second storage unit when a change in type is detected by the detection unit.

FIG. 1 shows an example of the configuration of an image decoding apparatus that decodes (decodes) data encoded according to the MPEG2 system. The image data received by the tuner 1 is subjected to demodulation processing in the demodulation processing unit 2, and is subjected to error correction processing by the error correction processing unit 3. Further, the error-corrected image data is sent to the software processing unit 4.
Sent to The software processing unit 4 is configured by a software program executed by the CPU.

The demultiplexer 11 demultiplexes the input data into image data and audio data for each channel. The demultiplexed image data is decoded by the MPEG decoding unit 12 using the MPEG method. The output of the MPEG decoding unit 12 is subjected to image frame conversion processing in the image frame conversion processing unit 13 from, for example, an image frame of a high-definition television signal typified by HDTV to an image frame of an NTSC television signal. . Further, the controller 14 controls each unit of the software processing unit 4 in addition to the MPEG decoding unit 12, and uses the cache memory 7 as needed when processing image data.

DMAC (Direct Memory Access Controller) 6
Is the DMA from the cache memory 7 to the frame memory 5
Control the transfer. The frame memory 5 is, for example, a DRAM (D
dynamic Randam Access Memory). The processed image data is output from the frame memory 5 to an image output device (not shown).

The reference memory 8 composed of, for example, a RAM has n
It is composed of reference memories (areas) 8-1 to 8-n. The reference memory 8 (hereinafter, simply referred to as the reference memory 8 when it is not necessary to individually distinguish the reference memories 8-1 to 8-n), stores the predicted macroblock from the frame memory 5 based on the motion vector. An offset address required for reading image data is stored for each type such as an image type and a prediction type.

For example, in the reference memories 8-1 to 8-n, an offset address for generating a predicted macroblock of luminance data and an offset address for generating a predicted macroblock of chroma data in the frame prediction mode. Offset address required to read a predicted macroblock of luminance data in field prediction mode, and offset address required to read a predicted macroblock of chroma data in frame prediction mode; two luminance data of frame structure in dual prime prediction mode Of the first luminance data, the offset address required to read the second luminance data predicted macroblock, and the first chroma data predicted macroblock. The offset address required to output the predicted macroblock of the second chroma data, the offset address required to read the predicted macroblock of the second chroma data, and the first luminance data of the two luminance data of the field structure in the dual prime prediction mode. Offset address required to read predicted macroblock, second
Offset address required to read the predicted macroblock of the luminance data, the offset address required to read the predicted macroblock of the first chroma data of the two chroma data, and the predicted macro of the second chroma data An offset address and the like necessary for reading a block are stored.

When a motion vector is supplied from the software processing unit 4, the reference memories 8-1 to 8-n store
An offset address of the frame memory 5 stored at a position having the motion vector as an address is output.
The switch 9 controls the reference memories 8-1 to 8-8 based on the motion compensation prediction mode supplied from the software processing unit 4.
A predetermined address is selected from among the offset addresses output from −n and output to the frame memory 5.

FIG. 2 shows a more detailed configuration example of the MPEG decoding unit 12. The demultiplexed input image signal is subjected to variable-length decoding in a variable-length decoding unit 31. The variable length decoding unit 31 outputs the decoded image data for one slice and the quantization step to the inverse quantization unit 32, and outputs the motion vector to the reference memory 8. The variable length decoding unit 31 also sets the motion compensation prediction mode to the switch 9
Respectively. The inverse quantization unit 32 inversely quantizes the image data that has been subjected to the variable length decoding based on the quantization step supplied from the variable length decoding unit 31. The inversely quantized image data for one slice is stored in the cache memory 7 via the controller 14.

The data (DCT coefficients) read from the cache memory 7 is subjected to an inverse DCT transform (discrete cosine transform) by an inverse DCT transform unit 33, and is returned to the original image data.

In the case of an intra macro block, the image data that has been subjected to the inverse DCT transformation processing by the inverse DCT transformation section 33 is directly used as a slice output buffer 7a of the cache memory 7.
Is transferred and stored.

In the case of a non-intra macro block, a motion vector is supplied from the variable length decoding unit 31 to the reference memories 8-1 to 8-n. The reference memories 8-1 to 8-n are:
An offset address of the frame memory 5 stored at an address corresponding to the input motion vector is generated. The switch 9 corresponds to the motion compensation prediction mode supplied from the variable length decoding unit 31, and stores the reference memories 8-1 to 8-8.
A predetermined one of the offset addresses output from −n is selected and output to the frame memory 5. The frame memory 5 reads the predicted macroblock stored at the offset address input at this time, and outputs the image data line by line to the prediction buffer 7b of the cache memory 7 and stores it.

The arithmetic unit 34 is provided with image data (difference data) of the macroblock of interest supplied from the inverse DCT transform unit 33.
And the predicted macroblock supplied from the prediction buffer 7b, and the result is decoded image data, which is transferred to the slice output buffer 7a. And the cache memory 7
The image data for one slice stored in the slice output buffer 7a is DMA-transferred to the frame memory 5 under the control of the DMAC 6.

The operation of the image decoding device will be described. The tuner 1 receives the image data and outputs the image data to the demodulation processing unit 2. The demodulation processing unit 2 that has received the image data demodulates the received image data, and outputs the demodulated image data to the error correction processing unit 3. The error correction unit 3 that has received the demodulated image data performs an error correction process on the image data, and executes a software processing unit 4.
Output to

The software processing unit 4 having received the error-corrected image data, the demultiplexer unit 11 of the software processing unit 4 converts the received image data into
The image data and audio data are demultiplexed for each channel and output to the MPEG decoding unit 12.

The MPEG decoding unit 12 includes a controller 14
The image data is decoded by using the cache memory 7 and the frame memory 5 as needed. The decoded image data is temporarily stored in a slice output buffer of the cache memory 7 and then DMA-transferred to the frame memory 5 by the DMAC 6. When the image frame conversion processing needs to be performed, the controller 14
3 is controlled so that the image data stored in the frame memory 5 is read out, subjected to image frame conversion processing, and then stored in the frame memory 5 again. Then, the frame memory 5 outputs the image data subjected to the image frame conversion processing as necessary to an image output device (not shown).

Further, a detailed operation of the MPEG decoding unit 12 shown in FIG. 2 will be described. The variable length decoding unit 31 performs a variable length decoding process on a macroblock for one slice. The inverse quantization unit 32 inversely quantizes the demodulated data and temporarily stores the inversely quantized data for one slice in the cache memory 7.
To be stored. This allows not only pixel data (DCT coefficients), but also motion vectors, macroblock image types,
Data of a type such as a prediction type is obtained for one slice.

Next, the controller 14 causes the DCT coefficients of the intra macroblock to be read based on the macroblock type from the inversely quantized one-slice image data stored in the cache memory 7. It is supplied to the DCT converter 33. The inverse DCT transform unit 33 performs an inverse DCT transform process on the DCT coefficients of the intra macroblock. Then, the image data that has been subjected to the inverse DCT conversion processing is, as shown in FIG.
At a predetermined position.

In the example of FIG. 3, the gray light gray squares represent intra macroblocks, and the other white squares represent non-intra macroblocks. As shown in the figure, in the slice output buffer 7a, the data of the decoded intra macroblock is stored at the corresponding position.

Subsequently, the controller 14 selects a non-intra macro block based on the macro block type stored in the cache memory 7 and restores a corresponding motion vector.

Then, the controller 14 stores the predicted macro block corresponding to the motion vector in the frame memory 5.
In the order of the addresses. In other words, if the predicted macroblocks are distributed as shown in FIG. 4 for the slice to be decoded, the order of the predicted macroblocks is 6, 1
4, 11, 15, 1, 4, 5, 8, 16, 12, 13,
A predicted macroblock including pixels in an upper line, such as 17, 7, 9, 10, 2, 3, 18, and 19, becomes a predicted macroblock earlier.

Next, the controller 14 operates the reference memory 8
, And generates an address for reading each predicted macroblock from the frame memory 5 line by line in the rearranged order. The generated address is input to the frame memory 5 via the switch 9 (detailed operations of the reference memory 8 and the switch 9 in this case will be described later). The frame memory 5 reads the image data of the predicted macro block corresponding to the input address, and stores the read image data in the prediction buffer 7b of the cache memory 7, as shown in FIG.

For example, in the example of FIG.
Of the pixel data of the sixth predicted macro block is read out. When the pixel data of the line L2 is read, the pixel data of the prediction macro block of No. 14 is read following the pixel data of the prediction macro block of No. 6.

As shown in FIG. 5, the pixel data read out for each line is written to the position of the corresponding predicted macro block in the prediction buffer 7b for each line. In FIG. 5, a black cell indicates a decoded intra macroblock of the slice being processed, and a gray gradation cell indicates the intra macroblock stored in the slice output buffer 7 a of the cache memory 7. . A white cell surrounded by a solid line indicates a predicted macroblock stored in the prediction buffer 7b. The predicted macroblock is stored at a position corresponding to a non-intra macroblock other than the intra macroblock of the slice to be processed.

Then, the controller 14 causes the non-intra macro block (target macro block) stored in the cache memory 7 to be read, and
3 for inverse DCT transformation. The controller 14
Further, it causes the prediction unit 7 to read out the predicted macroblock from the prediction buffer 7b and supply it to the arithmetic unit 34. The operation unit 34 is an inverse DC
The data input from the T conversion unit 33 and the prediction buffer 7
The data input from b is added and stored at a corresponding position (a position where intra macroblock data is not stored) in the slice output buffer 7a. FIG.
This shows a state in which the data for one slice is stored in the slice output buffer 7a in a state where it is all decoded.

In FIG. 6, the slice output buffer 7a
The gray shaded cells indicate intra macroblocks, and the black cells indicate non-intra macroblocks. The white cells in the prediction buffer 7b indicate predicted macroblocks.

Further, the controller 14 controls the DMAC 6 to transfer the decoded data of one slice stored in the slice output buffer 7a to the frame memory 5 as shown in FIG. The stored image data is stored in the frame memory 5. The frame memory 5 has a plurality of banks,
Reads out the decoded and stored image data line by line from the bank to which the writing has already been completed, other than the bank in which the decoding data is being written, as described above. And output.

As described above, when the processing of the intra macroblock and the non-intra macroblock is collectively processed for each slice, the DCT coefficient and the motion vector are both differential signal processing, so that the processing efficiency is improved.

In the reading of the predicted macro block, the reading is performed for each line of the frame memory 5 and in the order of the addresses.
Data of a plurality of prediction blocks can be read, and the frequency of page errors in the memory can be reduced.

Further, since one slice of decoded data stored in the slice output buffer 7a of the cache memory 7 is transferred to the frame memory 5 by DMA transfer, the memory bandwidth can be used efficiently.

In the above, the slice output buffer 7
The data of a is DMA-transferred by the DMAC6.
Burst transfer may be performed by the controller 14.

Next, more detailed operations of the reference memory 8 and the switch 9 will be further described. The address stored in the reference memory 8 is the offset address of the frame memory 5 (the address required to read the predicted macroblock corresponding to the macroblock of interest). That is,
As shown in FIG. 8, the screen of one frame is composed of H × V pixels, and the position of the upper left pixel of the macro block of interest is the coordinates (h, v) on the screen. Is (dx, dy), the position of the predicted macroblock on the screen is
By applying H, V, h, v, dx, and dy to a predetermined prediction formula, it can be represented as an address from the upper left position on the screen. The address from the upper left position of this screen becomes the offset address of the frame memory 5 without being corrected.

However, in the case where the screen is composed of a frame structure and in the case where the screen is composed of a field structure,
The address of the upper left pixel of the prediction macroblock is represented by a different prediction expression. For example, in the case of frame prediction, the address of the luminance data of the upper left pixel of the predicted macroblock is
For example, it is represented by the following prediction formula. H × dy + dx + H × v + h (luminance)

On the other hand, since the number of chroma data is の of the luminance data, it is expressed by the following prediction formula, for example. (H / 2) × (dy / 2) + dx / 2 + (H / 2) × (v / 2) + (h / 2) (Chroma)

The address of the luminance data and the address of the chroma data in the case of the field prediction are represented by the following prediction formula, for example. 2 × H × dy + dx + H × v + h + (H or 0) (luminance) (H) × (dy / 2) + dx / 2 + (H / 2) × (v / 2) + h / 2 + (H / 2 or 0) (Chroma )

In the above formula, H of (H or 0) is
This is a value selected when one of the reference frame (frame of the predicted macroblock) and the input frame (frame of the macroblock of interest) is the top field, while the other is the bottom field. Is also a value selected when the field is a top field or a bottom field.

In the case of dual prime prediction, prediction is performed for each field block from the average value of two reference field blocks. The prediction formula in the frame structure in this case is represented by the following formula, for example. H × dy + dx + H × v + h + (H or 0) (luminance 1) (3/2) × {2 × H × dy + dx} + H × v + h + (H or 0) (luminance 2) or (1/2) × {2 × H × dy + dx} + H × v + h + (H or 0) (luminance 2) (H / 2) × (dy / 2) + dx / 2 + (H / 2) × (v / 2) + h / 2 + (H / 2 or 0 ) (Chroma 1) (3/2) × {H × (dy / 2) + dx / 2} + (H / 2) × (v / 2) + h / 2 + (H / 2 or 0) (Chroma 2) or , (1/2) × {H × (dy / 2) + dx / 2} + (H / 2) × (v / 2) + h / 2 + (H / 2 or 0) (Chroma 2)

Further, the prediction formula in the case of the field structure in the dual prime prediction mode is as follows, for example. 2 × H × dy + dx + H × v + h + (H or 0) (luminance 1) (1/2) × {2 × H × dy + dx} + H × v + h + (0 or H) (luminance 2) (H) × (dy / 2) + Dx / 2 + (H / 2) × (v / 2) + h / 2 + 0 (Chroma 1) (1/2) × {(H) × (dy / 2) + dx / 2} + (H / 2) × (v / 2) + h / 2 + H / 2 (Chroma 2)

Since two motion vectors of the dual prime prediction formula in the frame structure are sent,
The book must be generated on the decoder side. In this case, there is a difference depending on whether the current field is being decoded in the top field or the bottom field, and whether the prediction vector is the top field or the bottom field. Either multiply by (3/2) or multiply by (1/2). On the other hand, since only one motion vector of the dual prime prediction in the field structure is sent, and the other is the nearest field being decoded by itself, (1/2) Is multiplied.

The addresses of the frame memory 5 calculated based on such a prediction formula are stored in the reference memories 8-1 to 8-8.
−n is stored at a predetermined timing. Therefore, for example, in the frame prediction mode, the motion vector (dx = −8, dy
= 15) is supplied to the reference memory 8 from the variable length decoding unit 31, the reference memory 8-1 stores an address for reading a predicted macroblock of frame-structured luminance data from the frame memory 5, Reference memory 8
Assuming that the chroma data corresponding to -2 is stored, the address of the luminance data of the frame memory 5 corresponding to the motion vector is read from the address [15] [-8] of the reference memory 8-1. Then, the address of the chroma data of the frame memory 5 is read from the address [15] [-8] of the reference memory 8-2 and supplied to the frame memory 5 via the switch 9. These addresses indicate addresses at which predicted macroblocks of luminance data or chroma data corresponding to the input motion vector are stored in the frame memory 5. Therefore, the luminance data or chroma data is immediately transmitted from those addresses. The predicted macroblock will be read.

The range of motion vectors is dx = −1920 to +1920, and dy = −1088 to +10, including the case of the high definition television system.
It becomes 88. Assuming that all data corresponding to these addresses are stored in the reference memory 8, the reference memory 8 needs to have a 12-bit address. By doing so, the reference memory 8 becomes large. For example, the reference memory 8 is composed of two memories having 6-bit addresses, and each memory has a range of 6 bits (−63 to +63). The address of the upper 6 bits and the address of the lower 6 bits may be held. In this way, the size of the reference memory 8 can be further reduced.

As described above, the address for reading the predicted macro block from the frame memory 5 is stored in the reference memory 8 in advance, so that the prediction equation described above is calculated each time. Can be obtained quickly, and the predicted macroblock can be read out correspondingly faster.

Next, referring to the flowchart of FIG.
An example of processing when the controller 14 switches the reference memory 8 by controlling the reference memory 8 and the switch 9 will be described. First, in step S1, the controller 1
No. 4 determines whether or not the image size has changed, and whether or not the structure has been changed from the progressive system to the interlaced system or from the interlaced system to the progressive system. The data required for such determination is MPEG
It is included in the sequence header in the stream of the two systems. Therefore, the controller 14 makes this determination based on the data read from the sequence header by the variable length decoding unit 31. If there is a change in the image size, a change from the progressive system to the interlace system, or conversely, a change from the interlace system to the progressive system, the process proceeds to step S2, and the controller 14 makes the change. A process for updating a table stored in the reference memory 8-i corresponding to the item is executed. That is, the controller 14 calculates a new address using the above-described prediction formula, and
Update the contents of an existing table. If it is determined in step S1 that there is no change in the image size, the progressive method, the interlace method, or the like, the update processing in step S2 is skipped.

Next, in step S3, it is determined whether the image structure has been changed from the frame structure to the field structure or vice versa. Since this determination is described in the picture header provided for each picture, it is possible to determine whether or not this change has occurred from the information of the picture header output by the variable length decoding unit 31. If there is a change from the field structure to the frame structure or from the frame structure to the field structure, step S
4, the controller 14 determines that the corresponding reference memory 8
-Update the table of j. Also in this case, the calculation of the above-described prediction formula is performed. If it is determined in step S3 that there is no change in the image structure, the processing in step S4 is skipped.

As described above, the prediction formula is recalculated only when a predetermined item in the stream changes and the table needs to be changed. This makes it possible to quickly generate a predicted macroblock as compared with the case where an address is calculated each time using a prediction formula as in the conventional case.

In step S5, the image data of the predicted macroblock is generated from the frame memory 5 according to the table stored in the reference memory 8 as described above, and the decoding process is executed. In step S6, the controller 14 determines whether or not the frame decoding process has been completed. If the frame decoding process has not been completed yet, the process returns to step S5, and the subsequent processes are repeatedly executed. If it is determined that the decoding process for one frame has been completed, the controller 14 returns to step S3 and repeatedly executes the subsequent processes. The above processing is performed for each frame.

If an offset table of the prediction type is prepared according to the change of the image type, the offset table is recalculated every time the image type is changed, and the condition determination of the image type for each macroblock is performed. Becomes unnecessary, and the processing time in the software processing unit 4 can be shortened as a result.

In the above description, all tables are prepared in the reference memory 8 in advance. However, the capacity of the reference memory 8 is reduced, and a necessary table is written to the reference memory 8 each time. Or a table that is used more frequently can be preferentially prepared in the reference memory 8. Alternatively, some of the necessary calculations may be calculated and stored in advance in the reference memory 8 as a table, and the remaining calculations may be performed each time.

In the present specification, a providing medium for providing a user with a computer program for executing the above processing includes an information recording medium such as a magnetic disk and a CD-ROM, and a network such as the Internet and a digital satellite. Transmission media is also included.

[0061]

As described above, according to the image processing apparatus according to the first aspect, the image processing method according to the third aspect, and the providing medium according to the fourth aspect, the addresses are stored in advance. Since the corresponding address is read based on the extracted type and the motion vector, rapid image processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of an image decoding device to which the present invention has been applied.

FIG. 2 is a block diagram illustrating a configuration of an embodiment of an MPEG decoding unit 12 of FIG. 1;

FIG. 3 is a diagram showing a storage state of a slice output buffer of FIG. 2;

FIG. 4 is a diagram for explaining an operation when reading a predicted macroblock from the frame memory 5 of FIG. 2;

FIG. 5 is a diagram showing a storage state of a prediction frame buffer of FIG. 2;

FIG. 6 is a diagram showing a state when a macroblock for one slice of the slice output buffer 7a of FIG. 2 is decoded.

FIG. 7 is a diagram for explaining DMA transfer of a macroblock for one slice from the slice output buffer 7a of FIG. 2 to the frame memory 5;

FIG. 8 is a diagram illustrating a positional relationship between a macro block of interest and a predicted macro block.

FIG. 9 is a flowchart illustrating a process of the MPEG decoding unit 12 of FIG. 2;

[Explanation of symbols]

4 software processing unit, 5 frame memory, 6
DMAC, 7 cache memory, 7a slice output buffer, 7b prediction buffer, 8 reference memory, 9 switch, 12 MPEG decoding unit, 14
Controller, 31 variable length decoding unit, 32 inverse quantization unit, 33 inverse DCT transform unit, 34 operation unit

Continued on front page F-term (reference) 5C053 FA17 FA20 FA23 FA30 GB07 GB19 GB22 GB26 GB29 GB32 GB38 HA33 JA30 KA03 KA08 KA19 KA22 KA24 LA07 LA14 5C059 KK11 MA00 MA01 MA23 MC11 MC38 ME01 NN21 PP16 SS02 SS03 SS08 SS12 SS07 TA00 TB06 TB12 TC24 TC25 TD05 TD06 UA05 UA33 UA36

Claims (4)

[Claims] 1. An extracting unit for extracting at least image data, a type, and a motion vector from input image data, and extracting the image data extracted by the extracting unit from an original image by referring to predicted image data. Conversion means for converting the data into data; first storage means for storing image data for generating the predicted image data; and generation of the predicted image data corresponding to the motion vector extracted by the extraction means. The first for
Second storage means for storing the address of the storage means, and the first storage means stored in the second storage means for causing the first storage means to generate the predicted image data.
An image processing apparatus comprising: a reading unit that reads an address of the storage unit based on the type extracted by the extraction unit. 2. The apparatus according to claim 1, further comprising: detecting means for detecting the change of the type; and changing means for changing an address read from the second storage means when the change of the type is detected by the detecting means. The image processing apparatus according to claim 1, wherein: 3. An extraction step of extracting at least image data, a type, and a motion vector from input image data, and extracting the image data extracted in the extraction step by referring to predicted image data to obtain an original image. Converting image data for generating the predicted image data into a first image data;
A first storing step of storing the predicted image data corresponding to the motion vector extracted in the extracting step.
Is stored in the second memory.
Storing the address of the first memory stored in the second memory for causing the first memory to generate the predicted image data according to the type extracted in the extracting step. And a reading step of reading based on the image processing method. 4. An extracting step of extracting at least image data, a type, and a motion vector from input image data, and extracting the image data extracted in the extracting step by referring to predicted image data to obtain an original image. Converting image data for generating the predicted image data into a first image data;
A first storing step of storing the predicted image data corresponding to the motion vector extracted in the extracting step.
Is stored in the second memory.
Storing the address of the first memory stored in the second memory for causing the first memory to generate the predicted image data according to the type extracted in the extracting step. A computer-readable storage medium that provides a computer-readable program that causes an image processing apparatus to execute a process including a reading step of reading based on a computer program.