JP2000164813A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, in which the degree of freedom of the interface of a DRAM(dynamic random access memory) is improved, by optimizing the area and the consumption power of the DRAM to a necessary minimum limit, according to the power source specification of the integrated circuit. SOLUTION: This semiconductor integrated circuit device is provided with individual modules which include a DRAM 100 provided with a memory cell 101, a word driver 102, a row decoder 103, a sense amplifier 104, a column decoder 105, an address buffer 107, an I/O buffer 110, a control circuit 106, and a power source pin 109 for VDD2 to a memory cell 101, a voltage step-up module 120 wherein one side of a layout pattern on a wafer and the terminal position on the side are made identical with the length of the one side and to the terminal position of the DRAM module 100, and a level shifter circuit module 140, wherein one side of the layout pattern on the wafer and the terminal position on the side are made identical with the length of the one side and to the terminal position of the DRAM module 100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a dynamic random access memory (hereinafter abbreviated as DRAM), and more particularly to a CPU (Centra).
The present invention relates to a semiconductor integrated circuit in which a logic circuit such as an l processing unit or a conversion circuit and a DRAM are mixed.

[0002]

2. Description of the Related Art As a conventional semiconductor integrated circuit, for example, there is a semiconductor integrated circuit in which a DRAM is configured as a memory integrated circuit for storing information.

Usually, two types of DRAMs are used: a reference power supply voltage and a voltage higher than the reference power supply voltage. A power supply voltage higher than the reference power supply voltage of the two types of voltages is used for writing to a memory cell in the DRAM, and the reference power supply voltage is used for other circuits and the like.

Conventionally, in a semiconductor integrated circuit in which a DRAM and a logic circuit are mixed, only a reference power supply voltage is applied to the DRAM.
And a booster circuit provided inside the DRAM generates a power supply voltage higher than this reference power supply voltage to generate a DR.
It is used for writing to a memory cell in the AM. The output from the DRAM is in accordance with the supplied reference power supply voltage.

[0005]

However, the conventional D
In some semiconductor integrated circuits having a RAM, the same voltage as the voltage for writing to a memory cell is supplied from the outside. Even in this case, a booster circuit in a DRAM macro transfers a reference voltage from a reference power supply voltage to the memory cell. The voltage is increased to the voltage for writing. Therefore, installing a booster circuit in all the DRAM macros leads to an increase in the area of the DRAM and a problem of an increase in power consumption.

Further, in a semiconductor integrated circuit in which a DRAM and a logic circuit are mixedly mounted, when a logic circuit which requires an interface with the DRAM uses a power supply voltage lower than a reference power supply voltage, the level shifter circuit is required at design time. It is necessary to provide the circuit in a semiconductor integrated circuit, and there is a problem that the design burden increases.

The present invention provides a semiconductor integrated circuit in which the area and power consumption of a DRAM are optimized to the minimum necessary according to the power supply specification of the present semiconductor integrated circuit to increase the degree of freedom of the interface of the DRAM and reduce the design load. The purpose is to provide.

[0008]

A semiconductor integrated circuit according to the present invention comprises a memory cell, a word driver, a row decoder, a sense amplifier, a column decoder, an address buffer, an input / output buffer, a control circuit, and a power supply for writing to the memory cell. A dynamic random access memory provided with an input terminal, and a booster circuit section having one side of a layout pattern on a wafer and a terminal position on the side having the same length and the same terminal position as the one side of the dynamic random access memory And a level shifter circuit portion having one side of the layout pattern on the wafer and terminal positions on the side having the same length and the same terminal positions as the one side of the dynamic random access memory as individual modules. is there.

According to the present invention, a semiconductor integrated circuit in which the area and power consumption of a DRAM are optimized to a necessary minimum according to the power supply specification of the present semiconductor integrated circuit, the degree of freedom of the interface of the DRAM is increased, and the design load is reduced. Can be provided.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a memory cell, a word driver, a row decoder, a sense amplifier, a column decoder, an address buffer, an input / output buffer, a control circuit, and writing to the memory cell. A dynamic random access memory provided with an input terminal for a power supply, and a booster in which one side of a layout pattern on a wafer and a terminal position on the side have the same length and the same terminal position as that side of the dynamic random access memory. A circuit portion and a level shifter circuit portion having one side of the layout pattern on the wafer and terminal positions on the side having the same length and the same terminal position as the one side of the dynamic random access memory as individual modules. It is a semiconductor integrated circuit. According to the power supply specification of the semiconductor integrated circuit, D It is possible to provide a semiconductor integrated circuit with reduced load on the design and AM area of power consumption and increase the optimized degree of freedom interfaces DRAM required minimum.

According to a second aspect of the present invention, there is provided a power supply pad of a reference voltage for driving the dynamic random access memory of the first aspect, and a power supply pad of a voltage higher than the reference voltage. In the case of a semiconductor integrated circuit in which a random access memory and a logic circuit other than the random access memory are mounted, and a boosting function and a level shifter function are not required,
Since the DRAM, the booster circuit section, and the level shifter circuit section are individually modularized, a DRAM in which the booster circuit section and the level shifter circuit section are eliminated can be easily configured, and the area and power consumption of the DRAM can be minimized. Thus, a semiconductor integrated circuit with a reduced size can be obtained, and the design load can be reduced.

According to a third aspect of the present invention, there is provided a power supply pad having a voltage higher than a reference voltage for driving the dynamic random access memory according to the first aspect, and a regulator circuit for converting a power supply voltage. In the case of a semiconductor integrated circuit in which a dynamic random access memory and other logic circuits are mixed and a regulator circuit for converting a power supply voltage is provided and a boosting function and a level shifter function are not required, Since the DRAM, the booster circuit section, and the level shifter circuit section are individually modularized, a DRAM in which the booster circuit section and the level shifter circuit section are eliminated can be easily configured, and the area and power consumption of the DRAM can be minimized. The semiconductor integrated circuit with the minimum reduction can be obtained, and the design load can be reduced. .

According to a fourth aspect of the present invention, there is provided a dynamic random access memory having a power supply pad of a reference voltage for driving the dynamic random access memory according to the first aspect and connected to the booster circuit section according to the first aspect. In the case of a semiconductor integrated circuit in which an access memory and other logic circuits are mixed, and only the boosting function is required, the DRAM and the boosting circuit are modularized so that the boosting circuit is used. Parts can be easily added to the DRAM, and a semiconductor integrated circuit in which the area and power consumption of the DRAM are reduced to a necessary minimum can be obtained.
The design load can be reduced.

According to a fifth aspect of the present invention, there is provided a power supply pad having a normal reference voltage and a power supply pad having a voltage lower than the reference voltage. It is a semiconductor integrated circuit in which a dynamic random access memory connected to a level shifter circuit section and a logic circuit other than these are mounted. In the case of a semiconductor integrated circuit that needs a boosting function and a level shifter function, a DRAM and Since the booster circuit section and the level shifter circuit section are separately modularized, the booster circuit section and the level shifter circuit section can be easily added to the DRAM, and the area and power consumption of the DRAM have been reduced to the necessary minimum. A semiconductor integrated circuit can be obtained, and the design load can be reduced.

Hereinafter, a semiconductor integrated circuit according to the present invention will be described based on specific embodiments. (Embodiment 1) A semiconductor integrated circuit according to Embodiment 1 of the present invention comprises a memory cell 101, a word driver 102, a row decoder 103, and a sense amplifier 10 as shown in FIG.
4, a column decoder 105, an address buffer 107, an input / output buffer 110, a control circuit 106, and a memory cell 1.
DRAM module 10 as a dynamic random access memory (DRAM) provided with a power supply pin 109 for VDD2 as an input terminal for a power supply for writing data to 01
0, a booster circuit module 120 as a booster circuit section having one side of the layout pattern on the wafer and terminal positions on the side having the same length and the same terminal position as the one side of the DRAM module 100; A level shifter circuit module 140 as a level shifter circuit section having one side of the layout pattern and terminal positions on the side having the same length and the same terminal position as the one side of the DRAM module 100 is provided as an individual module. .

The DRAM module 100 includes a memory cell 101, a word driver 102, and a row decoder 10.
3, a sense amplifier 104, a column decoder 105, a control circuit 106, an address buffer 107, an input / output buffer 110, a power supply pin 108 for VDD1, a power supply pin 109 for VDD2, data input / output pins 111 to 113, and a control signal output pin 114. And input / output pins 115-117.

The booster circuit module 120 includes a power supply pin 121 for VDD1, a power supply output pin 122 for VDD2, a control signal input pin 123, input / output pins 124 to 129, and a booster circuit 130. The level shifter circuit module 140 includes a power supply pin 141 for VDD1 and
DD3 power supply pin 142 and data input / output pin 143-
148 and level shifter circuits 149 to 151.

Here, VDD1 is a reference power supply voltage (for example, 1.8 volts), VDD2 is a power supply voltage higher than the reference power supply voltage (for example, 3.3 volts),
VDD3 is a voltage lower than the reference power supply voltage (for example, 1.
5 volts).

In this DRAM module 100, VD
V2 from the power supply pin 109 for D2 to the word driver 102
DD2 is supplied, and a control signal from the control circuit 106 is output to the control signal output pin 114. The data input / output pins 111 to 113 are connected to the input / output buffer 110 so that input / output signals can be output in both directions.

In the booster circuit module 120, an external control signal input from the control signal input pin 123,
VDD1 supplied from the power supply pin 121 for VDD1 is input to the booster circuit 130. The booster circuit 130 boosts this VDD1 to VDD2 and outputs it to the power supply output pin 122 for VDD2. The input / output pins 124 to 12
6 and the input / output pins 127 to 129 are connected without passing through an internal circuit.

In the level shifter circuits 149 to 151 of the level shifter circuit module 140, the data input / output pin 1
46 to 148 are level-converted from VDD3 to VDD1, output to the data input / output pins 143 to 145, and the signals from the data input / output pins 143 to 145 are converted to VDD.
Data input / output pin 1 is converted from D1 to VDD3.
46 to 148.

As described above, the DRAM module 100, the booster circuit module 120, and the level shifter circuit module 140 are each configured as a separate module, and the DRAM module 100 does not have a booster circuit. The DRAM module 100 and the booster circuit module 120 have the same length of one side of the layout pattern on the wafer, and the terminal positions on the sides of the same length match. Also, the DRAM module 100 and the level shifter circuit module 140 have the same length of one side of the layout pattern on the wafer, and the terminal positions on the sides of the same length also match.

Here, as shown in FIG. 2, the booster circuit module 12
0 and the level shifter circuit module 140 are arranged in such a manner that the sides thereof having the same length are in contact with each other.
00 will be described.

According to the arrangement shown in FIG. 2, since the terminals are in contact with each other, wiring between modules is unnecessary except for the power supply. The terminal arrangement of the DRAM macro 900 is DRA
The arrangement is almost the same as the terminal arrangement of the M module 100 except for the power supply pins.

Therefore, when the DRAM needs a boosting function, the DRAM module 100 and the boosting circuit module 12
0 to form a DRAM macro with a booster circuit.
If the RAM requires a level shifter function, the DRAM module 100 and the level shifter circuit module 140 are connected to form a DRAM macro with a level shifter circuit.
DRAM if boost function and level shifter function are required
The booster circuit module 120 and the level shifter circuit module 140 are connected to the module 100 to form a DRAM macro with a booster function and a level shifter function.
It is possible to configure a DRAM macro of only the M module 100.

The partial circuits from the row decoder 103 to the word driver 102 shown in FIG.
A power supply 201 for DD2 and input nodes 202, 215,
216, output node 217, PMOS transistors 203, 204, 207, 208, NMOS transistors 205, 206, 209, 210, 211, and NA
The circuit is configured by the ND element 212 and the buffer elements 213 and 214. Among the logical elements of the NAND element 212 and the buffer elements 213 and 214, the buffer element 21
4 is supplied with VDD2 and the NAND element 21
2 and the buffer element 213 are supplied with VDD1. When a word line selection signal is input to the input nodes 202, 215, and 216, VDD2 is output from the output node 217 at the time of selection.

As shown in FIG. 4, a memory cell 310 as a one-bit configuration of the memory cell 101 shown in FIG. 1 has a bit line 301, a word line 302, an NMOS transistor 303, and a capacitor 304.
It is composed of a transistor 303 and a capacitor 304. When VDD1 is supplied to the bit line 301 and VDD2 is supplied to the word line 302, the memory cell 310 is selected.

The level shifter circuits 149 to 15 shown in FIG.
1 is a power supply 401 for VDD1, an input node 402, an output node 403, PMOS transistors 404 and 405, and NMOS transistors 406 and 4 as shown in FIG.
07 and an INV element 408. This IN
The power supply voltage of V element 408 is lower than power supply voltage V DD1.
DD3. When a signal having an amplitude corresponding to VDD3 is input to the input node 402, V
A signal having an amplitude corresponding to DD1 is output. Although the input circuit to the DRAM has been described in this example, the input / output circuit may be configured as a module.

As described above, the booster circuit module 12 is easily added to the DRAM module 100.
0 and the terminal positions of the level shifter circuit module 140 are the same as the terminal positions of the DRAM module 100 and are individually modularized, and the booster circuit module 120 and the level shifter Since the DRAM macro can be configured by changing the combination in which the circuit module 140 is added, the semiconductor integrated circuit optimizes the area and power consumption of the DRAM to the minimum necessary and increases the degree of freedom of the interface of the DRAM. You can get
The design load can be reduced.

More specifically, the DRAM module 100 and the booster circuit module 120 are formed so that the lengths of the sides of the layout pattern on the wafer are equal to each other and the terminal positions on the sides of the equal length are matched. Since the module 100 and the level shifter circuit module 140 are also formed such that the lengths of the sides of the layout pattern on the wafer are equal to each other and the terminal positions on the sides of the same length are also matched, the booster circuit The module 120 and the level shifter circuit module 140 can be easily added.

(Embodiment 2) As shown in FIG. 6, a semiconductor integrated circuit according to Embodiment 2 of the present invention has a reference voltage (VDD1) for driving the DRAM module 100 of Embodiment 1 described above. A power supply pad 503 for VDD1 as a power supply pad, and a voltage higher than VDD1 (VDD
Power supply pad 5 for VDD2 as power supply pad of D2)
In this embodiment, a DRAM macro 501 including only the DRAM module 100 and a logic 502 as a logic circuit such as a CPU and a conversion circuit other than the DRAM macro 501 are mounted.

As shown in FIG. 6, this hybrid semiconductor integrated circuit 500 has a DRAM macro 501, a logic 502, and a VDD which are constituted only by a DRAM module 100.
Power supply pad 503 for power supply 1 and power supply pad 50 for VDD2
4. This power supply pad 5 for VDD1
03 is supplied with a reference power supply voltage VDD1 and VDD2.
The power supply pad 504 is supplied with a power supply voltage VDD2 higher than the reference power supply voltage VDD1. This VDD1
VDD1 from the power supply pad 503 for power supply is supplied to the power supply pin 108 for VDD1 of the DRAM module 100, and VDD2 from the power supply pad 504 for VDD2 is
The power is supplied to a power supply pin 109 for VDD2 provided in the RAM module 100.

As described above, the power supply pad 50 for VDD2
In the case of the semiconductor integrated circuit 500 to which VDD2 is inputted to the DRAM macro 501 and the boost function and the level shifter function are unnecessary in the DRAM macro 501, the DRAM macro 501 is constituted only by the modularized DRAM module 100. Is provided with a power supply pin 109 for VDD2 that receives VDD2 from a power supply pad 504 for VDD2, so that it is possible to obtain a semiconductor integrated circuit in which the area and power consumption of the DRAM macro 501 are reduced to the necessary minimum. Load can be reduced.

(Third Embodiment) As shown in FIG. 7, a semiconductor integrated circuit 600 according to a third embodiment of the present invention has a reference voltage (VDD1) for driving the DRAM module 100 according to the first embodiment. VDD as power supply pad
1 and a power supply pad 604 for VDD3 as a power supply pad of a voltage (VDD3) lower than VDD1. The booster circuit module 120 and the level shifter circuit module 140 of the first embodiment are connected to each other. D configured with the DRAM module 100
A RAM macro 601 and a logic 602 as a logic circuit such as a CPU and a conversion circuit other than the DRAM macro 601 are mounted together.

As shown in FIG. 7, the hybrid semiconductor integrated circuit 600 includes a DRAM macro 601 in which the booster circuit module 120 and the level shifter circuit module 140 are connected to the DRAM module 100 in contact with each other.
Logic 602, power supply pad 603 for VDD1,
And a power supply pad 604 for VDD3. The power supply pad 603 for VDD1 has a reference power supply voltage V
DD1 is supplied, and the power supply pad 604 for VDD3 is supplied with a power supply voltage VDD3 lower than VDD1.

The VDD1 from the VDD1 power supply pad 603 is connected to the VDD1 power supply pin 108 of the DRAM module 100 and the VDD1 of the booster circuit module 120.
1 and a power supply pin 141 for VDD1 of the level shifter circuit module 140. VDD from the power supply pad 604 for VDD3
3 is supplied to the logic 602 and the power supply pin 142 for VDD3 of the level shifter circuit module 140.

The booster circuit module 120 receives a signal from the DRAM module 100, generates a voltage VDD2 higher than VDD1, and generates a power supply output pin 1 for VDD2.
22 to a power supply pin 109 for VDD2 of the DRAM module 100. The level shifter circuit module 140 receives the signal from the logic 602, converts the amplitude of the signal from VDD3 to VDD1, and
It has been delivered to the RAM module 100.

As described above, the power supply pad 60 for VDD1
3 is supplied with VDD1 and a power supply pad 6 for VDD3.
In the case of the semiconductor integrated circuit 600 to which VDD3 is inputted to the DRAM macro 601 and the DRAM macro 601 needs a boosting function and a level shifter function, the DRAM macro 100 including the modularized DRAM module 100, the boosting circuit module 120 and the level shifter circuit module 140 601, and V 1 boosted from VDD 1 by the booster circuit module 120.
A semiconductor integrated circuit having the DRAM module 100 that receives the DD2 and a signal obtained by level-converting data from the logic 602 by the level shifter circuit module 140 can be obtained, and the design load can be reduced.

Fourth Embodiment As shown in FIG. 8, a semiconductor integrated circuit 700 according to a fourth embodiment of the present invention has a reference voltage (VDD1) for driving the DRAM module 100 according to the first embodiment. A power supply pad 704 for VDD2 as a power supply pad for a higher voltage (VDD2);
A regulator 703 is provided as a regulator circuit for converting the power supply voltage from VDD2 to VDD1.
A DRAM macro 701 composed of only the AM module 100 and a logic 702 as a logic circuit such as a CPU and a conversion circuit other than the above are mixedly mounted.

The power supply pad 704 for VDD2 is supplied with a power supply voltage VDD2 higher than the reference power supply voltage VDD1. V from the power supply pad 704 for VDD2
DD2 is supplied to the power supply pin 109 for VDD2 and the regulator 703 of the DRAM module 100. The regulator 703 converts the power supply voltage from VDD2 to VDD1 and outputs the power supply voltage to the power supply pin 108 for VDD1 of the DRAM module 100 and the logic 702.

As described above, the power supply pad 70 for VDD2
4, a regulator 703 for converting the voltage of VDD2 to VDD1 is provided. In the case of the semiconductor integrated circuit 700 which does not require the boosting function and the level shifter function in the DRAM macro 701, the DRAM macro 701
Is composed of only the DRAM module 100 and this DRA
The M module 100 has a power supply pad 70 for VDD2.
Power supply pin 10 for receiving VDD2 from VDD4
9 and VDD which receives VDD1 from the regulator 703
Since the power supply pin 108 for D1 is provided, the DRAM
A semiconductor integrated circuit in which the area and power consumption of the macro 701 are reduced to the necessary minimum can be obtained, and the design load can be reduced.

(Fifth Embodiment) As shown in FIG. 9, a semiconductor integrated circuit 800 according to a fifth embodiment of the present invention has a reference voltage (VDD1) for driving the DRAM module 100 according to the first embodiment. VDD as power supply pad
A DRAM macro 801 including a power supply pad 803 for one, and a DRAM module 100 connected to the booster circuit module 120 as the booster circuit unit of the first embodiment, and a CPU and a conversion circuit other than the DRAM macro 801 And a logic 802 as a logic circuit.

The reference power supply voltage VDD1 is supplied to the power supply pad 803 for VDD1. The VDD1 from the VDD1 power supply pad 803 is supplied to the VDD1 power supply pin 108 of the DRAM module 100, the VDD1 power supply pin 121 of the booster circuit module 120, and the logic 802. In the booster circuit module 120, VDD1 is boosted to VDD2 and VDD is increased.
2 from the power output pin 122 for the DRAM module 10
0 is supplied to the power supply pin 109 for VDD2.

As described above, the power supply pad 80 for VDD1 is used.
In the case of the semiconductor integrated circuit 800 in which VDD1 is input to the DRAM 3 and the DRAM macro 801 only needs the boosting function, the DRAM macro 801 is composed of the modularized DRAM module 100 and the boosting circuit module 120, and the boosting circuit module It is possible to obtain a semiconductor integrated circuit having the DRAM module 100 that receives VDD2 which is VDD1 boosted from 120, and the design load can be reduced.

[0045]

As described above, according to the semiconductor integrated circuit of the first aspect of the present invention, a memory cell, a word driver, a row decoder, a sense amplifier, a column decoder, an address buffer, an input / output buffer, a control circuit, A dynamic random access memory (DRAM) provided with an input terminal for a write power supply to the memory cell, and one side of a layout pattern on a wafer and terminal positions on the side having the same length as the one side of the DRAM A booster circuit section having the same terminal position and a level shifter circuit section having one side of the layout pattern on the wafer and the terminal position on the side having the same length and the same terminal position as the one side of the DRAM are separate modules. DRAM
The optimal DRAM macro can be configured by changing the combination of adding a booster circuit section and a level shifter circuit section according to the power supply specification of the semiconductor integrated circuit on which the logic and the logic are mounted. It is possible to obtain a semiconductor integrated circuit that has been optimized to a minimum and has increased flexibility in the interface of the DRAM, thereby reducing the design load.

According to the semiconductor integrated circuit of the present invention, a power supply pad of a reference voltage for driving the dynamic random access memory and a power supply pad of a voltage higher than the reference voltage are provided. With
Since the dynamic random access memory and other logic circuits are mixedly mounted, the DRAM, the booster circuit section and the level shifter circuit section are individually modularized, and the booster circuit and the level shifter function are not required. DR in which the section and the level shifter circuit section are deleted
The AM can be easily configured, a semiconductor integrated circuit in which the area and power consumption of the DRAM are reduced to the necessary minimum can be obtained, and the design load can be reduced.

According to a third aspect of the present invention, a power supply pad having a voltage higher than a reference voltage for driving the dynamic random access memory according to the first aspect, and a regulator for converting a power supply voltage are provided. Circuit, and the dynamic random access memory and other logic circuits are mixedly mounted.
Since the AM, the booster circuit section, and the level shifter circuit section are individually modularized, and the booster function and the level shifter function are unnecessary, the DRAM in which the booster circuit section and the level shifter circuit section are eliminated can be easily configured, and the DRAM can be easily constructed. The semiconductor integrated circuit in which the area and power consumption are reduced to the necessary minimum can be obtained, and the design load can be reduced.

According to a fourth aspect of the present invention, there is provided a booster circuit having a reference voltage power supply pad for driving the dynamic random access memory according to the first aspect. Since the DRAM and the booster circuit are modularized by incorporating the dynamic random access memory connected to the memory and the other logic circuits, the booster circuit can be easily integrated into the DRAM.
And a semiconductor integrated circuit in which the area and power consumption of the DRAM are reduced to the necessary minimum can be obtained, and the design load can be reduced.

According to a fifth aspect of the present invention, there is provided a power supply pad of a reference voltage for driving the dynamic random access memory of the first aspect and a power supply pad of a voltage lower than the reference voltage. With
A dynamic random access memory in which the booster circuit section and the level shifter circuit section according to claim 1 are connected to each other and a logic circuit other than the dynamic random access memory section are mounted on the DRAM.
And the booster circuit section and the level shifter circuit section are separately modularized, so that the booster circuit section and the level shifter circuit section can be easily added to the DRAM, and the area and power consumption of the DRAM can be reduced to a minimum. A semiconductor integrated circuit can be obtained, and the design load can be reduced.

[Brief description of the drawings]

FIG. 1 shows a DR of a semiconductor integrated circuit according to a first embodiment of the present invention.
Block diagram showing AM macro

FIG. 2 is a block diagram showing an arrangement of each module according to the first embodiment;

FIG. 3 is a circuit diagram showing a part of the DRAM module according to the first embodiment;

FIG. 4 is a circuit diagram showing a 1-bit configuration of a memory cell according to the first embodiment;

FIG. 5 is a circuit diagram showing a level shifter circuit according to the first embodiment;

FIG. 6 is a block diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 7 is a block diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention;

FIG. 8 is a block diagram showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a semiconductor integrated circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 DRAM module 101 memory cell 102 word driver 108 power supply pin for VDD1 109 power supply pin for VDD2 114 control signal output pin 120 booster circuit module 121, 141 power supply pin for VDD1 122 power supply output pin for VDD2 123 control signal input pin 130 booster circuit 140 level shifter circuit module 142 power supply pin for VDD3 149 to 151 level shifter circuit 201 power supply for VDD2 301 bit line 302 word line 303 NMOS transistor 304 capacitor 310 memory cell 401 power supply for VDD1 402 input node 403 output node 500 600 power supply pad for semiconductor integrated circuit 501, 601 DRAM macro 502, 602 logic 503, 603 VDD1 04,704 power pads 700, 800 semiconductor integrated circuit for the power supply pads 604 VDD3 for VDD2 701 and 801 DRAM macro 702 and 802 supply pads 900 DRAM macro logic 703 Regulator 803 VDD 1

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G11C 11/401 G11C 11/34 371K (72) Inventor Nobuyuki Nakai 1006 Odakadoma, Kadoma City, Osaka Matsushita Electric Industrial F term in reference (reference) 5B015 JJ03 KB63 KB91 KB93 PP02 PP07 5B024 AA01 BA27 BA29 CA21 5F038 BE07 BE09 BG03 BG06 BG10 DF08 DF11 EZ07

Claims (5)

[Claims] A dynamic random access memory provided with a memory cell, a word driver, a row decoder, a sense amplifier, a column decoder, an address buffer, an input / output buffer, a control circuit, and an input terminal for writing power to the memory cell; A booster circuit section having one side of the layout pattern on the wafer and a terminal position on the side having the same length and the same terminal position as the one side of the dynamic random access memory; and one side of the layout pattern on the wafer and the same. A semiconductor integrated circuit comprising, as individual modules, a level shifter circuit section in which terminal positions on a side have the same length and the same terminal position as one side of the dynamic random access memory. 2. The dynamic random access memory according to claim 1, further comprising: a power supply pad for driving the dynamic random access memory according to claim 1; and a power supply pad having a voltage higher than the reference voltage. Semiconductor integrated circuit. 3. The dynamic random access memory according to claim 1, further comprising: a power supply pad having a voltage higher than a reference voltage for driving the dynamic random access memory; and a regulator circuit for converting a power supply voltage. And a semiconductor integrated circuit. 4. A dynamic random access memory comprising a reference voltage power supply pad for driving the dynamic random access memory according to claim 1 and connected to the booster circuit unit according to claim 1, and another logic circuit. Mixed semiconductor integrated circuit. 5. A booster circuit section and a level shifter circuit section according to claim 1, further comprising a reference voltage power supply pad for driving the dynamic random access memory according to claim 1, and a power supply pad having a voltage lower than the reference voltage. A semiconductor integrated circuit in which a dynamic random access memory connected to the above and a logic circuit other than these are mounted.