JP2000155554A - Flat-panel display device and display drive device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent display characteristic deterioration due to DC drive etc., of a display panel caused by abnormality in a signal by providing a signal detection means for detecting abnormality in a first signal and a sequence processing means change-processing a signal form of a flat display module part side based on the detected signal in a signal management control means. SOLUTION: A signal management control part 471 is provided with a signal stop detection circuit 48 as a signal detection means detecting a stop of a signal to be detected and a sequence processing circuit 51 consisting of a signal delay circuit 49 and a logic circuit 50. Then, when the first signal is stopped in a display body module side, that is detected by the signal stop detection circuit 48. Then, the sequence processing circuit 51 controls a display body drive means, and the drive means sets a display body applied voltage to zero. Thus, even when the first signal of clock etc., is stopped, since the DC drive of a display body of a liquid crystal etc., is evaded, the display characteristic deterioration is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display (LC).
D), a flat display such as a plasma display panel (PDP) and an application device thereof, and more particularly, in a flat display device having a form in which a display module unit and a display control unit for controlling the display are separately arranged. The present invention relates to a signal management technique on the display module side.

[0002]

2. Description of the Related Art Conventionally, portable personal computers and word processors, which are generally called laptops, generally have an openable and closable flat display unit. As shown in FIG. 9, a liquid crystal display control unit 10 built in the apparatus main body and a flat liquid crystal display module unit 20 provided inside the opening / closing lid are separate and independent arrangements. The liquid crystal display controller 10 has a liquid crystal module controller 12 and a microprocessor unit (MPU) (not shown). The liquid crystal module controller 12 sends various control signals and clocks to the liquid crystal display module 20 side. Supply signal.

The liquid crystal display module section 20 includes, for example, a liquid crystal display panel (matrix liquid crystal display element) 22 of a simple matrix type and a TA in a peripheral (frame) area of the panel 22.
It has a signal electrode drive circuit (X driver) 24 and a scan electrode drive circuit (Y driver) 26 mounted in B, and a liquid crystal power supply circuit 28 for generating high liquid crystal drive voltages (reference voltages) V _{0 to} V _5. ing. The signal electrode drive circuit 24 includes a plurality of signal electrode driver semiconductor integrated circuits 24 _{1 to} 24 _m.
For example, a driver output is supplied for each line of a screen to a total of M signal electrodes. That is, the data signals D0 to D7 are sequentially taken into the shift register in the signal electrode drive circuit 24 by the pixel clock (shift clock pulse) XSCL, and when the signal (M bits) for one line of the screen is taken, scanning is performed. Line synchronization signal YSCL (data signal latch clock LP)
As a result, the data signal in the shift register is sent in parallel to the data latch circuit, and the data signal is subjected to serial / parallel conversion. In the data latch circuit, the signal voltage for one line is held for one scanning period, and based on the signal voltage, the selection switch circuit sets the driver output voltage connected to the signal electrode to either a selected or non-selected state. I do. The AC conversion clock FR is a clock that converts the above-described voltages into AC waveforms in order to prevent the liquid crystal element from being deteriorated due to DC driving. The forced blank display signal DF (bar) is a signal for forcibly bringing the liquid crystal screen into a blank display state. The scan electrode drive circuit 26 is configured as a cascade connection of a plurality of scan electrode driver semiconductor integrated circuits 26 _{1 to} 26 _n . For example, the selection voltage is applied to only one of the total N scan electrodes, and the other (N−1) Operate to apply a non-selection voltage to the scan electrodes. One scanning line period is started by the scanning start pulse (frame start signal) SP, and every time the scanning line synchronizing signal YSCL (data signal latch clock LP) is received, the selection voltage is changed from the first scanning electrode to the Nth row. It is successively applied to the scanning electrodes of the eyes (line order display). The liquid crystal power source circuit 28 disposed on the liquid crystal display module unit 20 side so as to generate a plurality of liquid crystal driving voltages V ₀ ~V ₅ to select the selection switch of the signal electrode driving circuit 24 and the scanning electrode driving circuit 26, The power is turned on / off by the forced blank display signal DF (bar).

[0004]

By the way, the liquid crystal display control section 10 built in the apparatus main body and the flat liquid crystal display module section 20 provided inside the opening / closing lid are generally connected via a hinge-coupled movable section. Are connected by a flexible cable 30. Therefore, each time the opening / closing lid on the side of the flat liquid crystal display module unit 20 is opened / closed, the cable 30 itself is bent, and the signal line of the cable 30 is likely to be damaged or broken due to physical factors. If a part of the signal line is broken, for example, the AC drive is not performed in a state where the DC voltage (DC component) is applied to the liquid crystal display panel 22, and it is expensive and difficult to replace as compared with other parts. The liquid crystal display panel 22 may be deteriorated. Such deterioration of the liquid crystal is a factor that hinders the life and display quality, and is an important problem for a display device based on visibility.

Here, the liquid crystal module controller 1
Among the signals supplied from the second to the liquid crystal display module unit 20 side, the signals that may cause the DC drive deterioration of the liquid crystal display panel 22 include a scan start pulse SP, a scan line synchronization signal YSCL (data signal latch clock L
P), AC clock FR and logic side power supply voltage V _C
C. In addition, even when any operation abnormality occurs in the liquid crystal module controller 12 and the microprocessor unit (MPU), the above-described signals may be abnormal, and the same situation as described above may occur.

By the way, the problem of the DC drive of the liquid crystal display can be generalized to the problem of signal abnormality on the liquid crystal module side. In addition, when assuming a wall-mounted television, since the display control unit and the display panel are remotely located, there is a problem of display quality deterioration due to signal level attenuation and noise influence while stopping signals. You. Further, the problem is not limited to the liquid crystal display but also to a plasma display.

Accordingly, an object of the present invention is to solve the above-described problems, and to solve the above-mentioned problems, deterioration of display characteristics due to DC drive of a display panel due to an abnormality of a signal supplied from the display control unit to the display module unit. It is an object of the present invention to provide a flat display device and a display body driving device which can prevent the occurrence of the problem.

[0008]

Generally, in a flat display device in which a display module section and a display control section for controlling the display are separately arranged, the display module side receives a control signal from the display control section or the like. Following the passive operation, the present invention employs an autonomous signal system having signal management control means. All of the components of the signal management control means can be provided on the display module side, but can also be shared between the display module section and the display control section.

The signal management control means includes a signal detection means for detecting occurrence of an abnormality in the first signal transferred from the display control section, and changes a signal form on the display module section based on the output of the signal detection means. And a sequence processing means for processing. A signal abnormality refers to a stop of a signal, a decrease in logic amplitude, interference, and the like. A typical example is a stop of a signal. In addition, examples of the flat display device include a liquid crystal display device and a plasma display device. A specific configuration of the signal detecting means is a signal stop detecting means for detecting stop of the first signal, and the sequence processing means applies a display object to be supplied to the display panel of the display driving means based on the output thereof. This is forcible stop control means for setting and controlling the voltage to zero. When the first signal stops on the display module side, this is detected by the signal stop detecting means. Thereby, the forcible stop control means controls the display driving means, and the driving means sets the display applied voltage to zero. Therefore, even when the first signal such as a clock is stopped, DC driving of a display such as a liquid crystal is avoided, so that deterioration of display characteristics can be prevented.

[0010] More specific forced stop control means include:
A first signal delay unit for delaying a second signal transferred from the display control unit in response to an output of the signal stop detection unit, and controlling display ON / OFF of the display unit driving unit based on the output; Can be adopted. According to such a configuration, it is a matter of course that the display of the liquid crystal panel can be set to the off state promptly by the generation of the detection signal. However, when the first signal is restarted, the display on state is restarted at that time. Instead, after a predetermined time determined based on the cycle of the second signal elapses, the display driving unit is set and controlled to be in the display ON state. Such a control method of the display body driving means with a time difference can prevent abnormal driving due to power supply abnormality induced by the rush current,
The power supply load can be reduced and the power supply circuit can be simplified.

The signal delay means is preferably an N-stage D flip-flop which receives a frame start signal as a second signal and is set / reset based on the output of the detection means. The delay time in such a case is determined in units of a frame period. A configuration in which a plurality of signal management control means are arranged on the liquid crystal module side can also be adopted. In such a case, stopping of a plurality of types of signals can be detected simultaneously. By providing a control terminal for a third signal for controlling the output of the forced stop control means, a plurality of signal management control means can be connected in cascade.
In such a case, when any one of the detected signals is stopped, it is possible to control the display off of the display driving means.

In order to prevent the display from deteriorating due to abnormal driving based on a further rush current, a power supply control means for controlling power on / off of a display power supply for generating a display driving voltage is provided by a display module. It is desirable to provide it on the part side. The power control means controls the power on / off of the display power supply means in accordance with the output of the detection means. With this configuration, the display power source is turned on after the expression of the first signal is confirmed on the display module side.

As a specific power control means, there is provided a second signal delay means for delaying a second signal transferred from the display control unit in accordance with an output of the detection means. A configuration for controlling power on / off of the means can be adopted. According to such a configuration,
After the output of the first signal has been confirmed and a predetermined time determined based on the cycle of the second signal has elapsed, the display power supply is turned on. For this reason, DC driving of the liquid crystal at the initial stage can be prevented.

In the case where the power supply control means is an M (<N) -stage D flip-flop which receives the display on / off signal as a second signal and is set / reset by the output of the detection means, After the display power supply is energized, the display drive is turned on. This also contributes to the reduction of the rush current. Here, M and N are positive integers.

The signal management control means according to the above configuration is provided on a glass substrate or the like on the display module side, but may be incorporated in a circuit of a display driver mounted on the display module side. Can be. That is, it can be realized as a display driving means with signal management control. Although the conventional display driver is configured as a driver LSI, such a display driver with signal management control may be configured as a semiconductor integrated circuit. Considering that the number of input / output wirings of the Y driver LSI among the driver LSIs is smaller than that of the X driver LSI, it is advantageous to use the Y driver as the driver LSI with the signal management control. The liquid crystal display device can be roughly classified into a simple matrix system and an active matrix system. It is desirable that the driver LSI with the signal management control is a scanning driver or a gate driver.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 is a block diagram showing the entire configuration of a liquid crystal display device according to Embodiment 1 of the present invention. In FIG. 1, the same portions as those shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

The scan driver semiconductor integrated circuit constituting the scanning electrode driving circuit (Y driver) 46 of the liquid crystal display module unit 40 in this embodiment _(LSI) 46 1 -46
_n has a signal management control unit 47.

First scan driver semiconductor integrated circuit 46
Signal management control unit 47 ₁ of ₁ detects the stop of the scanning line synchronization signal YSCL applied to the terminal CKB1 (data signal latch clock LP). The second scan driver semiconductor integrated circuit 46 ₂ of the signal management control unit 47 ₂ terminal CK
The stop of the scan start pulse (frame start signal) SP applied to B2 is detected. The signal management control unit 47 _n of the n-th (for example, third) scan driver semiconductor integrated circuit 46 _n outputs the AC clock F applied to the terminal CKBn.
Detect the stop of R. Each signal management control unit 47
₁ to 47 _n is the signal stop detection control terminal _S 1 to S _n
And it has a signal stop detection terminal _T 1 through T _n. Force blank display signal DFF the normally high voltage (bar) is supplied from the control circuit 10 side to the first scan driver semiconductor integrated circuit ₄₆₁ of the signal stop detection control terminal S ₁ of the signal management control unit 47 _1, the Signal stop detection terminal T ₁
It is connected to the signal stop detection control terminal S ₂ of the second scan driver semiconductor integrated circuit 46 ₂ of the signal management control unit 47 _2. The second scan driver semiconductor integrated circuit 4
6 ₂ of the signal management control unit 47 ₂ of the signal stop detection terminal T
₂ is connected to the next stage of the signal stop detection terminal (e.g., signal stop detection control terminal S _n of the signal management control unit 47 _n of the _n). The signal stop detection terminal _{T n} of the signal management control unit 47 _n of the n-th scan driver ₄₆ 1 -46 _n
And the signal driver 24 _{1 to} 24 _n are connected to the forced blank control terminal DF (bar).

The signal management control unit 47 ₁ of the scan driver
To 47 _n, as shown in FIG. 2 are cascade-connected, configuration of each signal management control unit ₄₇ 1 to 47 _n are identical. Data signal to be detected signal of the signal management control unit 47 ₁ is applied to terminal CKB ₁ latch clock L
P, the detected signal of the signal management control unit 47 ₂ terminal CKB
₂ to the applied scanning start pulse (frame start signal) SP, the detected signal of the signal management control unit 47 _n is AC clock FR applied to the terminal CKB _n.

[0020] Here, by paying attention to the signal management control unit 47 ₁ will be described the configuration. Signal management control unit 47 ₁ includes a signal stop detection circuit 48 as a signal detecting means for detecting the stop of the detected signal, the signal delay circuit 49 and logic circuit 50
Is provided.

The signal stop detecting circuit 48 is switched by a latch clock LP as a signal to be detected, is a first N-type MOS transistor Tr ₁ constituting a transfer gate, an inverter INV ₁ for inverting the phase of the latch clock LP, The second N-type MOS transistor Tr ₂ , which switches by a reverse phase signal of the latch clock LP to form a transfer gate,
The first capacitor C ₁₁ charged and discharged by the opening and closing operation of the N-type MOS transistor Tr ₁ , the second N-type MOS transistor Tr ₁
The second capacitor _{C 12} is charged and discharged by the opening and closing operation of the transistor Tr _2, the discharge resistor _{R 1} discharges the charge of the capacitor _{C 12,} and a second capacitor _{C 12}
By comparing the charging voltage and the threshold V _TH and an inverter INV ₂ for outputting a charge level judgment signal. The first N-type MOS transistor Tr ₁ and the inverter INV ₁ and the second N-type MOS transistor Tr
Reference numeral ₂ denotes a series exclusive switching circuit. The first N-type MOS transistor Tr ₁ forms a selective charging switch for the first capacitor C ₁₁ , and the second N-type MOS transistor Tr _{2 transfers} the charge of the first capacitor C ₁₁ to the second capacitor C ₁₁ It constitutes a selective charge switch for distributing transferred to C _12.

The signal delay circuit 49 includes an inverter INV
Has _two of the connected reset terminal to an output R (bars) and grounded input terminal D (bar), a D-type flip-flop 49a to the clock input CK frame start signal SP, the output of the inverter INV ₂ Terminal R (bar) and flip-flop 49 connected to
It has an input terminal D (bar) connected to the output Q (bar) of a, and comprises a D-type flip-flop 49b which receives the frame start signal SP as a clock input.
The logic circuit 50 receives the forced blank signal D from the control circuit 10.
Q output of FF (bar) and flip-flop 49b is 2
It is composed of an AND circuit AND as an input.

[0023] Figure 3 a typical scan electrode driving circuit except the signal management control unit 47 ₁ of the scan driver 46 ₁ (logic unit)
FIG. In this logic section, multi-bit scan electrode drive cells 46 ₁₁ , 46 ₁₂ ... Which apply voltages in a line order corresponding to a large number of scan electrodes are formed in an array. FIG. 3 shows the scan electrode driving cells 46 ₁₁ and 46 _{12 of} the first bit and the second bit and their peripheral circuits.

[0024] Here focusing on the scan electrode driving cell 46 ₁₁ explaining the configuration, the scanning electrode driving cell 46
Reference numeral ₁₁ denotes a D-type flip-flop 46a in a shift register which is activated by the frame start signal SP and transfers the frame start signal SP to the next stage every time the scanning synchronization signal YSCL is input, and an n-th flip-flop 46 for the bit selection output Q.
Force blank display signal DF and row forced blank display control circuit 46b for performing a logic operation in consideration of the (bar), a logic system power source voltage and the output (V _{CC =} 5 v supplied from the terminal T _n of the scan drivers 46 _n of ) Is converted to a high-voltage logic amplitude by a row unit voltage level shift circuit 46c.
And the forced blank display signal DF
A total line forced blank display control circuit 46d that performs a logical operation in consideration of (bar), and a high-voltage AC clock FR having a high-voltage logic amplitude from a logic system power supply voltage (V _CC = 5V) a voltage level shift circuit 46e for AC clock to be converted to _H, the high pressure AC clock FR high voltage AC of _H reverse phase clock FR _H
Forward / reverse two-phase clock generation circuit 46f for inverting to (bar)
And a pair of the high-voltage alternating clock FR _H and the opposite-phase high-voltage alternating clock FR _H (bar) and a pair of the outputs O and O (bar) of the row unit voltage level shift circuit 46c in a cross-linked combination. a selection control signal generation circuit 46g for generating a selection control signal _C 1 -C _4, each selection control signals _C 1,
The scan electrode driving voltage V is determined by C ₂ , C ₃ and C ₄ .
₅ , V ₁ , V ₀ , and V ₄ are selectively supplied to the scanning electrodes.
Here, the row unit forced blank display control circuit 46b and the total row forced blank display control circuit 46d constitute a forced blank display control circuit. Incidentally, INV ₃ is an inverter to adjust the logic to the row unit forced blank display control circuit 46b of the forced blank display control signal DF (bar).

Next, the operation of this embodiment will be described with reference to FIG. When at time t ₀ is logic supply V _CC of the liquid crystal display device is turned on, similarly to the conventional reset signal of the power-on reset terminal number μs~ several ms pulse width to the RS of the liquid crystal module controller 12 MP
The liquid crystal module controller 12 is supplied from the U (not shown) side and is initialized. During this initialization period, various signals output from the liquid crystal module controller 12 are generally in a stopped state. In this period, since the forced blank display signal DFF (bar) is at a low voltage level (hereinafter, referred to as L level), the liquid crystal power supply circuit 28 is in a power-off state, and the liquid crystal drive power supply voltages V _{0 to} V ₅ are not applied. It is an occurrence state. Therefore, no DC component is applied between the liquid crystal electrodes during the initialization period, and the deterioration of the liquid crystal element is prevented.

[0026] Beyond this period, as shown in FIG. 4, the forced blank display signal at time t ₁ DFF (bar) is a high voltage level from the L level changes (hereinafter, H-level hereinafter), also a liquid crystal module controller Reference numeral 12 generates a frame start signal SP, a data signal latch clock LP, and an AC conversion clock FR. Now first the operation of the scan driver 46 ₁ of the signal management control unit 47 _1, the input terminal CKA _first signal delay circuit 49 is supplied with a frame start signal SP, also detection terminal CKB _first signal stop detection circuit 48 Is supplied with a data signal latch clock LP.

H level of data signal latch clock LP
In the period, the transistor of the signal stop detection circuit 48
Tr₁Is turned on and the transistor Tr₂Is off
It is in. Therefore, during this period, the capacitor C₁₁Is charged
Is done. L level period of data signal latch clock LP
, The transistor Tr of the signal stop detection circuit 48
₂Is turned on and the transistor Tr₁Is off
You. Therefore, during this period, the capacitor C₁₁Is charged
A part of the charge₁₂It is transferred to and charged. De
Data signal latch clock LP repeat pulse is generated
Capacitor C₁₂Since the charging voltage of
Inverter INV₂Input voltage is threshold V_THBelow
At time t₂Inverter INV₂Output INV
_OUTBecomes H level. Time t₂Previously
Inverter INV₂Output INV _OUTIs L level
Therefore, the D flip-flop of the signal delay circuit 49
The output Q of 49a is at the L level.
Output T of 0₁Is at the L level. Here, the output INV
_OUTIs at the H level,₂Then go out
The force Q does not go to the H level. D flip flop 49
b, 49a, frame star
1 frame period (T_F) ~ 2 frames around
Period (2T_F), The output Q is maintained at the L level.
At time t₃ And the output T of the logic circuit 50₁Is H level
become.

Scan driver 46₂Signal management system
Gobe 47₂Signal stop detection circuit 48₂Detection terminal C
KB₂Is supplied with a frame start signal SP.
Signal delay circuit 49₂Input terminal CKA₂Scan
Liver 46₁Coming from the cascade output terminal DO
Cascade input DI₂Barrel frame start signal SP
Is supplied. And the scanning driver 46₁The logic of
Output T of circuit 50₁Is the scanning driver 46₂Logic circuit
50 is cascaded. Signal stop detection circuit 4
8₂Capacitor C₂₁Is the frame start signal SP
Is charged by repeated pulses of Also run
Inspection driver 46_nSignal management control unit 47 in_nof
Signal stop detection circuit 48_nDetection terminal CKB_nExchange
The streaming signal FR is supplied and a signal delay circuit 49 is provided._nEntering
Force terminal CKA_nHas a scanning driver 46₂Cascade
Cascade input DI coming from the output terminal DO_nWas
A frame start signal SP is supplied. And
Scan driver 46₂Output T of the logic circuit 50₂Is running
Inspection driver 46_nCascaded to the logic circuit 50
Have been. Signal stop detection circuit 48_nCapacitor C
_n2Is charged by the repetition pulse of the AC signal FR.
It is. Data signal latch clock L as detected signal
P, the frame start signal SP and the AC conversion signal FR
Since the period and duty ratio are different, each scan driver
And inverter INV₁~ INV_n Comparison judgment time t
₃To match, etc., the capacitor C₁₁~ C
_n1, C₁₂~ C_n2And discharge resistance R₁~ R_nThe value of the
It is desirable to make the (time constant) mutually adjustable.
For this purpose, in this embodiment, as shown in FIG.
External terminals for connecting capacitors and resistors are provided in the scan driver.
Have been.

As described above, the logic power supply V_CCWhen throwing
Point t₀From the output T of the logic circuit₁~ T_nTo H level
Time t₃In the period until, each scan driver and
And signal driver forced display blank control terminal DF (bar)
ー) has an L level output T _nIs supplied
Thus, the liquid crystal display panel 22 is in a blank display state. One
In other words, the forced display blank control signal DF (bar) is at L level.
The forced blank display control circuit shown in FIG.
The scanning electrode driving cell 46 is controlled by controlling the paths 46b and 46d.
Of the selection switch 46h of the transistor F₁Only on
In the state, the voltage V is applied to the scan electrode.₅(0v) is applied
Thus, the voltage between the liquid crystal electrodes (liquid crystal applied voltage) is 0 V.
Time t₀~ Time t₃Period corresponds to the LCD drive prohibition period.
Hit. Time t₁The LCD power supply circuit 28
And the liquid crystal drive voltage V₀~ V₅ These occur
The voltage is supplied to the scan and signal drivers,
At the time of raising, shift in scanning and signal driver
Registers, etc. are in an undefined state. However, at time t
₃Liquid crystal display is blank controlled until
Abnormal drive of the panel can be avoided.

Next, when the output T _n becomes H level at time t _3, since the forced display blank control terminals DF of each scanning driver and signal driver (bar) H-level voltage is supplied, the scan driver and The liquid crystal display panel 22 is AC driven by the normal operation of the signal driver, and a display screen is drawn on the liquid crystal panel 22. B shown in FIG. 4 represents a liquid crystal driving period. And logic power-on of the scan and signal drivers and the liquid crystal power source circuit 28 at time t _1, which liquid crystal display panel 22 is driven from when t ₃ when delayed. Therefore, since power-on does not occur at the same time, an excessive power-rush current is suppressed. This is because the delay action of the signal delay circuit 49 having a delay time of 1 to 2 frame periods effectively functions in addition to the delay operation of the signal stop detection circuit 48 itself.

Here, the time during this liquid crystal driving period B
Point t₄Sent from the LCD module controller 12 side.
The output of the output data signal latch clock LP
For example, suppose that it stopped. Data signal latch clock LP
Scan driver 46 during output of ₁Signal stop detection circuit 4
8₁Of the second capacitor C₁₂Is fully charged
However, when the clock LP stops, the second capacity
TA C₁₂To the first capacitor C₁₁Charge transfer from side
Or the second capacitor C₁₂The charge of
Discharge resistance R₁Discharges rapidly with a predetermined time constant
Inverter INV₂Input voltage gradually rises
You. Its input voltage is equal to its threshold V_THExceeds
Force voltage INV_OUTAt time t₅At L level.
This logic change causes the signal delay circuit 49₁Is reset
Since the output Q is at the L level, the forced display
Link control signal DF (bar) is at L level
Instead of the logic circuit 50₁Output T₁Is the time t₅In L
Level. This output T₁ Is the scanning driver 46₂of
Logic circuit 50₂Cascade input to
Even when the frame start signal SP is being output, its logic circuit 50
₂Output T₂Becomes L level. Further, the output T₂
Is the scanning driver 46_nLogic circuit 50_nCascade to
Input, so that the
Logic circuit 50_nOutput T_nBecomes L level. this
Output T_nIndicates forced display on the LCD module 46 side
Since it corresponds to the blank control signal DF (bar),
LCD blanking circuits 46b and 46d
The channel 22 enters a blank display state. That is, as shown in FIG.
Of the selection switch 46h of the scan electrode driving cell 46.
Jista F₁Only in the ON state, and the voltage V
₅(0v) is supplied, so that the voltage between the liquid crystal electrodes is 0v
Is maintained. Therefore, the data signal latch clock L
Even if P stops for some reason, the liquid crystal element
Since it is not driven by the component, liquid crystal deterioration is prevented beforehand.
You. Further, the frame start signal SP or the alternating signal F
Even if R stops for some reason, the output T_nIs L
The liquid crystal is similarly prevented from being deteriorated.
You. In the liquid crystal driving inhibition period A, the frame
As long as the start signal SP and the alternating signal FR continue
And the second capacitor C₂₂And C_n1Is in the charging state
Inverter INV₂, INV_nOutput of H level
It is.

Time t₆Data signal latch clock
When the lock LP begins to appear again, the second
Capacitor C₁₂Is charged and the inverter INV₁
Output INV_OUTBecomes H level. Output INV
_OUT1 to 2 frames from the time when
After the period, a signal delay circuit 49 functioning as a timer₁
Output Q at time t₇At H level. By this
And the logic circuit 50₁Output T₁Becomes H level
Together with this, the logic circuit 50₂, 50_nOutput T
₂, T_nBecomes H level. Therefore, the liquid crystal display module
The display blank control signal DF (bar)
-) Changes to the H level, the liquid crystal display panel 22
The crystal driving period B starts.

[0033] Finally, when the forced display blank control signal DFF of the liquid crystal display controller 12 side (bar) becomes the L level at time _{t 8,} the output _{T 1} of the logic circuit 50 ₁ is L
Therefore, the outputs T ₂ and T _{n of} the logic circuits 50 ₂ and 50 _n are also at the L level. Therefore, the forced display blank control signal DF on the liquid crystal display module unit 20 side
(Bar) becomes L level, and the liquid crystal display panel 22 enters the display off period C.

[0034]

Embodiment 2 FIG. 5 is a block diagram showing a liquid crystal display device according to Embodiment 2 of the present invention. In FIG. 5, the same portions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The plurality of scan drivers 76 _{1 to} 76 _n constituting the scan electrode drive circuit (X driver) 76 of the liquid crystal display module unit 70 of this embodiment are the same signal management control units as those of the first embodiment. 77 _{1 to} 77 _n , but as shown in FIG.
₁ to 77 _n in the liquid crystal drive voltage _V 0 ~V ₅ controls the timing of the power-on / off of the liquid crystal power source circuit 28 should generate a power supply power on / off control circuit ₇₈ 1 -
78 _n are added.

Power supply power on / off control circuit 78₁~
78_nIs a logic circuit 50₁Input terminal S₁~ S
_nINV that inverts the signal coming into the inverter₃
And two-stage D flip-flops 78a and 78b
And its output Q and terminal P₁~ P _nSignal coming from
And a logic circuit 78c that takes the logic of
The signal delay circuit 79 of each signal management control unit 77 is implemented as
The two-stage D flip-flop of the signal delay circuit 49 according to Example 1
The third stage D flip-flop is attached to flops 49a and 49b.
This is a configuration in which a step 79c is additionally connected.

First scanning driver 76₁Logic circuit 7
8c input terminal P₁Is the logic side power supply voltage V_CCof
A power on / off signal is supplied and the second scan
Liver 76₂Terminal P₂Has a first scanning driver 7
6₁Power supply on / off control circuit 78₁
Output PF₁Are supplied in cascade. Also the
n scan drivers 76_nTerminal P_nThe first
2 scan driver 76 ₂Power on / off
Control circuit 78₂Output PF₂Supplied in cascade
Have been. Then, the n-th scan driver 76_nNo electricity
Source power on / off control circuit 78_nOutput PF_nIs
To the power off terminal POFF (bar) of the liquid crystal power supply circuit 28
Supplied.

The liquid crystal power supply circuit 28 has the same configuration as the conventional one,
As shown in FIG. 7, a voltage conversion circuit 2 that generates a high voltage (20 to 40 V) boosted based on a V _CC (5 V) power supply voltage
8a, an npn transistor 28b for controlling on / off depending on a voltage value supplied to a power-off terminal POFF (bar), and a power switch for turning on / off in conjunction with on / off operation of the transistor 28b Pnp
And type transistor 28c, a smoothing capacitor 28d interposed between the ground and its collector, voltage divider circuit 28 which outputs a liquid crystal driving voltage V ₀ ~V ₅ from the charging voltage
e.

Next, the operation of the above embodiment will be described with reference to FIG.
It will be explained while doing. Time t₀At power switch S
W is closed and the logic power supply V of the liquid crystal display device is_CCThrow
Then, as in the first embodiment, the liquid crystal module controller
The power-on reset terminal RS of the roller 12 has several μs to several μs.
ms reset signal is supplied from MPU side.
Then, the liquid crystal module controller 12 is initialized.
Therefore, the output signal from the liquid crystal module controller 12 is
The signal is generally at rest. During this period,
Gic power supply voltage V_CCIs the first scan driver 76₁of
It is supplied to one input of a logic circuit 78c as an AND circuit.
However, the data signal latch clock LP has not yet appeared.
The output PF₁Is in the L level state. This result
As a result, the second scan driver 76₂Output PF₂Also L
And the nth scan driver 76 _nOutput PF
_nIs also at the L level, the power of the liquid crystal power supply circuit 28 is
The off terminal POFF (bar) is maintained at the L level state.
I have. Therefore, the transistor 28b shown in FIG.
Since the potential is at the L level (0 V), the boosted voltage is smooth.
It is not supplied to the capacitor 28d, and therefore the liquid crystal driving voltage
V₀~ V₅Does not occur. As in the first embodiment,
During the initialization period, no DC component is applied between the liquid crystal electrodes,
The deterioration of the crystal element is prevented.

Next, as shown in FIG.₁With liquid crystal
Various signals are generated from the module controller 12.
You. Is the forced blank display signal DFF (bar) at L level?
From the frame start signal SP,
Data signal latch clock LP and AC clock FR
Occurs. As described in the first embodiment, the data signal
Inverter INV by the start of appearance of the switch clock LP
₂Output INV_OUT At time t₂At H level
You. Therefore, the output of the power on / off control circuit 78b
Q is time t₂One or two frame periods later
t₃At the H level, the output PF of the logic circuit 78c
₁Becomes H level. Thereby, the second and n-th scans
Driver 76₂, 76_nOutput P of the logic circuit 78c
F₁, PF go to H level in conjunction with
Power off terminal POFF (bar) of circuit 28 is at H level
It is urged to. As a result, the transistor 28b is turned on.
The base-emitter of the transistor 28c.
The transistor 28c is also turned on by the voltage drop of the inter-resistance.
State, the smoothing capacitor 28d is charged, and the liquid crystal drive
Dynamic voltage V₀~ V₅Occurs. Time t₃From next
Time t when the frame start signal SP arrives₄Until
Output Q of D flip-flop 79c remains at L level
It is. Signal delay circuit 79 in this embodiment₁D
The number of flip-flop stages is the power on / off control circuit
78₁One step higher than that of
The output Q of the flop 79c is the output Q of the D flip flop 78b.
One frame period T_FJust delayed to H level
This is because that. As a result, the output T ₁, T₂, T_n
Are both at the H level.
Blank display signal DF (bar) on display module side
Changes from the L level to the H level, which causes the liquid crystal display
The driving voltage V is applied to the scanning electrodes and signal electrodes of the panel 22. ₀
~ V₅Is supplied with power to enter the liquid crystal display mode.

For example, the liquid crystal driving voltage V₀~ V₅Departure
When the liquid crystal display panel 22 is driven simultaneously with the production,
Power supply for the display panel and the scanning and signal driver
An electric rush current is induced. However, the book
In the embodiment, the time t₃ Is the liquid crystal drive voltage V₀~ V
₅Is generated, one frame period T_FAfter the LCD drive
Operation starts, the time difference of the power supply
Current can be distributed, preventing power down and reducing power capacity
The LCD panel and drivers, etc.
Contribute to protection. In addition, the power supply control described above is a development
The burden on the system is reduced and the LCD module
It is not necessary to increase the number of signal wirings between channels. Furthermore, power supply capacity
This leads to the use of inexpensive power supplies.
Next, at the time t in the liquid crystal driving period B,₅In the liquid crystal module
Data sent from the queue controller 12
Assuming that the oscillation of the signal latch clock LP has stopped,
As in the first embodiment, the inverter INV₂Input voltage is higher
Rises and its output voltage INV_OUTAt time t₆In L
And the output T₁, T₂, T_n Is also at L level
You. As a result, the forced display block on the liquid crystal display module side
Since the rank control signal DF (bar) becomes L level,
The crystal display panel 22 is in a blank display state. Example 1
The same effect as described above is exerted. Inverter INV₂of
Output voltage INV_OUTBecomes L level, the output PF
₁, PF₂, PF _nAlso at the L level at the same time
Power-off terminal POFF (bar) of crystal power supply circuit 28 is L
Changes to the liquid crystal drive voltage V₀~ V₅Occurrence of
Stops.

[0042] When the data signal latch clock LP at time _{t 7} begins to reappear in the same manner as in Example 1, the time the output voltage _{INV OUT} of the inverter INV ₂ is t
₈ at the H level, and as described above, at this time t
Output PF from ₈ at the time _{t 9} after a 1-2 frame period
₁ , PF ₂ and PF _n are also at the H level. As a result, the power-off terminal POFF (bar) of the liquid crystal power supply circuit 28 changes to the H level, so that the liquid crystal drive voltage V ₀ to
V ₅ is generated, they are applied to the driver side. Then, as described above, the outputs T ₁ , T ₂ , and T _n are delayed from the time t ₉ by one frame period _{TF at} the time t.
_{At 10} , the liquid crystal display panel 22 changes to the H level, and the scanning electrodes and the signal electrodes of the liquid crystal display panel 22 are supplied with liquid crystal driving voltages V _{0 to} V ₅ , and the liquid crystal display mode is restarted.

Time t₁₁On the LCD controller 12 side
Display blank control signal DFF (bar) is at L level
, The output T₁, T₂, T_nAlso L level
Therefore, the forced display brand on the liquid crystal display module 70 side
The control signal DF (bar) also becomes L level, and the liquid crystal display
The channel 22 enters the display off period C. At this time t₁₁From
Time point t after 1-2 frame periods₁₂Power on / off with
Control circuit 78₁Output of D flip-flop 78b
Q changes to L level and the output PF₁, PF₂ , PF
_nAlso at L level. As a result, the liquid crystal power supply circuit 28
The power off terminal POFF (bar) also goes to L level
And the liquid crystal drive voltage V₀~ V₅Stops occurring. This
, The forced display screen on the liquid crystal display controller 12 side.
When the link control signal DFF (bar) goes low, the liquid crystal
After a certain period of time after the drive stops,
The application of the crystal voltage is stopped. Such a power-off system
Logic power supply V_CCAnd LCD drive power supply
V₀~ V₅Potential relationship is maintained and the driver
Raw bipolar current and through current are suppressed, and the liquid crystal display
The protection of the panel and the driver can be achieved.

In this embodiment, the power of the liquid crystal power supply circuit 28 is turned on after the clock is supplied to the liquid crystal module side, and the power of the liquid crystal power supply circuit 28 is turned off by stopping the output of the clock. Since the rush current is dispersed or time-differenced by such an auto sequence of energizing the power supply, the liquid crystal panel, the driver, and the liquid crystal power supply circuit constituting the liquid crystal display module can be protected as described above.

In each of the above embodiments, the signal management control unit is incorporated in the scanning driver LSI. This is because the number of input / output signal lines is smaller than that of the signal driver LSI and the display frame area is smaller. This is because the width is large, so that the circuit board on which the signal management control unit is mounted has a large area margin. In this embodiment, the display device of the simple matrix liquid crystal panel has been described. However, the present invention is not limited to this, and the active device is not limited thereto.
The invention can be applied to a matrix type liquid crystal display device. In such a case, it is preferable to provide a signal management control unit on the gate driver LSI side. In that case, when the clock stops, the gate driver LSI is controlled so that all gates are turned on, and the source driver is controlled so that the data side outputs the same potential as the common side,
All pixel electric fields are set so as to be in a non-applied state.
Furthermore, the present invention is applicable not only to displays but also to display devices whose display quality is degraded by DC driving, such as electronic devices using liquid crystal devices and plasma displays, such as liquid crystal optical arithmetic devices. is there.

In each of the above embodiments, means for detecting an abnormality of a signal supplied from the liquid crystal module controller 12 and means for removing an abnormal state of the signal before or after the fact are provided on the liquid crystal module side. Has been
Some components of these means may be provided on the liquid crystal module side, and the remaining components may adopt a shared configuration provided on the system (controller) side. For example, a plurality of signals (S
P, LP, FR) have different frequencies and pulse duties.
The signal is converted to a single composite signal using a usive OR gate, sent back to the system side, monitored for an abnormal state by a decision circuit, and the output is used to remove the abnormal state.
It is possible to adopt a configuration in which an indicator is displayed by using a display body different from the LCD module side. The return output terminals T _n of the scan drivers 46 _n of the embodiment shown in FIG. 1 to the system side, the logic system and the liquid crystal-based system for controlling power on / off at a certain procedure (sequence) can alternatively employed.

Another cause of the deterioration of the liquid crystal panel is a voltage value shift of the liquid crystal driving voltages V _{0 to} V ₅ due to an abnormality of the voltage dividing circuit 28 e in the liquid crystal power supply circuit 28 shown in FIG. For example, it is considered that the liquid crystal panel is driven by an effective DC component and deteriorates. Since these abnormalities can also be detected as fluctuations of the power supply current and the power supply voltage, the abnormal state can be removed by the above-described abnormality removing means.

[0048]

As described above, in the flat display device according to the present invention, when the signal transmitted from the display control unit stops oscillating, the DC drive of the liquid crystal is forcibly performed by the signal management control means on the display module side. Will be suspended. For this reason,
The display body can be prevented from being deteriorated due to the DC drive. Also, the power supply rush current can be reduced. The present invention is applicable not only to liquid crystal display devices but also to plasma display devices and the like. The present invention is suitable for use in a display device in which the display quality and life of the display body cause irreparable deterioration due to an abnormality in the drive signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a signal management control unit of each scanning driver and a connection relationship between the drivers in the embodiment.

FIG. 3 is a circuit diagram showing a scan electrode drive cell of the scan driver in the embodiment.

FIG. 4 is a timing chart illustrating the relationship between various signals in the liquid crystal display module for explaining the operation of the embodiment.

FIG. 5 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a signal management control unit of each scanning driver and a connection relationship between the drivers in the embodiment.

FIG. 7 is a circuit diagram showing a configuration of a liquid crystal power supply circuit in the embodiment.

FIG. 8 is a timing chart showing the relationship among various signals in the liquid crystal display module for explaining the operation of the embodiment.

FIG. 9 is a block diagram illustrating a configuration of a conventional liquid crystal display device.

[Explanation of symbols]

10 ... LCD controller 12,40,70 ... liquid crystal module controller 20 ... flat-shaped liquid crystal display module unit 22 ... liquid crystal display panel (matrix liquid crystal display device) ₂₄ 1 to 24 m _... signal electrode driver semiconductor integrated circuits 24 ... Signal electrode drive circuit (X driver) 26, 46, 76... Scan electrode drive circuit (Y driver) 26 _{1 to} 26 _n , 46 _{1 to} 46 _n , 76 ₁ to
76 _n ... scanning electrode driver semiconductor integrated circuit 28 ... liquid crystal power supply circuit 28a ... voltage conversion circuit 28b ... npn transistor 28c ... pnp transistor 28d ... smoothing capacitor 28e ... voltage dividing circuit 30 ... cables 46 ₁₁ and 46 ₁₂ ... scanning electrodes D driving cells 46a, 49a, 49b, 78a, 78b, 79c ... D
Type flip-flop 46b ... row unit forced blank display control circuit 46c ... row unit voltage level shift circuit 46d ... total row forced blank display control circuit 46e ... voltage level shift circuit 46f ... forward / reverse two-phase clock generation circuit 46g ... selection control signal Generation circuit 46h selection switches 47, 47 _{1 to} 47 _n , 77 _{1 to} 77 _n signal management control section 48 signal stop detection circuits 49, 79 signal delay circuit 50 logic circuit 51 sequence processing circuit 78 _{1 to} 78 _n power supply power on / off control circuit 78c logic circuit Tr ₁ first N-type MOS transistor Tr ₂ second N-type MOS transistor INV ₁ , INV ₂ , INV ₃ inverter C ₁₁ first capacitor C _{12 ...} second capacitor R 1 _... discharge resistor the aND ... aND circuit CKB1 CKBn ... terminal S ₁ to S n _... signal stop detection control terminal T ₁ through T n _... signal stop detection terminal V ₀ ~V 5 _... liquid crystal driving voltages (reference voltages) D0 to D7 ... data signal XSCL ... pixel clock (shift clock Pulse) YSCL ... Scan line synchronization signal LP ... Data signal latch clock FR ... Alternating clock DF (bar) ... Display off signal (forced blank display signal) SP ... Scan start pulse (frame start signal) POFF (bar) ... Power OFF terminal

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 16, 2000 (2000.2.1
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4

Claims (26)

[Claims] 1. A flat display module module and a display control section for controlling the flat display module module are separately arranged, and the flat display module module section has a flat display body and a display body driving means for driving the flat display body. A flat display device, comprising signal management control means, wherein the signal management control means detects signal abnormality detection of a first signal transferred from the display control unit side, based on the detection signal. And a sequence processing means for changing the signal form of the flat display module section. 2. The flat display device according to claim 1, wherein the signal management control means is provided on the flat display module section. 3. The signal detection means according to claim 1, wherein said signal detection means is a signal stop detection means for detecting stop of said first signal, and said sequence processing means is said display based on an output of said signal stop detection means. A flat display device, comprising forcible stop control means for setting and controlling a display body application voltage to be supplied to the flat display body of the body drive means to zero. 4. The forcible stop control means according to claim 3, wherein said forcible stop control means has first signal delay means for delaying a second signal transferred from said display control unit by an output of said signal stop detection means. A flat display device characterized by the above-mentioned. 5. The flat display device according to claim 4, wherein the forcible stop control means has a control terminal for a third signal whose output is to be controlled. 6. The method according to claim 5, wherein n is a positive integer,
A flat display device comprising n signal management control means, wherein the types of detected signals to be input to each signal management control means as the first signal are different from each other. 7. The method according to claim 6, wherein k = 1,..., N-1.
Then, the control output of the k-th signal management control means is changed to the k-th signal management control means.
A third signal of the + 1st signal management control means, and display ON / OFF of the display drive means is controlled based on a control output of the nth signal management control means. Flat display device. 8. The signal stopping device according to claim 4, wherein the first signal delay unit receives the frame start signal as the second signal and stops the signal when N is a positive integer. A flat display device comprising N stages of D flip-flops which can be set / reset based on an output of a detecting means. 9. The power supply according to claim 7 or 8, wherein the power supply controls on / off of a display power supply for generating a display drive voltage based on an output of the signal stop detection means and a fourth signal. A flat display device comprising a control means on the flat display module side. 10. The power supply control unit according to claim 9, further comprising a second signal delay unit that delays a second signal transferred from the display control unit based on an output of the signal stop detection unit. Flat display device. 11. The signal processing apparatus according to claim 10, wherein the second signal delay means receives a frame start signal as the second signal and sets M as a positive integer based on an output of the signal stop detection means.・ M (<
N) A flat display device comprising D flip-flops. 12. The flat display device according to claim 1, wherein the flat display body is a liquid crystal display panel. 13. The flat display device according to claim 1, wherein the flat display body is a plasma display panel. 14. A display driver which is provided on the flat display module section and supplies a display drive voltage to the flat display based on various signals from the display controller, the display driver being transferred from the display controller. Signal control means including signal detection means for detecting occurrence of abnormality of the first signal, and sequence processing means for changing the signal form of the flat display module based on the detection output. A display body driving device characterized by the above-mentioned. 15. The flat display element according to claim 14, wherein said signal detecting means is a signal stop detecting means for detecting a stop of said first signal, and said sequence processing means is based on an output of said signal stop detecting means. A display body driving device, which is forcible stop control means for setting and controlling a display body application voltage to be supplied to the power supply to zero. 16. The apparatus according to claim 15, wherein said forced stop control means has first signal delay means for delaying a second signal transferred from said display control unit by an output of said signal stop detection means. Characteristic display body driving device. 17. The display driving apparatus according to claim 16, wherein said forced stop control means has an input terminal of a third signal whose output is to be controlled. 18. The signal delay unit according to claim 17, wherein a frame start signal is input as the second signal, and when N is a positive integer, set / reset is performed based on an output of the signal stop detection unit. A display body driving device comprising N possible stages of D flip-flops. 19. The display power supply unit according to claim 15, wherein the signal management unit generates a display driving voltage based on an output of the signal stop detection unit and a fourth signal. And a power supply control means for controlling power on / off of the display device. 20. The power supply control unit according to claim 19, wherein the power supply control unit includes a second signal delay unit that delays a second signal transferred from the display control unit based on an output of the signal stop detection unit. Display driving device. 21. The signal processing apparatus according to claim 20, wherein the second signal delay means receives a frame start signal as the second signal and sets M as a positive integer based on an output of the signal stop detection means.・ M (<
An N) -stage D flip-flop. 22. The display device driving device according to claim 14, wherein the display device driving device is a liquid crystal driving device for driving a liquid crystal display panel. 23. The display device driving device according to claim 22, wherein the liquid crystal driving device is a semiconductor integrated circuit. 24. The display driver according to claim 23, wherein the semiconductor integrated circuit is a Y driver. 25. The display driver according to claim 24, wherein the Y driver is a scan driver of a simple matrix liquid crystal display. 26. The display driver according to claim 24, wherein the Y driver is a gate driver of an active matrix liquid crystal display.