JP2000100189A - 1-chip microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the life of a non-volatile memory caused by read failure by changing a read voltage being stored at the specific address region of the non-volatile memory by a control circuit in advance based on the reference result of a group of nonvolatile memories for reference. SOLUTION: A group of non-volatile memories 40 for reference are arranged at the end part of memory arrays 41 and 42 at left and right sides. Data is written to all of the group of non-volatile memories 40 for reference with inferior characteristics as compared with the group of non-volatile memories for reference. Then, when a control circuit 44 detects that state changes from this state to that where data has been erased via a sense amplifier 43, the control circuit 44 changes to a desired voltage out of read voltages being stored at a predetermined address region of the group of non-volatile memories in advance. More specifically, data is written to the group of non-volatile memories 40 with inferior characteristics and control is made so that a voltage to be applied to a word line can be lowered when data has been erased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer having a built-in electrically erasable nonvolatile memory (for example, a flash memory).

[0002]

2. Description of the Related Art FIG. 7 is a cell structure diagram showing a programmed state of a general split gate type nonvolatile memory, wherein (1) is a control gate, (2) is a floating gate, (3) is a drain, and ( 4) indicates a source.

When the nonvolatile memory shown in FIG. 7 is set to a program state, for example, 2 volts, 0 volt, and 1 volt are applied to the control gate (1), the drain (3), and the source (4), respectively.
Apply a voltage of 2 volts. Then, the capacity between the control gate (1) and the floating gate (2) and the capacity between the floating gate (2) and the source (4) are capacitively coupled (capacitance between the control gate (1) and the floating gate (2)> floating). Gate (2)
And the capacitance between the source (4)) and the capacitive coupling ratio, the floating gate (2) is not actually applied with a voltage, but as a result, is in an equivalent state to the application of a high voltage of, for example, 11 volts.

As a result, a channel is formed between the drain (3) and the source (4) where electrons continue, and hot electrons in the channel are converted into an insulating film (not shown).
, And is injected into the floating gate (2), and the floating gate (2) is in a negatively charged state. This is the program state of the nonvolatile memory cell. FIG.
Is a cell structure diagram showing a read state of the nonvolatile memory in a program state, and FIG. 9 is a cell structure diagram showing a read state of the nonvolatile memory in a non-program state.

When the nonvolatile memory shown in FIGS. 8 and 9 is set to the read state, for example, 5 volts, 2 volts, and 0 volts are applied to the control gate (1), the drain (3), and the source (4), respectively. Apply. In the case of FIG. 8, since electrons are injected into the floating gate (2),
No channel is formed between the drain (3) and the source (4), and the nonvolatile memory cell is turned off. On the other hand, in the case of FIG. 9, since no electrons exist in the floating gate (2), a channel is formed between the drain (3) and the source (4), and the nonvolatile memory cell is turned on.

FIG. 6 is a block diagram for outputting a logical value "0" or "1" according to a program state of a nonvolatile memory cell, (5) is a nonvolatile memory cell, and (6)
Denotes a sense amplifier. The sense amplifier (6) has a voltage value of 0 volt (logical value "0") or a voltage value of 5 volt (5 volts) depending on the comparison result between the output current of the nonvolatile memory cell (5) and the reference current Iref. (Logical value "1").

When the nonvolatile memory cell (5) is in the programmed state as shown in FIG. 8, the sense amplifier (6) detects that the output current of the nonvolatile memory cell (5) is smaller than the reference current Iref, and performs a logic operation. The value "0" is output. on the other hand,
When the nonvolatile memory cell (5) is not in the programmed state as shown in FIG. 9, the sense amplifier (6) detects that the output current of the nonvolatile memory cell (5) is larger than the reference current Iref, and performs the logic operation. The value "1" is output.

FIG. 10 is a cell structure diagram showing an erased state of a nonvolatile memory, for example, a control gate (1).
14 volts and 0 volts to the drain (3) and source (4). Then, the floating gate (2)
The electrons injected into the semiconductor device move to the control gate (1) via the insulating film. However, since the drain (3) and the source (4) have the same potential, no channel is formed. This is the erased state of the nonvolatile memory cell.

Thus, the fixed voltage is applied to the control gate (1), the drain (3), and the source (4) for a fixed time according to the program state, the read state, and the erase state of the nonvolatile memory. Had been applied.

[0010]

In a one-chip microcomputer having such a built-in nonvolatile memory, when the nonvolatile memory is used as a ROM, data retention characteristics are important.

In particular, in the memory cell array structure shown in FIG. 11, except for the voltage applied to the non-selected cells indicated by the dotted circle, except for the level of the voltage (5V) applied to the control gate (1) (word line WL), This is the same as the above-described erased state (the applied voltage at this time is 14 V as described above). Therefore, the electrons injected into the floating gate (2) gradually move to the control gate (1) side due to the repetition of the read operation, causing a read failure. In particular, it was remarkable when the power supply voltage was high.

Accordingly, an object of the present invention is to provide a one-chip microcomputer capable of controlling the magnitude of a read voltage of a nonvolatile memory before a read failure occurs.

[0013]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and has been made in consideration of the above circumstances, and has been made in consideration of the above circumstances. In the microcomputer, a reference non-volatile memory group (40) having inferior characteristics to the non-volatile memory (7) in the memory cell array is provided, and a reference result of the reference non-volatile memory group (40) is obtained. Based on the control circuit (4
According to 4), the read voltage previously stored in the specific address area of the nonvolatile memory (7) is changed.

The reference nonvolatile memory group (4)
0) is a cell structure having a longer gate length or a shorter gate width than the internal nonvolatile memory (7), and is provided for all the reference nonvolatile memory groups (40). , The program state (“0” state).

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described below with reference to the drawings.

FIG. 2 is a block diagram showing a one-chip microcomputer according to the present invention.

In FIG. 2, reference numeral (7) denotes a nonvolatile memory (for example, a nonvolatile memory), which can electrically erase data and can repeatedly write and read data.
It mainly stores program data for controlling the operation of the one-chip microcomputer. In the memory cell (5) constituting the nonvolatile memory (7), data writing, reading, and erasing are normally performed in the states shown in FIGS. The control data A and the nonvolatile memory (7) for controlling the magnitude or time of the write voltage of the nonvolatile memory (7) are respectively stored in the specific address areas a, b, c, and d of the nonvolatile memory (7). )) Control data B for controlling the magnitude or time of the erase voltage, control data C for controlling the magnitude or time of the read voltage,
Control data D for controlling the magnitude of the reference voltage Vref (corresponding to the reference current Iref) of the sense amplifier (6) when reading the nonvolatile memory (7) is written in advance.

(8) is a program counter for addressing the nonvolatile memory (7).
(9) is an instruction register which holds data read from the nonvolatile memory (7).
(10) is an instruction decoder which decodes data held in the instruction register (9) and
It outputs a control signal for executing various operations of the chip microcomputer. (11A) (11
B) (11C) is a register for holding the control data A, B, C of the addresses a, b, c held in the instruction register (9) via the data bus (13). The address d of the nonvolatile memory (7)
Is the control data for reference at the time of reading. This control data D is directly connected to the reference voltage section of the sense amplifier (6), and the reference voltage Vref is set simultaneously with the initialization of the one-chip microcomputer. Configuration. Further, the erasing operation of the nonvolatile memory (7) is executed in units of one page (for example, 128 bytes), and the control data A,
There is no inconvenience that B, C, and D are collectively erased simultaneously with the erasing operation.

FIG. 3 is a circuit block diagram for controlling the write time, the erase time, and the read time. still,
It is assumed that control data A, B, and C for controlling a writing time, an erasing time, and a reading time are written in advance at addresses a, b, and c of the nonvolatile memory (7). In FIG. 3, reference numeral (14) denotes a counter, which is configured by cascade-connecting a plurality of T flip-flops. AND gate (15) (16) (17) and OR
The gate (18) forms a switching circuit, and the AND gate (1
5) Specific frequency division outputs X1, X2, X3 (for example, 0.4 msec, 0.8 msec, 1.6 msec) of the counter (14) are applied to one input terminal of (16) and (17). Register (11) has frequency-divided outputs X1, X
Control bit Y for selecting one of X2 and X3
1, Y2 and Y3 are held. Each bit of the register (11A) is connected to the other input terminal of the AND gates (15), (16), and (17). Control bits Y1, Y2, Y3
Becomes a logical value "1" when selecting the divided outputs X1, X2, X3. Therefore, the control bit Y of the logic value "1"
1, Y2, and Y3, corresponding to any one of the divided outputs X1,
One of X2 and X3 is output from the OR gate (18), and the voltage application time in FIG. 7 is controlled. For example, depending on the write characteristics of the nonvolatile memory (7), the voltage application time of 0.4 msec is not sufficient, but 0.8 msec.
Is sufficient, only the control bit Y2 becomes the logical value "1", and the writing is executed based on the divided output X2 of the counter (14). The registers (11B) and (11C) for the erase operation and the read operation are also
A configuration similar to that of FIG. 3 is provided.

FIG. 4 is a circuit block diagram for controlling a write voltage, an erase voltage, and a read voltage. still,
The control data A, B, and C for controlling the write voltage, the erase voltage, and the read voltage are stored at addresses a, b, and c of the non-volatile memory (7), respectively. It is assumed that the information is written according to the characteristics. In FIG. 4, (19) is a high voltage generation circuit,
A voltage VPP is generated. The output of the high-voltage generating circuit (19) is connected to the cathode of a Zener diode (20), and the anode of the Zener diode (20) is connected to p.
, Q, and r (p>q> r) diode series bodies (21), (22), and (23) are connected in parallel. Further, between the anode of the Zener diode (20) and the diode series bodies (21), (22) and (23), the Zener diode (20) is connected between the output of the high voltage generating circuit (19) and the ground. Diode series body (21) (22) (2
NMO for selectively connecting or disconnecting with any one of 3)
The drain-source paths of the S-transistors (24), (25), (26) are inserted, and the NMOS transistors (24), (2)
5) The gate of (26) is connected to and controlled by each bit of the register (11A). When the NMOS transistors (24), (25) and (26) are off, the NMOS transistors
NMOS when only transistor (24) is off
NMOS when only transistor (25) is off
The output VPP of the high voltage generating circuit (19) becomes lower in the order in which only the transistor (26) is turned off. For example, according to the write characteristics of the nonvolatile memory (7), the write voltage is NM under the condition that the voltage application time is fixed.
When the level when the OS transistor (26) is turned on is not sufficient, but when the level when the NMOS transistor (25) is turned on is sufficient, only the control bit Y2 has the logical value "1", and FIG. The source voltage is controlled. The register (1
1B) and (11C), the same configuration as that of FIG. 4 is provided. In this case, the control gate voltage in FIG. 10 is controlled.

FIG. 5 shows the reference voltage Vr of the sense amplifier (6).
It is a circuit block diagram for controlling ef. Specifically, the output current of the memory cell (5) and the reference current Iref are subjected to current-voltage conversion inside the sense amplifier (6). Therefore, actually, the configuration is such that the reference voltage Vref is applied without applying the reference current Iref to the sense amplifier (5).
Note that the reference voltage V is applied to the address d of the nonvolatile memory (7).
It is assumed that control data D for controlling ref has been written in accordance with the characteristics of the nonvolatile memory (7).
The resistances (27), (28), (2) are connected between the power supply VDD and the ground.
9) and (30) are connected in series, and the drains of the NMOS transistors (31), (32) and (33) are connected in series resistance (2).
7) Connected to the connection points of (28), (29), and (30), the sources are commonly connected, and the gate is directly controlled by control bits Z1, Z2, and Z3 of address d. The reference voltage Vref decreases in the order of turning on the NMOS transistors (31), (32), and (33). For example, the reference voltage Vref is set to N according to the readout characteristics of the nonvolatile memory (7).
When the value when the MOS transistor (33) is turned on is not sufficient, but when the value when the NMOS transistor (32) is turned on is sufficient, only the control bit Z2 may be set to the logical value “1”. Thus, an accurate logical value can be obtained from the sense amplifier (6).

Hereinafter, a configuration which characterizes the present invention will be described with reference to FIG.

FIG. 1 is a diagram showing a layout of a memory cell array to which the present invention is applied. In FIG.
Reference numerals 1) and (42) denote memory cell arrays on the left and right sides, respectively, and a nonvolatile memory group for reference (4
0) is arranged. The non-volatile memory group (40) for reference has a cell structure with a longer gate length or a shorter gate width than the non-volatile memory (7). ) Can be a non-volatile memory having a structure inferior to that of () (in this case, data is easily erased). Further, (43) is a sense amplifier for reading the nonvolatile memory group for reference (40), and (44) is a control circuit.

Here, in the nonvolatile memory (7) configured as described above, the read operation is repeated, thereby suppressing a read failure that has conventionally occurred. ), A reference nonvolatile memory group (40) having inferior characteristics to that of the reference nonvolatile memory group (40) is provided, and all of the reference nonvolatile memory groups (40) are in a programmed state (the state of "0" in which data is written). From the "0" state to the "1" state (a state in which data is erased)
Is detected by the control circuit (44) via the sense amplifier (43), the control circuit (44) applies the read voltage stored in the specific address area C of the nonvolatile memory (7) in advance. The control is performed so that the desired read voltage is changed from the data.

Each time the read operation to the nonvolatile memory (7) in the memory cell array is repeated, the reference nonvolatile memory (4) connected to the same word line WL
The read operation is also performed for 0). In this way, when it is detected that the data in the reference nonvolatile memory (40) has been erased while the sequential read operation is repeated, the read voltage is reduced via the control circuit (44). change. That is, data is written in a reference nonvolatile memory group (40) having characteristics that are inferior to those of the nonvolatile memory (7) in the memory cell array, and data in the reference nonvolatile memory group (40) is written. Is erased, the read voltage applied to the word line WL (gate electrode) is increased from the initial set value of 5 V to, for example, 4.5.
V so as to reduce the degree of data erasure and reduce the amount of non-volatile memory (7) caused by poor reading.
Can be extended, and the service life can be extended as compared with the related art.

Hereinafter, after the read voltage is changed, data is rewritten in the reference nonvolatile memory (40), and the reference nonvolatile memory (4) is again written.
When it is detected that the data in 0) has been deleted,
The read voltage is set to 4.5 V via the control circuit (44).
Therefore, control is performed to lower the voltage to, for example, 4V. Hereinafter, similarly, the longevity of the nonvolatile memory (7) is intended to be prolonged, and the longevity of the non-volatile memory (7) connected to other word lines WL is similarly extended. It is planned.

[0027]

As described above, according to the present invention, data is written in a reference nonvolatile memory group having characteristics that are inferior to those of the nonvolatile memories in the memory cell array. By lowering the read voltage when the data is erased, it is possible to extend the life of the non-volatile memory caused by the read failure, and to achieve a longer life than in the past.

[Brief description of the drawings]

FIG. 1 is a diagram showing a memory cell array of a nonvolatile memory applied to the present invention.

FIG. 2 is a block diagram showing a one-chip microcomputer of the present invention.

FIG. 3 is a circuit block diagram for controlling times of a write voltage, an erase voltage, and a read voltage of the nonvolatile memory.

FIG. 4 is a circuit block diagram for controlling the magnitudes of a write voltage, an erase voltage, and a read voltage of a nonvolatile memory.

FIG. 5 is a circuit block diagram for controlling a reference voltage of a sense amplifier.

FIG. 6 is a block diagram showing a sense amplifier portion of the nonvolatile memory.

FIG. 7 is a cell structure diagram showing a programmed state of a nonvolatile memory.

FIG. 8 is a cell structure diagram showing a read state of the nonvolatile memory in a programmed state.

FIG. 9 is a cell structure diagram showing a read state of the nonvolatile memory which is not in a program state.

FIG. 10 is a cell structure diagram showing an erased state of a nonvolatile memory.

FIG. 11 is a diagram for explaining a problem of a conventional nonvolatile memory.

[Explanation of symbols]

 (7) Non-volatile memory (40) Non-volatile memory group for reference (44) Control circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 (72) Inventor Takashi Asami 2-5-5 Keihanhondori, Moriguchi-shi, Osaka SANYO ELECTRIC In-house F term (reference) 5B025 AA03 AB01 AC01 AD03 AD05 AD09 AE08 5F001 AA22 AA25 AB03 AC02 AC06 AD12 AD20 AD41 AD44 AE02 AE03 AE08 AF05 AF06 AF07 AG40 5F083 EP02 EP24 ER02 ER09 ER14 ER17 ER22 GA30 LA10

Claims (3)

[Claims] 1. A one-chip microcomputer having, as a program memory, a nonvolatile memory capable of electrically erasing data and writing / reading data, wherein the reference memory has a lower characteristic than that of the nonvolatile memory in a memory cell array. One chip, comprising: a nonvolatile memory; and a control circuit that changes a read voltage stored in a specific address area of the nonvolatile memory in advance based on a reference result of the nonvolatile memory for reference. Microcomputer. 2. The one-chip microcomputer according to claim 1, wherein the reference nonvolatile memory is set in a state where data is written. 3. The non-volatile memory for reference has a cell structure with a longer gate length or a shorter gate width than a nonvolatile memory in a memory cell array. 2. The one-chip microcomputer according to claim 1.