JP2000097994A - Semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test a device to be tested in a short time by making a semiconductor tester capable of simultaneously testing a DC testing system and function testing system by using a plurality of contact means. SOLUTION: Two device (DUTs) to be tested are conveyed from a tray, mounted on contact means 51, 53, and tested by a DC testing system, After it is finished, the two DUTs are conveyed, mounted on contact means 52, 54. Then, the two DUTs of a new test are mounted at the means 51, 53, and the tests on a functional testing system and a DC testing system are simultaneously conducted at both the DUTs. After both the tests are finished, the two DUTs of the means 52, 54 are sorted based on a test decision result, and delivered to a tray. Meanwhile, two DUTs of the means 51, 52 are conveyed to and mounted at the means 51, 53, and two DUTs of new test are conveyed to and mounted at the means 51, 53, and then, the operation is repeated and continued.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a function test system and a DC test system into a plurality of contact means, respectively, and performs tests independently and simultaneously, thereby shortening a test time per device under test. The present invention relates to a semiconductor test device.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. A schematic block configuration of a conventional semiconductor test apparatus will be described. As shown in FIG. 3, a semiconductor test apparatus for testing a device under test DUT includes a timing generator 10, a pattern generator 20, a format control 30, a pin electronics 40, contact means 51 and 52, a logic comparator 60, , A fail memory 70, and DC test units 81 and 82.

Although not shown in FIG. 3, each component block is controlled by software by a controller.

FIG. 3 shows a case where two DUTs under test are tested. The number of pins of the device under test DUT is
For example, there are 256 pins, but for simplicity of the drawing, they are shown as one pin. For simplicity of the figure, the pin electronics 40 has two channels.

In general, there are various test items of a semiconductor test device, such as a contact test, a DC test, a function test, and an AC test. On the other hand, from the viewpoint of the hardware to be tested, it can be classified into a unit such as a DC test for performing a test of a DC test system and a unit such as a function test for performing a test of a function test system. Therefore, for simplicity, the description will be made separately for the case where the DC test system and the function test system are tested.

First, the operation of the unit relation for performing a test of the function test system will be described. The timing generator 10 generates a reference clock serving as a test rate, a phase signal, and a strobe.

[0007] The pattern generator 20 receives the reference clock from the timing generator 10 and outputs logical pattern data to the format control 30 at the rate of the reference clock.

The format controller 30 shapes the waveform of the logic pattern with the phase difference and the time width based on the logic pattern data and the phase signal from the timing generator 10, and supplies the waveform to the driver 45.

The pin electronics 40 is a circuit for measurement and includes a driver 45, a comparator 46, reed relays R1, R2 and the like. Also, there are a large number of pin electronics 40 corresponding to the test channels, for example, for 512 channels, which are built in the test head. When a function test system test is performed, the reed relay R1 is turned on (make), and the reed relay R2 is turned off (break).

The driver 45 amplifies the logic pattern to a test voltage level, and connects the reed relay R1 with the contact means 5
The test pattern is applied to the test pins of the device under test DUT via the devices 1 and 52.

On the other hand, the comparator 46 compares an output signal output from the device under test DUT with a comparison voltage,
The data is output to the logic comparator 60 as logic level data.

The contact means 51 and 52 are, for example, IC
A socket or the like, which transports the device under test DUT and makes contact with test pins, and
Signal connection.

The logic comparator 60 is also called a digital compare, and outputs a logic output from the comparator 46,
The logic data of the expected value output from the pattern generator 20 is logically compared at the strobe timing, and the quality of the device under test DUT is determined based on the coincidence or disagreement.

The fail memory 70 is a memory for storing the result of the pass / fail judgment and analyzing the failure.

Next, the operation of the unit relation of the DC test system will be described. However, in addition to the DC test units 81 and 82, there is a universal DC test unit having a wide voltage range as a DC test system unit.
It is omitted for simplicity of the figure. Also, at the time of DC test, the reed relay R1 is turned off,
The reed relay R2 is turned on.

The DC test is also called a DC parametric test, and includes a test of current applied voltage measurement and a voltage applied current measurement. That is, the current applied voltage is measured from the DC test units 81 and 82 via the pin electronics 40 and the contact means 51.
And a voltage is measured by applying a predetermined current to the test pin. Similarly, in the voltage application current measurement, a predetermined voltage is applied from the DC test units 81 and 82 to the test pins of the device under test DUT via the pin electronics 40 and the contact means 51 to measure the current.

Further, the hardware configuration of the semiconductor test apparatus will be described with reference to FIG. As shown in FIG. 4, the semiconductor test device includes a semiconductor test device main body 100,
It comprises a handler 90 and a test head 92.

The semiconductor test apparatus main body 100 includes DC test units 81 and 82 and a format control unit 30.
, A logic comparator 60, various other test units (not shown), a controller,
It has a built-in power supply.

The test head 92 incorporates the pin electronics 40 and is connected to each unit of the semiconductor test apparatus main body 100 by a signal via a cable.

The handler 90 is integrated with the test head 92 and transports the device under test DUT by the transport means 91.

The transport of the device under test DUT is
Although not shown in the figure, for example, the device under test DUT
The test device DUT is sucked from the tray on which the DUT is mounted by the transfer means 91, mounted on the contact means 51 and the contact means 52, and tested. Each is sorted and carried out to a tray.

In a semiconductor test apparatus, the number of devices under test DUT that can be measured simultaneously is generally limited by the number of DC units. In this example, two DC test units 81 and 82 allow two devices under test DUT. Can be measured simultaneously. In addition, the number of channels of the test head 92 is also limited. For example, in the case of 512 channels, the maximum number of pins of the device under test DUT capable of simultaneously measuring two is two.
56 pins.

Next, test steps in the case where two devices under test DUT are measured and tested at the same time will be described in a bulleted form. However, for simplicity of explanation, DC
The test of the test system is a DC test, the test of the function test is a function test, and other test items are omitted.

(1) The two devices under test DUT are transported by the transport means 91, and are mounted on and contacted with the contact means 51 and the contact means 52, respectively.

(2) Turn off the reed relay R1 and turn on the reed relay R2.

(3) DC of two devices under test DUT
Perform tests simultaneously.

(4) When the DC test is completed, the reed relay R1 is turned on and the reed relay R2 is turned off.

(5) Function tests of two devices under test DUT are performed simultaneously.

(6) When the function test is completed, the two DUTs under test are transferred by the transfer means 91 from the contact means 51 and the contact means 52 to the DUT.
According to the judgment result of the test, each is sorted and carried out to the tray.

(7) The above steps (1) to (6) are repeated to perform a test.

As described above, the test of the device under test DUT is performed, and the number of pins of the device under test DUT is large.
In the case of multiple functions, a long test time may be required.
For example, when the device under test DUT has 128 pins, the total transport time is 2 seconds, the DC test system time is 30 seconds,
If the time of the function test system is 30 seconds, the test time is 62 seconds. Further, when two devices under test DUT are measured simultaneously, the throughput per device is 31 seconds.

[0032]

As described above, when the device under test has a large number of pins and is multifunctional, the test time may be long, which is inconvenient in practical use. Therefore, the present invention has been made in view of these problems,
An object of the present invention is to provide a semiconductor test apparatus capable of testing in a short test time even when the device under test has a large number of pins and has a multi-function.

[0033]

That is, a first aspect of the present invention, which has been made to achieve the above object, is to provide a DC test system for testing by a unit for performing a DC test and a function test for testing by a unit for performing a function test. The gist of the present invention is to provide a semiconductor test apparatus capable of independently providing a plurality of contact means to a plurality of contact means and simultaneously performing tests of a DC test system and a function test system.

A second aspect of the present invention, which has been made to achieve the above object, comprises a semiconductor test apparatus main body provided with controller means and a handler provided with transport means for transporting a device under test. In semiconductor test equipment,
A semiconductor test apparatus which includes a plurality of contact means capable of simultaneous measurement of a DC test system and a plurality of contact means capable of simultaneous measurement of a function test system, so that a DC test system and a function test system can be simultaneously tested. It is a gist.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. The schematic block configuration of the semiconductor test apparatus of the present invention will be described. As shown in FIG. 1, a semiconductor test apparatus for testing a device under test DUT includes a timing generator 10, a pattern generator 20, a format control 30, contact means 51 and 52,
The pin electronics 41, 42, 43, 44 are changed and contact means 53, 54 are added to the conventional configuration including the logic comparator 60, the fail memory 70, and the DC test units 81, 82.

Therefore, the description of the operation and test items for each of the same constituent blocks as in the prior art is omitted. Although not shown in FIG. 1, each component block is controlled by software by a controller as in the related art.

In the semiconductor test apparatus according to the present invention, the DC test system block and the function test system block are provided independently with separate contact means. Then, the DC test system includes the pin electronics 41 and 43.
And two contact devices DUT via the contact means 51 and 53, respectively. The function test system includes the pin electronics 42, 4
4 and the contact means 52 and 54 are connected to the two DUTs under test, respectively. Therefore,
A conventional reed relay for switching between the DC test system and the function test system is unnecessary.

According to the present invention, when the number of DC test units is two and the number of channels of the test head is 512 and the number of channels of the other function test is the same as the conventional one, the device under test DUT capable of simultaneous measurement is the conventional two. In this case, the maximum number of pins of the device under test DUT is 128 pins, which is half the conventional number.

The hardware configuration of the semiconductor test apparatus will be described with reference to FIG. As shown in FIG.
As in the prior art, the semiconductor test apparatus of the present invention includes a semiconductor test apparatus main body 100, a test head 92, a handler 90
It consists of:

However, the configuration of the pin electronics and the contact means of the test head 92 and the method of transporting the device under test DUT by the transport means 91 of the handler 90 are different from those in the related art.

Next, a description will be given of an example of a test step in the case where there are four DUTs under test. Further, for simplicity of the drawing, each of the four devices under test DUT has one pin. The steps from a state in which the device under test DUT is not mounted on the contact means 51 to 54 will be described below in a bulleted manner.

(1) Two devices under test DUT to be newly tested are transported from the tray by the transport means 91, and mounted on the contact means 51 and 53, respectively, to make contact.

(2) A test of the DC test system of the device under test DUT mounted on the contact means 51 and 53 is performed.

(3) Two devices under test DUT of the contact means 51 and 53 for which the test of the DC test system has been completed
Is transported by the transporting means 91 to the contact means 52 and 54, respectively, and is mounted. (4) On the other hand, two new devices under test DUT to be newly tested are transported from the tray by the transport means 91 and mounted on the contact means 51 and 53, respectively.

(5) DC test system test for two DUTs mounted on contact means 51 and 53, and function test system for two DUTs mounted on contact means 52 and 54 And test at the same time.

(6) DC test system test for two DUTs mounted on contact means 51 and 53 and function test system for two DUTs mounted on contact means 52 and 54 Is completed, the two DUTs DUT mounted on the contact means 52 and 54 are sorted by the transport means 91 based on the determination result of the test, and are carried out to the tray.

(7) On the other hand, the two DUTs under test mounted on the contact means 51 and 53 are transferred to the transport means 91.
, And are conveyed and mounted on the contact means 52 and 54, respectively.

(8) Further, the two DUTs to be newly tested are transported from the tray by the transport unit 91 and mounted on the contact units 51 and 53, respectively.

(9) By repeating steps (5) to (8), the device under test DUT
The test is continued.

According to the above-described steps, the contact means of the DC test system and the function test system are separately performed at the same time, and therefore, the number of pins of the device under test DUT is large. The test time per hit can be reduced. In other words, when the test times of the divided test items are almost the same, and when the total transport time is relatively shorter than the test time, the time required for one test can be reduced, and the throughput is improved.

For example, if the device DUT under test is 128 pins and the total transport time is 4 seconds, and the test time of both the DC test system and the function test system is 30 seconds, the test of four device DUTs is performed. Is 64 seconds including the transport time, and the throughput per one is 16 seconds in the state where the test is continuously performed. However, the time of the two devices under test DUT performing the first DC test and the time of the two devices under test performing the function test last are ignored.

Incidentally, in the present embodiment, the case where one test head is used has been described. However, the present invention can be similarly realized by using a plurality of test heads. Also, the method of transporting the device under test DUT by suction has been described as the transporting means 91 of the handler 90. However, other transporting methods using a carrier can be similarly realized.

[0054]

The present invention is embodied in the form described above and has the following effects. That is,
Since the test items are divided and tested independently at the same time, when the test time of the divided test items is about the same,
In addition, for a device under test whose transport time is relatively shorter than the test time, the time required for testing each device can be reduced, and the throughput is improved. Further, in the pin electronics, the switching reed relay for the DC test system and the function test system is not required, so that the reliability of the pin electronics is improved and the test signal waveform of the function test system is also improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor test apparatus according to the present invention.

FIG. 2 is a hardware configuration of a semiconductor test apparatus of the present invention.

FIG. 3 is a block diagram of a conventional semiconductor test apparatus.

FIG. 4 is a hardware configuration of a conventional semiconductor test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Timing generator 20 Pattern generator 30 Format control 40, 41, 42, 43, 44 Pin electronics 45 Driver 46 Comparator 51, 52, 53, 54 Contact means 60 Logic comparator 70 Fail memory 81, 82 DC test unit 90 Handler 91 Transport means 92 Test head 100 Semiconductor test equipment main body

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G003 AA07 AB01 AE01 AE06 AF05 AF06 AG01 AG11 AG12 AG17 AH01 AH04 2G032 AA01 AB01 AB05 AC03 AD01 AD05 AE01 AE02 AE07 AE08 AE10 AE11 AE12 AE14 AF10 AG02 AG07 AG09 AH04 A0704 AA04 BA14 DG14 DG23 DG25

Claims (2)

[Claims] 1. A DC test system for testing by a unit for performing a DC test and a function test system for testing by a unit for performing a function test are independently provided to a plurality of contact means, respectively. A semiconductor test device that can perform tests with the system simultaneously. 2. A semiconductor test apparatus comprising a semiconductor test apparatus main body provided with a controller means and a handler provided with a transport means for transporting a device under test, a plurality of contacts capable of simultaneously measuring a DC test system. And a plurality of contact means capable of simultaneously measuring a function test system, and a semiconductor test apparatus capable of simultaneously testing a DC test system and a function test system.