JP2000081466A - Semiconductor integrated device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct a test by use of the internal clocks of a semiconductor integrated device (LSI). SOLUTION: At the first stage of a test, a selector 22 selectively outputs a test clock CLK1 given from an LSI tester, in accordance with a select signal SL. Then test data are stored in an input data register 24 in synchronism with the clock CLK1. After the test data have been stored, when the logic level of the select signal SL is varied, the selector 22 selects an internal clock CLK generated by an internal oscillating circuit 21, and a core logic part 23 generates output data through the action synchronized with the clock CLK. The output data are stored in an output data register 25. After the output data have been stored, when the logic level of the select signal SL is varied, the output data stored are outputted in synchronism with the clock CLK1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device (hereinafter referred to as "LSI").
The present invention relates to a device formed on one LSI chip and capable of performing a test using a test pattern by an LSI tester.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration of a conventional LSI chip.
FIG. This LSI chip 10 has an internal
An internal oscillation circuit 11 for supplying a clock CLK;
Clock CLK and test clock CL input from outside
K _tIs input, and the selection input from the selection terminal Ts is input.
CLK or clock based on the clock signal SL
CLK_tAnd the input terminal IN and output
Core logic unit 13 connected between the
It has. The core logic unit 13 uses the selector 12
The input terminal IN is synchronized with the selected and applied clock.
Fetches and processes the data given by
Output data to the output terminal OUT.
You. For such an LSI chip 10, a test pattern
When performing a test using a component, an LSI tester is used.
Can be The LSI tester is connected to the test
The turn is given to the chip 10 as input data,
The test clock CLK is supplied via the clock terminal Tc._tTo
This is given to the selector 12. The select signal SL at this time
Indicates that the selector 12 outputs the test clock CLK_tSelect
Logic level, so that
Clock CLK_tIs given to the core logic unit 13.
The core logic unit 13 includes a test clock CLK._tSame as
The test pattern given from the input terminal IN.
And outputs the processing result to the output terminal OUT.
You.

[0003]

However, the conventional LSI chip 10 shown in FIG. 2 has the following problems. When testing, since the core logic unit 13 operates in synchronization with the test clock CLK _t, it is constrained to a maximum frequency of the test clock CLK _t the LSI tester is generated, than, be tested at high speed Could not. Further, when the frequency of the internal clock CLK and the test clock CLK _t the internal oscillation circuit 11 outputs different, since there is no the LSI means taking their adjustment to operate the core logic unit 13 by the internal clock CLK Could not be evaluated.

[0004]

According to a first aspect of the present invention, there is provided an internal oscillating circuit for generating an internal clock by oscillating an externally supplied test clock or an externally supplied test clock. A selector for selecting and outputting the internal clock based on a select signal; and inputting data input from an input terminal in synchronization with the test clock or the internal clock supplied from the selector and processing the data. And a core logic unit that outputs the output data of the result to the output terminal, the following input data register and output data register are provided. The input data register is connected between the input terminal and the core logic unit, and is synchronized with a test clock output from the selector during the first first period when the test mode is set, and is used as input data. It stores the test data given from the input terminal.
The output data register is connected between the core logic and the output terminal, and in the second period following the first period, synchronizes with the internal clock output from the selector and outputs the output data output from the core logic unit. The stored output data is supplied to the output terminal in synchronization with the test clock output from the selector during a third period after the storage and the end of the second period. By adopting such a configuration,
In the first period, the test data is stored in the input data register in synchronization with the test clock. In the second period, the test data stored in the input register is taken into the core logic unit in synchronization with the internal clock, and is processed in synchronization with the internal clock. Output data generated as a result of the processing is stored in the output data register.
The output data stored in the output data register is the third data.
In the period, the clock is supplied to the output terminal in synchronization with the test clock.

In the second and third inventions, the L of the first invention is used.
In the SI, a counter is provided which counts the number of clock pulses in the internal clock or the test clock output from the selector and generates a select signal whose polarity changes each time the counted number reaches a predetermined value. By adopting such a configuration, the polarity of the select signal automatically changes, and the selection by the selector automatically changes.
According to a fourth aspect, in the LSI of the first aspect, the input data register and the output data register each output a pulse when a predetermined number of data is input. Further, during the first first period in which the test mode is set, the selector selects the test clock, and when a predetermined number of test data is input to the input data register, the pulse output from the input data register is output. Makes the selector select an internal clock based on
When a predetermined number of output data are input to the output data register, select signal generation means is provided for generating a select signal for causing the selector to select a test clock based on a pulse output from the output data register. By adopting such a configuration, when the test data input to the input data register via the input terminal reaches a predetermined number, the selection of the selector is switched, and the core logic unit is synchronized with the internal clock. The operation is performed, and when a predetermined number of output data is stored in the output data register, the selection of the selector is switched, and the output data is output from the output data register in synchronization with the test clock.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of an LSI chip showing a first embodiment of the present invention. The LSI chip 20 includes an internal oscillation circuit 21 for supplying an internal clock CLK to the inside of the chip, a selector 22, and a core logic unit 23, as in the conventional case. Unlike the conventional LSI chip, the LSI chip 20 is provided with an input data register 24 and an output data register 25 newly constituted by a RAM (random access memory) or the like. The selector 22 is for selecting and outputting an internal clock CLK or a clock terminal clock test input from Tc CLK _t based on the select signal SL input from the select terminal Ts. Core logic unit 23, and outputs the result of the internal clock CLK or in synchronization with the test clock CLK _t uptake data were operating in processing synchronized with the clock.

An input terminal IN for inputting data to the LSI chip 20 includes a two-input AND gate 26 and a two-input NOR
The gate 27 is connected to one input terminal. A signal tst for setting a test mode is input to the other input terminals of the AND gate 26 and the NOR gate 27. The output terminal of the NOR gate 27 is connected to the input side of the core logic unit 23, and the output terminal of the AND gate 26 is connected to the input data register 24.
Is connected to the input side. The output side of the core logic unit 23 is connected to one input terminal of each of a two-input AND gate 28 and a two-input NOR gate 29. These A
The other input terminal of the ND gate 28 and the NOR gate 29 receives the signal tst. AN
The output terminal of the D gate 28 is connected to the input side of the output data register 25. The output terminal of the NOR gate 29 is connected to the output terminal OUT of the chip 20. The input data register 24 and the output data register 25 are also configured to receive the clock selected by the selector 22.

Next, the operation of the LSI chip 20 when a test is performed using an LSI tester will be described. When performing a test, the signal tst is set to a valid “H” in advance. As a result, the test mode is set. When the test mode is set, the AND gates 26 and 28
Pass through the data supplied from the input terminal IN and the data output from the core logic unit 23.
R gates 27 and 29 block the data. FIG.
2 is a time chart illustrating an operation of FIG. 1 in a test mode. The period in which the test mode is set can be divided into a first period Tm1, a second period Tm2, and a third period Tm3, as shown in FIG. In the first period Tm1, the selector 22 provides to select the test clock CLK _t, the select signal SL of "H" to the selector 22. Input data register 24 is synchronized with the clock CLK _t selector 22 selects and outputs the test data Di1 constituting the test pattern supplied via the input terminal IN and an AND gate 26 from the LSI tester
ＤDiN and store them. After all the test data Di1 to DiN forming the test pattern are stored, the logic level of the select signal SL is changed to “L”, so that the second period Tm2 is set.

In the second period Tm2, the selector 22 controls the internal clock CLK based on the "L" select signal SL.
The internal clock CLK is supplied to the core logic unit 23, the input data register 24, and the output data register 25. As a result, the core logic unit 23 fetches the data Di1 to DiN stored in the input data register 24 in synchronization with the internal clock CLK, and performs an operation corresponding to the data Di1 to DiN in an operation synchronized with the internal clock CLK. Data Do1 to Do
N is generated and stored in the output data register 25. After the output data Do1 to DoN are stored in the output data register 25, the logic level of the select signal SL is changed to "H" again, so that the third period is started. In the third period Tm3, based on the select signal SL "H", the output selector 22 selects the test clock CLK _t, the test clock CLK _t the core logic section 23, the input data register 24, And the output data register 25. Accordingly, the output data register 25 is synchronized with the test clock CLK _t,
The stored output data Do1 to DoN are sequentially output to an output terminal O
Output to UT. The output data Do1 to DoN are L
The data is input to the SI tester, and the LSI chip 20 is evaluated.

When the evaluation of the LSI chip 20 is completed, the signal tst is set to invalid “L”, and the mode shifts to the normal mode. In this state, AND gates 26 and 28 cut off data supplied from input terminal IN and data output from core logic unit 23, and NOR gates 27 and 29.
Pass that data, the input data register 24 and the output data register 25 do not function. As described above, in this first embodiment, is provided with the input data register 24 and the output data register 25, it is possible to use a different internal clock CLK and the test clock CLK _t, evaluation The accuracy of is improved. Also, the logic level of the select signal SL is changed to
Since the m2 are running core logic unit 23 with the internal clock CLK, at frequencies above the maximum frequency of the test clock CLK _t, it is possible to generate the output data Do1～DoN, and evaluation of the LSI chip 20 Can be shortened.

Second Embodiment FIG. 4 is a block diagram of an LSI chip showing a second embodiment of the present invention. The same elements as those in FIG. 1 showing the first embodiment are common. Reference numerals are given. A feature of the LSI chip 30 is that a counter 31 for generating a select signal SL is provided. The output terminal of the counter 31 is connected to one input terminal of a two-input AND gate 32. A test signal tst for setting a test mode is input to the other input terminal of the AND gate 32, and an output terminal of the AND gate 32 is connected to the selector 22. Other parts of the chip 30 except for the counter 31 and the AND gate 32 are the same as those of the first embodiment shown in FIG. The output side of the selector 22 is connected to the counter 31.

FIG. 5 is a time chart for explaining the operation of the counter 31 in FIG. Referring to FIG.
The operation of the LSI chip 30 will be described. When performing a test, the signal tst is set to a valid “H” in advance. As a result, the test mode is set. In the state where the test mode is set, the AND gates 26 and 28 are connected to the data supplied from the input terminal IN and the core logic unit 23.
, And the NOR gates 27 and 29 cut off the data. Further, when the test mode is set, the AND gate 32 passes the select signal SL output from the counter 31 to the selector 22. The period in which the test mode is set includes the first period Tm1, the second period Tm2, and the third period Tm1, similarly to the first embodiment.
Can be divided into the period Tm3. First period Tm1
In the counter 31, providing a select signal SL of the selective test clock CLK _t "H" to the selector 22. Input data register 24 is synchronized with the clock CLK _t selector 22 selects and outputs the input terminal I
N and the test data Di1 to DiN given via the AND gate 26 are inputted and stored. Counter 31
Counts the number of clock pulses output from the selector 22, and inverts the logic level of the select signal SL when the count value reaches a set value. Assuming that the number of test data Di1 to DiN is smaller than the set value, after the test data Di1 to DiN are stored, the logic level of the select signal SL is inverted to “L”.
And the process proceeds to the second period Tm2.

In the second period Tm2, the select signal SL
Of the internal clock CL
Since K is selected and output, the core logic unit 23 and the output data register 25 operate in synchronization with the internal clock CLK, as in the first embodiment, and output data D
o1 to DoN are stored in the output data register 25. Also in the second period Tm2, since the counter 31 counts the number of clock pulses output from the selector 22, after the output data Do1 to DoN are stored,
The logic level of select signal SL is inverted to "H" again.
become. When the logic level of the select signal SL becomes “H”, the process shifts to the third period Tm3.

In the third period Tm3, the select signal SL
Based on, since the selector 22 selects and outputs the test clock CLK _t, as in the first embodiment, the output data register 25 is synchronized with the test clock CLK _t, the output data stored Do1~ DoN is sequentially output to the output terminal OUT. The output data Do1 to Do1
N is input to the LSI tester, and the LSI chip 30 is evaluated. When the evaluation of the LSI chip 30 is completed, the signal tst is set to invalid “L”, and the mode shifts to the normal mode. In this state, the AND gate 32 is connected to the selector 22
Is fixed at “L”, the core logic 23 performs an operation synchronized with the internal clock CLK. As described above, in the second embodiment,
An LSI chip 30 similar to that of the first embodiment is provided with a counter 31 that counts the number of clock pulses output by the selector 22 and inverts the logic level of the select signal SL. In addition to the effect, it is not necessary to change the select signal SL externally. Furthermore, the select terminal Ts for introducing the select signal SL from outside can be eliminated.

Third Embodiment FIG. 6 is a block diagram of an LSI chip showing a third embodiment of the present invention, and common elements to those in FIG. 4 showing the second embodiment are common. Reference numerals are given. This LSI chip 40 is obtained by changing the counter 31 of the second embodiment to a programmable counter 41 in which the setting of the maximum value of the count is variable by an external program signal. Has become. In the LSI chip 40 having such a configuration, the programmable counter 4
1 counts the number of pulses of the clock selected by the selector 22, and when the count result exceeds the set maximum value of the count, the logical level of the select signal SL is inverted. Therefore, the operation at the time of testing the LSI chip 40 is the same as that of the second embodiment. Therefore, in the third embodiment, the same effect as that of the first embodiment is obtained, and it is not necessary to externally change the select signal SL, similarly to the second embodiment. Further, since the maximum value of the count set in the programmable counter 41 is variable, there is no restriction on the number of steps of the test pattern,
Tests with test patterns according to the circuit scale can be rationally executed.

Fourth Embodiment FIG. 7 is a block diagram of an LSI chip according to a fourth embodiment of the present invention. The same elements as those in FIG. 1 according to the first embodiment are used in common. Reference numerals are given. This LSI chip 50 has the same internal oscillation circuit 2 as that of the first embodiment.
1, a selector 22, and a core logic unit 23. F is provided between the core logic unit 23 and the input terminal IN.
An input data register 51 composed of an IFO (First-in-First-out) memory is connected, and an output data register 52 composed of a FIFO memory is provided between the core logic unit 23 and the output terminal OUT. Is connected.
For these input / output data registers 51 and 52,
AND gates 26 and 28 and NOR gates 27 and 29 are connected as in FIG. Input data register 51
Has a function of generating a pulse when data is fully stored, and the output data register 51 has a function of generating a pulse when data is fully stored. These pulses are input to the select signal generating means 53. Select signal generating means 5
3 is, for example, a toggle flip-flop (hereinafter, T-FF)
The T-FF 53a outputs the “L” select signal SL when the first pulse is input, and outputs the “H” select signal SL when the second pulse is input. Connected to output. T-FF
The output terminal Q / of 53 a is connected to one input terminal of a two-input AND gate 54. A signal tst for setting a test mode is provided to the other input terminal of the AND gate 54.
And the output terminal of the AND gate 54 is connected to the selector 22.

FIG. 8 is a time chart showing the operation of the registers 51 and 52 and the T-FF 53a in FIG. The operation during the test of FIG. 7 will be described with reference to FIG. When performing a test, the signal tst is set to a valid “H” in advance. As a result, the test mode is set. When the test mode is set, the AND gates 26 and 28 pass the data supplied from the input terminal IN and the data output from the core logic unit 23, and the NOR gates 27 and 29 cut off the data. I do. Further, when the test mode is set, the AN
The D gate 54 passes the select signal SL output from the T-FF 53a to the selector 22. The period in which the test mode is set can be divided into a first period Tm1, a second period Tm2, and a third period Tm3, as in the first embodiment. In the first period Tm1, T-FF53a impart a select signal SL of the selective test clock CLK _t "H" to the selector 22. The input data register 51 includes a clock CL selected and output by the selector 22.
Synchronized to K _t, and stores the input test data Di1~DiN applied through input terminal IN and an AND gate 26. Since the input data register 51 storing all the test data Di1 to DiN is in the data full state, it outputs a pulse as shown in FIG. This pulse is given to the toggle terminal T of the T-FF 53a,
53a outputs the select signal SL of "L". Thereby, the process shifts to the second period Tm2.

In the second period Tm2, the selector 22 operates the internal clock CL by the select signal SL of "L".
Since K is selected and output, the core logic unit 23 and the output data register 52 operate in synchronization with the internal clock CLK as in the first embodiment, and output data D
o1 to DoN are stored in the output data register 52. The output data register 52 storing all the output data Do1 to DoN is in a data full state and outputs a pulse. This pulse is applied to the toggle terminal T of the T-FF 53a, and the T-FF 53a outputs the "H" select signal SL. Thereby, the process shifts to the third period Tm3. In the third period Tm3, the selector 22 outputs the test clock C based on the select signal SL.
Since selects and outputs LK _t, as in the first embodiment, the output data register 52 test clock CL
Synchronized to K _t, and outputs the output data Do1~DoN stored sequentially, the output terminal OUT. This output data Do1
To DoN are input to the LSI tester, and the LSI chip 5
0 is evaluated. When the evaluation of the LSI chip 50 is completed, the signal tst is set to invalid “L”, and the mode shifts to the normal mode. In this state, the AND gate 54 fixes the select signal SL input to the selector 22 to “L”, so that the core logic unit 23 operates in synchronization with the internal clock CLK.

As described above, in the third embodiment,
An input data register 51 that outputs a pulse when storing test data Di1 to DiN of a test pattern
And an output data register 52 that outputs a pulse when the output data Do1 to DoN are stored, and a T-FF 53a that inverts the logic level of the select signal SL with these output pulses. An effect similar to that of the embodiment is obtained. Further, as compared with the first and third embodiments, since the select signal SL is generated inside the chip, unnecessary external terminals can be reduced. Further, since the counter 31 is not used, the circuit scale can be reduced. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, the AND gate 26 and the NOR gate 27 on the input side of the input data registers 24 and 51 may be configured by combining other gates. The AND gate 28 and the NOR gate 29 on the input side of the output data registers 25 and 52 may be configured by combining other gates. Further, the T-FF 53a can be constituted by a 1-bit counter or the like.

[0020]

As described in detail above, according to the first aspect of the invention, the input terminal is connected between the input terminal and the core logic section, and is synchronized with the test clock output from the selector during the first period. Connected between the input data register for storing test data and the core logic and the output terminal, and stores output data output from the core logic section in synchronization with the internal clock output from the selector during the second period And third
During this period, an output data register for providing the stored output data to the output terminal is provided in synchronization with the test clock output from the selector, so that when inputting / outputting data to / from the LSI, the output clock is synchronized with the test clock. It is possible to operate the core logic part with the internal clock,
A test that is not limited by the frequency of the test clock can be performed. Further, the accuracy of LSI evaluation can be improved. Second
According to the third aspect, since the counter or the programmable counter is provided, the logic level of the select signal is automatically inverted, so that it is not necessary to externally change the logic level of the select signal. According to the fourth invention,
Since the input data register and the output data register are configured to output a pulse when a predetermined number of data is input, and a select signal generating means for generating a select signal based on these pulses is provided,
There is no need to externally change the logic level of the select signal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an LSI chip according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional LSI chip.

FIG. 3 is a time chart showing the operation of FIG. 1 in a test mode.

FIG. 4 is a configuration diagram of an LSI chip according to a second embodiment of the present invention.

FIG. 5 is a time chart showing an operation of a counter 31 in FIG. 4;

FIG. 6 is a configuration diagram of an LSI chip according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of an LSI chip according to a fourth embodiment of the present invention.

FIG. 8 shows registers 51 and 52 and a T-FF 53 in FIG.
6 is a time chart showing the operation of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 21 Internal oscillation circuit 22 Selector 23 Core logic part 24, 51 Input data register 25, 52 Output data register 31 Counter 41 Programmable counter 53 Select signal generating means 53a T-FF CLK Internal clock CLK _t Test clock SL Select signal

Claims (4)

[Claims] An internal oscillation circuit that oscillates to generate an internal clock; a selector that selects and outputs an externally applied test clock or the internal clock based on a select signal; And a core logic unit that fetches input data in synchronization with the test clock or the internal clock given from the selector, processes the data, and outputs output data of the processing to an output terminal. , Connected between the input terminal and the core logic unit,
In the first first period when the test mode is set, the input data for synchronizing with the test clock output from the selector and storing the test data given through the input terminal as the input data A register, which is connected between the core logic and the output terminal, and is output by the core logic unit in synchronization with the internal clock output from the selector during a second period following the first period. An output data register for storing output data and synchronizing with the test clock output by the selector and providing the stored output data to the output terminal during a third period after the second period is completed And a semiconductor integrated device. 2. A counter for counting the number of clock pulses in the internal clock or the test clock output from the selector and generating the select signal whose logic level changes each time the count number reaches a predetermined value is provided. 2. The semiconductor integrated device according to claim 1, wherein: 3. The semiconductor integrated device according to claim 2, wherein said counter comprises a programmable counter in which said predetermined value is variable. 4. The input data register and the output data register each output a pulse when a predetermined number of data is input, and the selector supplies the selector with the test clock during the first period. When the predetermined number of the test data is input to the input data register, the selector selects the internal clock based on the pulse output from the input data register, and the output data register Select signal generating means for generating the select signal for causing the selector to select the test clock based on the pulse output from the output data register when the predetermined number of output data is input is provided. The semiconductor integrated device according to claim 1.