IT1255764B - Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici. - Google Patents

Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici.

Info

Publication number
IT1255764B
IT1255764B ITMI921171A ITMI921171A IT1255764B IT 1255764 B IT1255764 B IT 1255764B IT MI921171 A ITMI921171 A IT MI921171A IT MI921171 A ITMI921171 A IT MI921171A IT 1255764 B IT1255764 B IT 1255764B
Authority
IT
Italy
Prior art keywords
thin
soi structure
ionian
installation
high energy
Prior art date
Application number
ITMI921171A
Other languages
English (en)
Original Assignee
Enichem
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Enichem filed Critical Enichem
Priority to ITMI921171A priority Critical patent/IT1255764B/it
Publication of ITMI921171A0 publication Critical patent/ITMI921171A0/it
Priority to EP93201283A priority patent/EP0570057A3/en
Priority to TW082103612A priority patent/TW213516B/zh
Priority to KR1019930008294A priority patent/KR970004423B1/ko
Priority to JP5136425A priority patent/JPH0637288A/ja
Publication of ITMI921171A1 publication Critical patent/ITMI921171A1/it
Priority to US08/302,091 priority patent/US5707899A/en
Application granted granted Critical
Publication of IT1255764B publication Critical patent/IT1255764B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)

Abstract

Procedimento per la preparazione di una struttura SOI con ossido sottile e profondo comprendente, in successione, i seguenti stadi:- una prima impiantazione ionica a fluenza di ossigeno compresa nell'intervallo 10 alla 15-10 alla 16 ioni/cm2;- un successivo trattamento termico nell'intervallo di temperatura compreso fra 600 e 900° C;- una seconda impiantazione ionica a fluenza di ossigeno nell'intervallo 2/8x10 alla 17 ioni/cm2;- un ultimo trattamento termico a temperatura compresa fra 1150 e 1400°C.
ITMI921171A 1992-05-15 1992-05-15 Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici. IT1255764B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
ITMI921171A IT1255764B (it) 1992-05-15 1992-05-15 Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici.
EP93201283A EP0570057A3 (en) 1992-05-15 1993-05-06 Soi structure with a deep thin oxide layer prepared by ion implantation at high energy followed by thermal treatment
TW082103612A TW213516B (en) 1992-05-15 1993-05-10 SOI structure with a deep thin oxide layer prepared by ion implantation at high energy followed by thermal treatment
KR1019930008294A KR970004423B1 (ko) 1992-05-15 1993-05-14 고에너지에서 이온 주입후 열처리를 통하여 제조된 깊고 얇은 산화물층을 갖는 에스오아이(soi) 구조물
JP5136425A JPH0637288A (ja) 1992-05-15 1993-05-14 高エネルギーでイオン注入し、続いて熱処理することにより製造される、深く、薄い酸化物層を備えたｓｏｉ構造
US08/302,091 US5707899A (en) 1992-05-15 1994-09-07 SOI structure with a deep thin oxide layer prepared by ION implantation at high energy followed by thermal treatment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI921171A IT1255764B (it) 1992-05-15 1992-05-15 Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici.

Publications (3)

Publication Number Publication Date
ITMI921171A0 ITMI921171A0 (it) 1992-05-15
ITMI921171A1 ITMI921171A1 (it) 1993-11-15
IT1255764B true IT1255764B (it) 1995-11-15

Family

ID=11363298

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI921171A IT1255764B (it) 1992-05-15 1992-05-15 Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici.

Country Status (6)

Country Link
US (1) US5707899A (it)
EP (1) EP0570057A3 (it)
JP (1) JPH0637288A (it)
KR (1) KR970004423B1 (it)
IT (1) IT1255764B (it)
TW (1) TW213516B (it)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3036619B2 (ja) * 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
JP3427114B2 (ja) * 1994-06-03 2003-07-14 コマツ電子金属株式会社 半導体デバイス製造方法
US6090689A (en) * 1998-03-04 2000-07-18 International Business Machines Corporation Method of forming buried oxide layers in silicon
US5976952A (en) * 1997-03-05 1999-11-02 Advanced Micro Devices, Inc. Implanted isolation structure formation for high density CMOS integrated circuits
KR100491272B1 (ko) * 1997-07-16 2005-08-01 페어차일드코리아반도체 주식회사 소이 기판의 제조 방법
US6180487B1 (en) 1999-10-25 2001-01-30 Advanced Micro Devices, Inc. Selective thinning of barrier oxide through masked SIMOX implant
US6476446B2 (en) 2000-01-03 2002-11-05 Advanced Micro Devices, Inc. Heat removal by removal of buried oxide in isolation areas
US6613643B1 (en) 2000-01-28 2003-09-02 Advanced Micro Devices, Inc. Structure, and a method of realizing, for efficient heat removal on SOI
WO2001067510A1 (en) * 2000-03-10 2001-09-13 Nippon Steel Corporation Simox substrate and method for production thereof
EP1852908A1 (en) * 2000-05-03 2007-11-07 Ibis Technology, Inc. Implantation process using sub-stoichiometric, oxygen doses at diferent energies
US6417078B1 (en) 2000-05-03 2002-07-09 Ibis Technology Corporation Implantation process using sub-stoichiometric, oxygen doses at different energies
US6593173B1 (en) 2000-11-28 2003-07-15 Ibis Technology Corporation Low defect density, thin-layer, SOI substrates
US6414355B1 (en) 2001-01-26 2002-07-02 Advanced Micro Devices, Inc. Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness
US6548369B1 (en) * 2001-03-20 2003-04-15 Advanced Micro Devices, Inc. Multi-thickness silicon films on a single semiconductor-on-insulator (SOI) chip using simox
US6492244B1 (en) 2001-11-21 2002-12-10 International Business Machines Corporation Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices
CN100466203C (zh) * 2003-12-16 2009-03-04 国际商业机器公司 绝缘体上硅晶片的成形绝缘层及其制造方法
JP4876442B2 (ja) 2005-06-13 2012-02-15 株式会社Ｓｕｍｃｏ Ｓｉｍｏｘウェーハの製造方法およびｓｉｍｏｘウェーハ

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031231A (ja) * 1983-07-29 1985-02-18 Toshiba Corp 半導体基体の製造方法
US4676841A (en) * 1985-09-27 1987-06-30 American Telephone And Telegraph Company, At&T Bell Laboratories Fabrication of dielectrically isolated devices utilizing buried oxygen implant and subsequent heat treatment at temperatures above 1300° C.
JPS62132344A (ja) * 1985-12-04 1987-06-15 Nec Corp 集積回路用シリコン基板の製造方法
US4749660A (en) * 1986-11-26 1988-06-07 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making an article comprising a buried SiO2 layer
FR2616590B1 (fr) * 1987-06-15 1990-03-02 Commissariat Energie Atomique Procede de fabrication d'une couche d'isolant enterree dans un substrat semi-conducteur par implantation ionique et structure semi-conductrice comportant cette couche
US5238858A (en) * 1988-10-31 1993-08-24 Sharp Kabushiki Kaisha Ion implantation method
US5080730A (en) * 1989-04-24 1992-01-14 Ibis Technology Corporation Implantation profile control with surface sputtering
US5143858A (en) * 1990-04-02 1992-09-01 Motorola, Inc. Method of fabricating buried insulating layers

Also Published As

Publication number Publication date
KR930024086A (ko) 1993-12-21
ITMI921171A1 (it) 1993-11-15
EP0570057A2 (en) 1993-11-18
US5707899A (en) 1998-01-13
EP0570057A3 (en) 1996-11-06
KR970004423B1 (ko) 1997-03-27
JPH0637288A (ja) 1994-02-10
TW213516B (en) 1993-09-21
ITMI921171A0 (it) 1992-05-15

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960514