GB9520626D0 - Method and system for providing support for speculative execution - Google Patents

Method and system for providing support for speculative execution

Info

Publication number
GB9520626D0
GB9520626D0 GBGB9520626.4A GB9520626A GB9520626D0 GB 9520626 D0 GB9520626 D0 GB 9520626D0 GB 9520626 A GB9520626 A GB 9520626A GB 9520626 D0 GB9520626 D0 GB 9520626D0
Authority
GB
United Kingdom
Prior art keywords
providing support
speculative execution
speculative
execution
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB9520626.4A
Other versions
GB2294341A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB9520626D0 publication Critical patent/GB9520626D0/en
Publication of GB2294341A publication Critical patent/GB2294341A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
GB9520626A 1994-10-18 1995-10-09 Providing support for speculative execution Withdrawn GB2294341A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/324,940 US5692169A (en) 1990-12-14 1994-10-18 Method and system for deferring exceptions generated during speculative execution

Publications (2)

Publication Number Publication Date
GB9520626D0 true GB9520626D0 (en) 1995-12-13
GB2294341A GB2294341A (en) 1996-04-24

Family

ID=23265788

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9520626A Withdrawn GB2294341A (en) 1994-10-18 1995-10-09 Providing support for speculative execution

Country Status (4)

Country Link
US (1) US5692169A (en)
JP (1) JPH08123685A (en)
DE (1) DE19534752A1 (en)
GB (1) GB2294341A (en)

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US5778219A (en) * 1990-12-14 1998-07-07 Hewlett-Packard Company Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
DE69433124T2 (en) 1993-11-05 2004-05-27 Intergraph Corp., Huntsville Command memory with associative crossbar switch
US5740391A (en) * 1996-03-01 1998-04-14 Hewlett-Packard Co. Preventing premature early exception signaling with special instruction encoding
US5748936A (en) * 1996-05-30 1998-05-05 Hewlett-Packard Company Method and system for supporting speculative execution using a speculative look-aside table
US5854928A (en) * 1996-10-10 1998-12-29 Hewlett-Packard Company Use of run-time code generation to create speculation recovery code in a computer system
US5850553A (en) * 1996-11-12 1998-12-15 Hewlett-Packard Company Reducing the number of executed branch instructions in a code sequence
GB2361082B (en) * 1996-11-13 2002-01-30 Intel Corp Processor
US6631454B1 (en) 1996-11-13 2003-10-07 Intel Corporation Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies
US5881280A (en) * 1997-07-25 1999-03-09 Hewlett-Packard Company Method and system for selecting instructions for re-execution for in-line exception recovery in a speculative execution processor
US5915117A (en) * 1997-10-13 1999-06-22 Institute For The Development Of Emerging Architectures, L.L.C. Computer architecture for the deferral of exceptions on speculative instructions
WO1999019795A1 (en) * 1997-10-13 1999-04-22 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for optimizing execution of load and store instructions
US6205491B1 (en) * 1997-12-18 2001-03-20 Sun Microsystems, Inc. Method and apparatus for deferred throwing of exceptions in C++
US6076154A (en) * 1998-01-16 2000-06-13 U.S. Philips Corporation VLIW processor has different functional units operating on commands of different widths
JP3663881B2 (en) * 1998-02-09 2005-06-22 富士ゼロックス株式会社 Device information management device
US6216222B1 (en) 1998-05-14 2001-04-10 Arm Limited Handling exceptions in a pipelined data processing apparatus
US6151706A (en) * 1998-06-16 2000-11-21 Silicon Graphics, Inc. Method, system, and computer program product for extending sparse partial redundancy elimination to support speculative code motion within an optimizing compiler
US6260190B1 (en) * 1998-08-11 2001-07-10 Hewlett-Packard Company Unified compiler framework for control and data speculation with recovery code
US6301705B1 (en) * 1998-10-01 2001-10-09 Institute For The Development Of Emerging Architectures, L.L.C. System and method for deferring exceptions generated during speculative execution
JP2000122875A (en) * 1998-10-19 2000-04-28 Internatl Business Mach Corp <Ibm> Method and system for processing exception
US6519694B2 (en) 1999-02-04 2003-02-11 Sun Microsystems, Inc. System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity
US6463579B1 (en) * 1999-02-17 2002-10-08 Intel Corporation System and method for generating recovery code
US6453463B1 (en) * 1999-06-07 2002-09-17 Sun Microsystems, Inc. Method and apparatus for providing finer marking granularity for fields within objects
US6640315B1 (en) 1999-06-26 2003-10-28 Board Of Trustees Of The University Of Illinois Method and apparatus for enhancing instruction level parallelism
US7761857B1 (en) * 1999-10-13 2010-07-20 Robert Bedichek Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts
US6658555B1 (en) * 1999-11-04 2003-12-02 International Business Machines Corporation Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline
US20020100031A1 (en) * 2000-01-14 2002-07-25 Miguel Miranda System and method for optimizing source code
US6732363B1 (en) * 2000-02-28 2004-05-04 Sun Microsystems, Inc. Supporting inter-process communication through a conditional trap instruction
US6594821B1 (en) * 2000-03-30 2003-07-15 Transmeta Corporation Translation consistency checking for modified target instructions by comparing to original copy
US6615300B1 (en) 2000-06-19 2003-09-02 Transmeta Corporation Fast look-up of indirect branch destination in a dynamic translation system
US6895527B1 (en) * 2000-09-30 2005-05-17 Intel Corporation Error recovery for speculative memory accesses
WO2002101548A1 (en) * 2001-06-08 2002-12-19 Equator Technologies, Inc. System for compiling a computer program
US7584425B2 (en) * 2001-07-31 2009-09-01 Verizon Business Global Llc Systems and methods for generating reports
US6931515B2 (en) 2002-07-29 2005-08-16 Hewlett-Packard Development Company, L.P. Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loads
US7051238B2 (en) * 2002-07-30 2006-05-23 Hewlett-Packard Development Company, L.P. Method and system for using machine-architecture support to distinguish function and routine return values
US20040024992A1 (en) * 2002-08-02 2004-02-05 Shan-Chyun Ku Decoding method for a multi-length-mode instruction set
US7000091B2 (en) * 2002-08-08 2006-02-14 Hewlett-Packard Development Company, L.P. System and method for independent branching in systems with plural processing elements
US7310723B1 (en) 2003-04-02 2007-12-18 Transmeta Corporation Methods and systems employing a flag for deferring exception handling to a commit or rollback point
US20060224869A1 (en) * 2005-03-31 2006-10-05 Flachs Brian K Combination of forwarding/bypass network with history file
US8413162B1 (en) 2005-06-28 2013-04-02 Guillermo J. Rozas Multi-threading based on rollback
US7996662B2 (en) * 2005-11-17 2011-08-09 Apple Inc. Floating point status/control register encodings for speculative register field
US7721076B2 (en) * 2006-12-18 2010-05-18 Intel Corporation Tracking an oldest processor event using information stored in a register and queue entry
US7747899B2 (en) * 2007-06-26 2010-06-29 Microsoft Corporation Providing mapping fault processing
US8566780B2 (en) * 2007-06-26 2013-10-22 Microsoft Corporation Object model based mapping
US20130326200A1 (en) * 2011-02-11 2013-12-05 Freescale Semiconductor, Inc. Integrated circuit devices and methods for scheduling and executing a restricted load operation
JP6726136B2 (en) * 2017-06-22 2020-07-22 ルネサスエレクトロニクス株式会社 Data access device and access error notification method

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US4881194A (en) * 1987-11-16 1989-11-14 Intel Corporation Stored-program controller for equalizing conditional branch delays
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US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
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US5546599A (en) * 1994-03-31 1996-08-13 International Business Machines Corporation Processing system and method of operation for processing dispatched instructions with detected exceptions

Also Published As

Publication number Publication date
GB2294341A (en) 1996-04-24
JPH08123685A (en) 1996-05-17
US5692169A (en) 1997-11-25
DE19534752A1 (en) 1996-04-25

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)