GB678427A - Improvements in electronic adding devices - Google Patents

Improvements in electronic adding devices

Info

Publication number
GB678427A
GB678427A GB574151A GB574151A GB678427A GB 678427 A GB678427 A GB 678427A GB 574151 A GB574151 A GB 574151A GB 574151 A GB574151 A GB 574151A GB 678427 A GB678427 A GB 678427A
Authority
GB
United Kingdom
Prior art keywords
pulse
group
lead
pulses
trigger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB574151A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JOHN RONALD WOMERSLEY
British Tabulating Machine Co Ltd
Original Assignee
JOHN RONALD WOMERSLEY
British Tabulating Machine Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JOHN RONALD WOMERSLEY, British Tabulating Machine Co Ltd filed Critical JOHN RONALD WOMERSLEY
Priority to GB574151A priority Critical patent/GB678427A/en
Priority to FR1093951D priority patent/FR1093951A/en
Priority to US225726A priority patent/US2898042A/en
Publication of GB678427A publication Critical patent/GB678427A/en
Priority to US816356A priority patent/US3062446A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491Computations with decimal numbers radix 12 or 20.
    • G06F7/492Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494Adding; Subtracting
    • G06F7/495Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/491Indexing scheme relating to groups G06F7/491 - G06F7/4917
    • G06F2207/4913Sterling system, i.e. mixed radix with digit weights of 10-20-12

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  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Electrotherapy Devices (AREA)

Abstract

678,427. Digital electric calculating-apparatus. BRITISH TABULATING MACHINE CO., Ltd., WOMERSLEY, J. R., and TOWNSEND, R March 9, 1951, No. 5741/51, Class 106 (i). [Also in Group XL (c)] An electronic device for adding two numbers ex. pressed in a chosen notation and each represented by a pulse train in which groups of pulses represent, in the binary code, the digits of the number, comprises a first adding means for adding the twc pulse trains to form a first sum pulse train, a second adding means for adding the first sum pulse train and a pulse train representing in each group a " filler " digit equal to the difference between the natural radix of the group (e.g. 16 if each group has four pulses) and the radix of the chosen notation to form a second sum pulse train, and a third adding means to add to each group of either the first or second sum pulse trains a correction pulse group depending on whether or not a carry out of the group takes place during the first or second adding processes, the first or second sum pulse train being delayed by a time equal to the duration of a pulse group. It is shown that if a carry out of a group is produced at the first or second addition, the " filler" digit must be added to the first sum of that group to arrive at the correct sum. The embodiments described have four pulses in a group and operate on decimal numbers, using a " filler " digit of 6. In one arrangement, Fig. 2, the two pulse trains from serial stores 30, 31 are added in a first adder 32 having a carry delay device 33. The sum output is applied to a second, but simplified, adder or carry generator 39 to which pulses representing the " filler" digit (the second and third pulses of each group of four) are also applied via a lead 40. This carry generator has no sum output and carries occurring between groups are suppressed by pulses on a lead 41 connected to the carry delay device 43 and supplied with a pulse in the first period of each group. These carry pulses are, however, applied to a lead 44 which, with a lead 35 connected to the carry input of the first adder 32, is connected to a coincidence circuit 45 producing an output pulse on a lead 47 only when a pulse is present on either of leads 35, 44 and on a lead 46 supplied with a pulse during the first period of each group. Thus, when a carry out of a group has occurred during either the first or second adding operations, a pulse is applied to the lead 47. A trigger pair 48 is switched "on" thereby and is restored at the end of the group by one of a series of pulses on a lead 49. While the trigger is " on " a gate 50 is opened to pass "filler" digit pulses on lead 51 to the third adder 55 which also receives the sum output of the first adder after it has passed through a one-pulse-group delay device 38, which may comprise a short ultrasonic delay line or a network. The sum output 58 of this adder carries the corrected sum pulse train. If desired, the delay device 38 may produce a delay corresponding with the number of pulses (e.g. 32) in a complete pulse train, in which case a delay of the same amount less the duration of one group is produced by a device in the lead 47. In a second arrangement; Fig. 1, the sum output from the second adder 7 (in this case a complete adder) is applied to the third adder 13 via a one-pulse group delay device 12 and if a carry out of a group has occurred in either of the first or second adders 3, 7, no addition takes place in the third adder since the input thereto represents the correct sum. If, however, no such carry occurs, a gate 23 is opened under control of a trigger pair 21 and a coincidence circuit 19 to apply pulses to the third adder representing the complement (in the present example, 10) of the "filler" digit. In the third adder, carries out of a group are suppressed by pulses on a lead 17, each occurring in the first period of a group, so that the correction pulses effectively subtract the "filler" digit if it should not have been added. By choosing appropriate " filler " digits, numbers in other notations, e.g. duodecimal, may be added and by using larger pulse groups, notations having radices greater than 16 may be employed. Moreover, by using suitable control pulse trains, numbers expressed in non- uniform notations may be added. Each adder may comprise a group of six rectifiers 62-67, Fig. 3, having their cathodes connected in pairs to the three input leads 59-61, a group of three rectifiers 68-70 having their anodes connected respectively to the input leads, and a group of three rectifiers 71-73 having their cathodes connected to the input leads. If positive pulses occur simultaneously on two or more input leads, the potential of the connected anodes of the rectifiers of at least one pair of the first six, which are connected through resistances to a positive supply 104, rises. A triode V3, the grid of which is coupled to these rectifiers, is thus rendered conducting and produces a negative pulse on the carry output lead 34 connected to its anode. If a pulse occurs simultaneously on each of the three input leads, the connected anodes of the rectifiers 71-73 rise in potential and a positive pulse is applied over a condenser 90 to the grid of a triode V<SP>1</SP> to render it conducting and produce a positive pulse at its cathode which is connected to the sum output lead 36. The rectifiers 68-70 normally conduct to a negative lead 107 and if one or more pulses occur on the input leads, the increase in potential of the connected cathodes produces an increase in potential at a point between rectifiers 82, 89 connected over a resistance 83 to the positive lead 104. This normally produces a positive pulse over a condenser 93 at the grid of a triode V<SP>2</SP> to render it conducting and produce a positive pulse at the sum output lead 36 connected to its cathode. If, however, two or more pulses are present, a negative pulse is produced over a condenser 97 at the point between the rectifiers 82, 89, by conduction in the triode V<SP>3</SP>, to inhibit the pulse normally applied to the triode V<SP>2</SP>. A shaping waveform is also applied to the grids of the triodes V1, V2 over condensers 95, 101. The carry generator 39, Fig. 2, may comprise merely the six rectifiers 62-67, the triode V3 and the associated components. Each unit delay comprises an inverting triode V<SP>8</SP>, Fig. 4, the anode of which is coupled by a differentiating circuit 115, 122, to the left-hand grid of a trigger pair V<SP>4</SP>, V<SP>5</SP> having two stable states, the valve V<SP>4</SP> normally conducting. A negative pulse is consequently produced at the end of the positive pulse at the anode of the triode V<SP>9</SP>, to switch the trigger, which is restored at the end of the pulse period by a negative control pulse applied to its right-hand grid from lead 132. A second trigger V<SP>6</SP>, V<SP>7</SP> is consequently switched at this time by virtue of a coupling between its left-hand grid and the left-hand anode of the first trigger. This second trigger is restored in the middle of the next period by a negative control pulse on a lead 134. While the second trigger is switched, a cathodefollower triode V<SP>8</SP> is conducting by virtue of a connection between its grid and the left-hand anode of the second trigger. A corresponding positive pulse is thus produced on the output lead 61 connected to the cathode of the triode V<SP>8</SP>. This pulse may be inhibited during the first period of each group by negative pulses on a lead 133 applied to the grid of the triode V<SP>8</SP> over a rectifier 128. If all the output pulses are required on a second output, the latter is connected to a second cathode-follower also coupled to the left-hand grid of the second trigger. The coincidence and gating circuits 19, 21, 23, Fig. 1, are shown in Fig. 6. When a positive pulse is received on both of two leads 6, 10, coupled over rectifiers 138, 139, to the control grid of a pentode V<SP>10</SP>, and also on the lead 20 coupled to the suppressor grid, a negative pulse is produced at the anode to switch a trigger V<SP>11</SP>, V<SP>12</SP> to the left-hand grid of which the anode is connected. The trigger is restored at the end of the period by a negative pulse on the lead 22 coupled to the right-hand grid. While the trigger is switched, a cathode-follower triode V<SP>13</SP>, the grid of which is connected to the right-hand anode of the trigger is rendered non-conducting. If, however, the trigger is not switched, the triode V<SP>13</SP> conducts and its cathode is at high potential and blocks a rectifier 159 so that positive pulses on the lead 24 coupled to the grid of a cathode-follower triode V<SP>14</SP> produce output pulses on the lead 25. The grid of the triode V<SP>14</SP> is normally held below cut-off by its connection to a potentiometer 156, 155 arranged between earth and a negative supply potential. The circuits 45, 48 and 50, Fig. 2, are similar except that, as output pulses are only required when the trigger is switched, the triode V<SP>13</SP> is coupled to the left-hand anode of the trigger.
GB574151A 1951-03-09 1951-03-09 Improvements in electronic adding devices Expired GB678427A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB574151A GB678427A (en) 1951-03-09 1951-03-09 Improvements in electronic adding devices
FR1093951D FR1093951A (en) 1951-03-09 1951-04-27 Further training in electronic adding machines
US225726A US2898042A (en) 1951-03-09 1951-05-11 Electronic adding devices
US816356A US3062446A (en) 1951-03-09 1959-04-30 Serial adder for binary coded numbers with radix correction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB574151A GB678427A (en) 1951-03-09 1951-03-09 Improvements in electronic adding devices

Publications (1)

Publication Number Publication Date
GB678427A true GB678427A (en) 1952-09-03

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ID=9801777

Family Applications (1)

Application Number Title Priority Date Filing Date
GB574151A Expired GB678427A (en) 1951-03-09 1951-03-09 Improvements in electronic adding devices

Country Status (1)

Country Link
GB (1) GB678427A (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2733862A (en) * 1952-12-26 1956-02-07 Ooooo cccccctc
US2823855A (en) * 1952-11-26 1958-02-18 Hughes Aircraft Co Serial arithmetic units for binary-coded decimal computers
US2890831A (en) * 1953-02-06 1959-06-16 British Tabulating Mach Co Ltd Serial adder with radix correction
US2892587A (en) * 1953-09-03 1959-06-30 Hughes Aircraft Co Result-from-carry adder-subtracters
US2910239A (en) * 1953-01-30 1959-10-27 Ibm Serial type binary-coded decimal adder
US2923474A (en) * 1953-09-02 1960-02-02 Hughes Aircraft Co Multiple input binary-coded decimal adders and subtracters
US2936116A (en) * 1952-11-12 1960-05-10 Hnghes Aircraft Company Electronic digital computer
US2943790A (en) * 1956-01-10 1960-07-05 Curtiss Wright Corp Arithmetic device
US2947479A (en) * 1953-09-25 1960-08-02 Burroughs Corp Electronic adder
US2961159A (en) * 1956-06-06 1960-11-22 James D Gallagher Multi-channel electric pulse height analyser with binary coded decimal display
US2989237A (en) * 1956-05-14 1961-06-20 Int Computers & Tabulators Ltd Coded decimal adder subtractor
US3004706A (en) * 1955-10-25 1961-10-17 Int Computers & Tabulators Ltd Computing machines
US3014662A (en) * 1954-07-19 1961-12-26 Ibm Counters with serially connected delay units
US3018047A (en) * 1957-02-11 1962-01-23 Monroe Calculating Machine Binary integer divider
US3023964A (en) * 1954-12-28 1962-03-06 Rca Corp Digital computing systems
US3023963A (en) * 1954-12-28 1962-03-06 Rca Corp Digital computing systems
US3028085A (en) * 1957-07-16 1962-04-03 Clary Corp Calculating apparatus
US3201762A (en) * 1957-01-25 1965-08-17 Honeywell Inc Electrical data processing apparatus
US3245039A (en) * 1954-03-22 1966-04-05 Ibm Electronic data processing machine

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2936116A (en) * 1952-11-12 1960-05-10 Hnghes Aircraft Company Electronic digital computer
US2823855A (en) * 1952-11-26 1958-02-18 Hughes Aircraft Co Serial arithmetic units for binary-coded decimal computers
US2733862A (en) * 1952-12-26 1956-02-07 Ooooo cccccctc
US2910239A (en) * 1953-01-30 1959-10-27 Ibm Serial type binary-coded decimal adder
US2890831A (en) * 1953-02-06 1959-06-16 British Tabulating Mach Co Ltd Serial adder with radix correction
US2923474A (en) * 1953-09-02 1960-02-02 Hughes Aircraft Co Multiple input binary-coded decimal adders and subtracters
US2892587A (en) * 1953-09-03 1959-06-30 Hughes Aircraft Co Result-from-carry adder-subtracters
US2947479A (en) * 1953-09-25 1960-08-02 Burroughs Corp Electronic adder
US3245039A (en) * 1954-03-22 1966-04-05 Ibm Electronic data processing machine
US3014662A (en) * 1954-07-19 1961-12-26 Ibm Counters with serially connected delay units
US3023964A (en) * 1954-12-28 1962-03-06 Rca Corp Digital computing systems
US3023963A (en) * 1954-12-28 1962-03-06 Rca Corp Digital computing systems
US3004706A (en) * 1955-10-25 1961-10-17 Int Computers & Tabulators Ltd Computing machines
US2943790A (en) * 1956-01-10 1960-07-05 Curtiss Wright Corp Arithmetic device
US2989237A (en) * 1956-05-14 1961-06-20 Int Computers & Tabulators Ltd Coded decimal adder subtractor
US2961159A (en) * 1956-06-06 1960-11-22 James D Gallagher Multi-channel electric pulse height analyser with binary coded decimal display
US3201762A (en) * 1957-01-25 1965-08-17 Honeywell Inc Electrical data processing apparatus
US3018047A (en) * 1957-02-11 1962-01-23 Monroe Calculating Machine Binary integer divider
US3028085A (en) * 1957-07-16 1962-04-03 Clary Corp Calculating apparatus

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