GB2471833B - Under land routing - Google Patents

Under land routing

Info

Publication number
GB2471833B
GB2471833B GB0911767.2A GB0911767A GB2471833B GB 2471833 B GB2471833 B GB 2471833B GB 0911767 A GB0911767 A GB 0911767A GB 2471833 B GB2471833 B GB 2471833B
Authority
GB
United Kingdom
Prior art keywords
rdl
layers
ubm
tracks
routing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0911767.2A
Other versions
GB0911767D0 (en
GB2471833A (en
Inventor
Zaid Aboush
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Technologies International Ltd
Original Assignee
Cambridge Silicon Radio Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cambridge Silicon Radio Ltd filed Critical Cambridge Silicon Radio Ltd
Priority to GB0911767.2A priority Critical patent/GB2471833B/en
Priority to TW098124713A priority patent/TWI487078B/en
Publication of GB0911767D0 publication Critical patent/GB0911767D0/en
Priority to US12/829,745 priority patent/US8368224B2/en
Publication of GB2471833A publication Critical patent/GB2471833A/en
Application granted granted Critical
Publication of GB2471833B publication Critical patent/GB2471833B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
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    • H01L2224/02331—Multilayer structure
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An electronic component of a Wafer Level Chip Scale Package (WLCSP) comprises an integrated device and a plurality of packaging layers in which routing between bond pad locations on the device (fig 1; 105) and solder ball lands 300 on the surface of the component in an under ball metallization layer (UBM) is provided by tracks 305 in an intermediate metallic redistribution layer (RDL) 310, 311. Vias allow electrical connection between the UBM and RDL layers, and the RDL and device bond pad layers. The RDL tracks may be routed below the extent of a solder ball land by providing a channel 304 through both the via 302, 303 and redistribution layer 310, 311 underneath the land.
GB0911767.2A 2009-07-07 2009-07-07 Under land routing Active GB2471833B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0911767.2A GB2471833B (en) 2009-07-07 2009-07-07 Under land routing
TW098124713A TWI487078B (en) 2009-07-07 2009-07-22 Under land routing
US12/829,745 US8368224B2 (en) 2009-07-07 2010-07-02 Under land routing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0911767.2A GB2471833B (en) 2009-07-07 2009-07-07 Under land routing

Publications (3)

Publication Number Publication Date
GB0911767D0 GB0911767D0 (en) 2009-08-19
GB2471833A GB2471833A (en) 2011-01-19
GB2471833B true GB2471833B (en) 2013-05-15

Family

ID=41022269

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0911767.2A Active GB2471833B (en) 2009-07-07 2009-07-07 Under land routing

Country Status (2)

Country Link
GB (1) GB2471833B (en)
TW (1) TWI487078B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060022350A1 (en) * 2004-07-29 2006-02-02 Watkins Charles M Integrated circuit and methods of redistributing bondpad locations
US20060292711A1 (en) * 2005-06-28 2006-12-28 Peng Su Mechanical integrity evaluation of low-k devices with bump shear
US20070052092A1 (en) * 2005-09-02 2007-03-08 Ching-Hung Kao Interconnection structure
US20070063352A1 (en) * 2005-09-21 2007-03-22 Agere Systems Inc. Routing under bond pad for the replacement of an interconnect layer
US20080001296A1 (en) * 2005-04-18 2008-01-03 Chao-Chun Tu Bond pad structures and semiconductor devices using the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7122458B2 (en) * 2004-07-22 2006-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating pad redistribution layer
US20080083980A1 (en) * 2006-10-06 2008-04-10 Advanced Chip Engineering Technology Inc. Cmos image sensor chip scale package with die receiving through-hole and method of the same
US20080157303A1 (en) * 2006-12-28 2008-07-03 Advanced Chip Engineering Technology Inc. Structure of super thin chip scale package and method of the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060022350A1 (en) * 2004-07-29 2006-02-02 Watkins Charles M Integrated circuit and methods of redistributing bondpad locations
US20080001296A1 (en) * 2005-04-18 2008-01-03 Chao-Chun Tu Bond pad structures and semiconductor devices using the same
US20060292711A1 (en) * 2005-06-28 2006-12-28 Peng Su Mechanical integrity evaluation of low-k devices with bump shear
US20070052092A1 (en) * 2005-09-02 2007-03-08 Ching-Hung Kao Interconnection structure
US20070063352A1 (en) * 2005-09-21 2007-03-22 Agere Systems Inc. Routing under bond pad for the replacement of an interconnect layer

Also Published As

Publication number Publication date
TWI487078B (en) 2015-06-01
GB0911767D0 (en) 2009-08-19
GB2471833A (en) 2011-01-19
TW201103110A (en) 2011-01-16

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