GB2276632A - Gold alloy for use in semiconductor element - Google Patents

Gold alloy for use in semiconductor element Download PDF

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Publication number
GB2276632A
GB2276632A GB9405839A GB9405839A GB2276632A GB 2276632 A GB2276632 A GB 2276632A GB 9405839 A GB9405839 A GB 9405839A GB 9405839 A GB9405839 A GB 9405839A GB 2276632 A GB2276632 A GB 2276632A
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ppm
yttrium
gold
calcium
weight
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GB2276632B (en
GB9405839D0 (en
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Kenji Mori
Masanori Tokida
Takanori Fukuda
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Tatsuta Electric Wire and Cable Co Ltd
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Tatsuta Electric Wire and Cable Co Ltd
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Publication of GB2276632B publication Critical patent/GB2276632B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C5/00—Alloys based on noble metals
    • C22C5/02—Alloys based on gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/012—Semiconductor purity grades
    • H01L2924/01204—4N purity grades, i.e. 99.99%
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Wire Bonding (AREA)

Abstract

Gold alloys are disclosed containing yttrium, calcium, beryllium and lead as additives in the ratio of yttrium: calcium: beryllium: lead = 1: 0.5 to 2.0 : 0.1 to 1.0 : 0.1 to 1.0, preferably 1 : 0.7 to 1.5 : 0.2 to 0.6 : 0.1 to 0.5. The yttrium content is at least 5 ppm by weight, preferably 10 to 30 ppm. The total content of said additives is 80 ppm or less by weight, preferably 20 to 60 ppm, the balance being inevitable impurities and gold. The head resistance and the strengths of such alloys at normal and high temperatures are improved and the splicing loop height can be reduced. Also the influence of the wire flow due to the sealing resin is negligible, and the shape of the ball is favourable, so that the reliable splicing can be achieved.

Description

GOLD ALLOY FOR USE IN SEMICONDUCTOR ELEMENT The present invention relates to gold alloys for use in semiconductor elements, in particular to gold alloys for use in semiconductor elements advantageously used for bonding gold wires improved in heat resistance used for connecting mainly for example electrodes on said semiconductor elements with external leads.
Fine gold wires have been used as bonding wires connecting for example electrodes on silicon semiconductor elements with external leads. It is the reason why such the fine gold wires have been used in many cases that gold balls have a true spherical shape, said gold balls formed being suitable in hardness not so as to damage said silicon semiconductor elements by a pressure during a splicing, a sure connection being able to be achieved, and thus they being remarkably high in reliability. And, many proposals have been made as for such the bonding fine gold wires.
However, as to the practical uses of such many proposals, problems have occurred in that the fine gold wires exhibit lower recrystallization temperatures and are lacking in heat resistance, so that a tensile strength of a portion immediately above the formed gold ball is insufficient and thus the wire is broken or the spliced wire is broken when sealed with resins even though the fine gold wire is spliced without the breakage of the wire in the case where a front end of the fine gold wire is molten to form the gold ball, whereby conducting the splicing, in an automatic bonder or a wire flow occurs to bring about a short circuit in the case where the semiconductor element is protected with sealing resins.
It has been well known that various kinds of bonding fine gold wire improved in breaking strength and heat resistance by adding a very small quantity of elements as additives to high-purity gold to an extent of not spoiling the gold ball formed during the connecting process in shape and hardness have been proposed in order to solve the above described problems.
It was found from the inventors' investigation whether such various kinds of fine gold wire proposed can be concretely put to practical use or not that they are all unsuitable for the thin packaging devices, which have been rapidly diffused in recent years, in splicing loop height and thus insufficient.
It is an object of the present invention to provide gold alloys for use in semiconductor elements capable of remarkably reducing a splicing loop height and thus being satisfactorily adopted as bonding wires of thin packaging devices.
According to the present invention gold alloys are provided containing yttrium, calcium, beryllium and lead in the ratio of yttrium : calcium : beryllium : lead = 1 : 0.5 to 2.0 : 0.1 to 1.0 : 0.1 to 1.0, the minimum quantity of yttrium being 5 ppm by weight, the total quantity of these elements being 80 ppm or less by weight, and the rest being inevitable impurities and gold.
According to a preferred embodiment of the invention, the ratio of Y : Ca : Be : Pb is 1 : 0.7 to 1.5 : 0.2 to 0.6 : 0.1 to 0.5. The yttrium content is preferably 10 to 30 ppm by weight and the total content of Y, Ca, Be and Pb is preferably 20 to 60 ppm by weight.
In the case where yttrium is added in a quantity of 5 ppm or less by weight, the heat resistance cannot be improved and the wire flow occurs under an influence by sealing resins and additionally the loop height is fluctuated and thus the splicing cannot be stabilized, so that the minimum quantity of yttrium was set at 5 ppm by weight, preferably 10 to 30 ppm by weight.
In the case where a ratio of calcium to yttrium is less than 0.5, a synergism of yttrium and beryllium is wanting, the heat resistance being unstabilized, the loop height being fluctuated, and the wire flow slightly occurring.
On the contrary, in the case where said ratio of calcium to yttrium exceeds 2.0, an oxidized film is formed on a surface of a ball, said ball being distorted in shape, calcium being deposited on grain boundaries of gold crystals to generate the brittleness, whereby hindering the wire-extending process. Accordingly, the ratio of calcium to yttrium was set at 0.5 to 2.0, preferably 0.7 to 1.5.
In the case where a ratio of beryllium to yttrium or calcium is less than 0.1, the mechanical strength at the normal temperature cannot be still more improved. On the contrary, in the case where said ratio of beryllium to yttrium or calcium exceeds 1.0, said oxidized film is formed on said surface of the ball, the ball being distorted in shape, beryllium being deposited on said grain boundaries of said gold crystals to generate the brittleness, whereby hindering the wire-extending process. Accordingly, the ratio of beryllium to yttrium or calcium was set at 0.1 to 1.0, preferably 0.2 to 0.6.
In the case where a ratio of lead to yttrium, calcium or beryllium is less than 0.1, no effect can be obtained.
On the contrary, the strengths at the normal temperature and high temperatures are improved with an increase of said ratio of lead to yttrium, calcium or beryllium but the ball is distorted in shape and deteriorated in true sphericity in the case where the ratio of lead to yttrium, calcium or beryllium exceeds 1.0, so that the ratio of lead to yttrium, calcium or beryllium was set at 0.1 to 1.0, preferably 0.1 to 0.5.
And, the total quantity of the elements is set at 80 ppm or less, preferably 20 to 60 ppm. In the case where the total quantity of the elements exceeds 80 ppm, an oxidized film of the elements added formed on the surface of the ball has a bad effect on the shape of the ball (generates cavities) not to give the ball the true spherical shape.
The preferred embodiments of the present invention will be below described.
Gold alloys comprising electrolytic gold having the purity of 99.99 % by weight or more and chemical components shown in Table 1 are molten in the high-frequency vacuum melting furnace to be cast and then the resulting ingot is rolled followed by subjecting to the wire-extending process at the normal temperature to obtain a fine gold alloy wire having the final wire diameter of 25 m followed by annealing to adjust the nature so that the elongation may amount to 4 4 %.
TABLE 1
Chemical components (ppm by weight) Gold and inevitable Total Y Ca Be Pb impurities quantity 1 7 4 0. 8 0. 8 rest 12. 6 2 20 25 8 8 " 61 3 30 25 10 10 " 75 4 10 18 8 8 " 44 Preferred 5 10 10 4 5 " 29 6 10 15 6 3 " 34 embodiment 7 20 14 8 2 " 44 8 20 20 4 6 " 50 9 20 30 5 3 " 58 10 30 20 6 3 " 59 11 30 20 8 8 " 66 1 3 1. 5 0. 3 0. 3 rest 5. 1 Comparative 2 30 30 15 15 " 90 example 3 50 25 3 3 " 81 4 40 30 10 5 " 85 The obtained fine gold alloy wires were examined as to the tensile strength at the normal temperature, the tensile strength at the high temperature (after holding for 20 seconds at 250 C ), the splicing loop height, the wire flow during the molding and the shape of the ball. The results are shown in Table 2.
T a b l e 2
Tensile characteristics Tensile characteristics at the normal temperature at high temperatures Loop Existence Shape of the ball height of the Breaking load Elongation Breaking load Elongation ( m) wire flow External True (gf) (%) (gf) (%) appearance sphericity Cavity 1 11.5 4 8.0 3 1 7 0 2 13.0 4 11.0 2 1 5 0 3 13.5 4 12.0 2 1 4 0 4 12.5 4 10.0 2 1 6 0 Preferred 5 12.0 4 9.5 2 1 6 0 6 12.5 4 10.5 2 1 5 5 embodiment 7 12.5 4 10.5 2 1 5 5 8 13.0 4 11.0 2 1 5 0 9 13.5 4 11.5 2 1 4 5 10 13.5 4 11.5 2 1 4 5 11 13.5 4 11.5 2 1 4 5 1 9.0 4 6.5 7 1 9 0 x Comparative 2 13.5 4 12.5 2 1 4 0 x x x example 3 13.0 4 11.0 2 1 5 0 x x x 4 13.5 4 12.5 2 1 4 0 The splicing loop height is measured by splicing the electrodes on the semiconductor element to the external leads by the use of the high-speed automatic bonder followed by observing the top height of the formed loop and the electrode surface of the tip by means of the optical microscope.
The wire flow was evaluated from the distortion value (h/ I x 100) by splicing the electrodes on the semiconductor element to the external leads by means of the high-speed automatic bonder and setting the assembly in the the metal mold of the thin mold to pour the sealing resin into the metal mold followed by observing the obtained package by means of X-rays to measure the distortion of the bonding wire due to the sealing resin, that is the maximum curved distance (h) from the straight splicing and the splicing span ( 2 ).
Mark O : the distortion value amounts to less than 3 % (suitable for the thin package).
Mark A : the distortion value amounts to 3 to 10 %.
Mark x: the distortion value amounts to 11 % or more.
The shape of the ball was evaluated from three standpoints, that is external appearance, true sphericity and cavities, by observing the gold alloy ball, which is obtained by the electric torch discharge by the use of the high-speed automatic bonder, by means of the scanning electron microscope.
At first, the external appearance was evaluated from the condition of the oxides generated on the surface of the ball.
Mark C : the surface of the ball is smooth.
Mark A : the oxides are slightly confirmed on the surface of the ball.
Mark x : the oxides are clearly confirmed on the surface of the ball.
Next, the true sphericity was evaluated from the difference between the long diameter ( u m) and the short diameter ( a m) of the ball having the diameter (75 a m) about 3 times the diameter of the wire.
Mark 0: : 3 a m or less Mark A : 3 to 6 m Mark x : 6 u m or more At last, the cavities were evaluated from the generating condition of the contracting holes at the bottom portion of the ball.
Mark O : the contracting holes are not confirmed at all.
Mark A : the contracting holes are slightly confirmed.
Mark x : the contracting holes are clearly confirmed.
As understood from the results shown in Table 2, according to the preferred embodiments 4 to 10 of the present invention, the ratio among yttrium, calcium, beryllium and lead added, their total quantity and the quantity of the inevitable impurities are ideal, so that the heat resistance and the strengths at the normal temperature and high temperatures are improved, the splicing loop height being able to be reduced, also the influence of the wire flow due to the sealing resin being negligible, and also the shape of the ball being favorable, and thus the reliable splicing can be achieved. In addition, according to the preferred embodiment 1, the total quantity of the elements added is slightly less than the preferable range and thus the loop height is slightly higher than that according to the above described preferred embodiments 4 to 10 and the distortion value amounted to 3 to 10 % but special disadvantages did not occur in practical use. Moreover, according to the preferred embodiments 2, 3 and 11, the total quantity of the elements added slightly exceeds the preferable range and thus the difference between the long diameter and the short diameter amounted to 3 to 6 m and the cavities were slightly confirmed but special disadvantages did not occur in practical use. It is judged from the above described results that special disadvantages do not occur in practical use according to the preferred embodiments 1 to 11 shown in Table 1. In particular, according to the preferred embodiments 4 to 10, the desired object of the present invention can be satisfactorily achieved.
Contrary to the present invention, according to the comparative example 1, the total quantity of the elements added is 5.1 ppm, that is extremely little, and thus the loop height was remarkably increased and the wire flow occurred, Consequently, the fine gold alloy wire according to the comparative example 1 could not be put to practical use. Furthermore, according to the comparative examples 2, 3, the total quantity of the elements added exceeds the permissible limit, and, according to the comparative example 3, also the ratio of lead to beryllium is greatly deviated from the permissible limit, so that the shape of the ball is unfavorable. Consequently, the fine gold alloy wires according to the comparative examples 2, 3 could not be put to practical use.
As above described, according to the present invention, in the gold alloys containing yttrium, calcium, beryllium and lead, they are contained in the ratio of yttrium calcium : beryllium : lead = 1 : 0.5 to 2.0 : 0.1 to 1.0 : 0.1 to 1.0, the minimum quantity of yttrium being 5 ppm by weight, their total quantity being 80 ppm or less by weight, and the rest being inevitable impurities and gold, and, in the gold alloys containing yttrium, calcium, beryllium and lead, they are contained in the ratio of yttrium : calcium beryllium : lead = 1 : 0.7 to 1.5 : 0.2 to 0.6 : 0.1 to 0.5, yttrium being contained in a quantity of 10 to 30 ppm by weight, their total quantity being 20 to 60 ppm by weight, and the rest being inevitable impurities and gold, so that the following superior effects can be taken.
That is to say, both the strength at the normal temperature and the strengths at the high temperatures are improved, the splicing loop height being able to be reduced, the wire flow due to the sealing resin being able to prevent from occurring, the high-speed automatic bonder being sufficiently applicable, and also the ball being formed in the true spherical shape, so that the fine wires made of the gold alloys according to the present invention can be satisfactorily put to practical use with high reliability in particular as the bonding wires of the thin packaging devices and thus have the great merit in the industrial applications.

Claims (5)

CLAIMS:
1. A gold alloy for use in semiconductor components containing yttrium, calcium, beryllium and lead, characterised in that these elements are contained in the ratio of Y : Ca : Be : Pb = 1 : 0.5 to 2.0 : 0.1 to 1.0 0.1 to 1.0, the minimum content of yttrium being 5 ppm by weight, the total content of said elements being 80 ppm or less by weight, and the balance being inevitable impurities and gold.
2. A gold alloy according to claim 1 wherein the ratio of Y : Ca : Be : Pb is 1 : 0.7 to 1.5 : 0.2 to 0.6 0.1 to 0.5.
3. A gold alloy according to claim 1 or claim 2 wherein the yttrium content is 10 to 30 ppm by weight.
4. A gold alloy according to any preceding claim wherein the total content of said element is 20 to 60 ppm by weight.
5. A gold alloy according to claim 1 substantially as herein described with reference to any one of the specific examples.
GB9405839A 1993-03-31 1994-03-24 Gold alloy for use in semiconductor element Expired - Fee Related GB2276632B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5945065A (en) * 1996-07-31 1999-08-31 Tanaka Denshi Kogyo Method for wedge bonding using a gold alloy wire

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5945065A (en) * 1996-07-31 1999-08-31 Tanaka Denshi Kogyo Method for wedge bonding using a gold alloy wire

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GB2276632B (en) 1996-02-28
KR940022687A (en) 1994-10-21
KR0157474B1 (en) 1998-12-01
GB9405839D0 (en) 1994-05-11
SG44578A1 (en) 1997-12-19
TW284791B (en) 1996-09-01

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