GB1266513A - - Google Patents

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Publication number
GB1266513A
GB1266513A GB1266513DA GB1266513A GB 1266513 A GB1266513 A GB 1266513A GB 1266513D A GB1266513D A GB 1266513DA GB 1266513 A GB1266513 A GB 1266513A
Authority
GB
United Kingdom
Prior art keywords
energized
array
current
winding
core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1266513A publication Critical patent/GB1266513A/en
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • G11C11/06014—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit
    • G11C11/06021—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit with destructive read-out
    • G11C11/06028—Matrixes
    • G11C11/06035—Bit core selection for writing or reading, by at least two coincident partial currents, e.g. "bit"- organised, 2L/2D, or 3D

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

1,266,513. Magnetic core storage. ELECTRONIC MEMORIES Inc. 19 May, 1969, No. 25509/69. Heading G4C. A magnetic core matrix is modified whereby a plurality of planar arrays can be accessed simultaneously. Previously each array was written into or read from individually, hence the quantity of switching and selecting hardware is reduced. Prior Art (Fig. 1, not shown).-This is a so- - called 2“ D high-speed memory system having a number of planar arrays each accessed separately. Each core in an array is accessed using coincident X,Y enabling pulses. The Apparatus.-An array comprises a number of core planes 1 arranged in one plane, and the X and sensing lines for each column of each core plane are energized separately as before. A Y winding passes through each row of cores in an array and is connected to a common bus. In this embodiment there are 4 arrays disposed in a square, the busses of adjacent planes in the square being connected together. One end of each bus is connected to a sink switch and the other ends of each Y winding is connected to a junction between two diodes O, the other ends of the diodes being connected through respective transistors which act as drive or current switches and are connected to a current source. Writing.-One sink switch is energized to allow a current flow in one direction, another sink switch is energized to allow current flow in another direction and the two current switches are enabled in each array. Thus current flows through the Y winding of all arrays and selected X lines may be energized to cause writing. Reading.-The direction of current flow through the Y windings is reversed using the sink switches and the selected sensing lines are energized. It is possible to energize only one row winding, two embodiments of current sources are described (Figs. 3 and 4, not shown), and the arrangement may be used for 3D systems.
GB1266513D 1969-05-19 1969-05-19 Expired GB1266513A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2550969 1969-05-19

Publications (1)

Publication Number Publication Date
GB1266513A true GB1266513A (en) 1972-03-08

Family

ID=10228846

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1266513D Expired GB1266513A (en) 1969-05-19 1969-05-19

Country Status (1)

Country Link
GB (1) GB1266513A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2787507A3 (en) * 2008-01-15 2015-04-29 Micron Technology, Inc. Resistive memory cells and their programming, reading and operating methods
US9257648B2 (en) 2011-02-24 2016-02-09 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US9257430B2 (en) 2008-06-18 2016-02-09 Micron Technology, Inc. Semiconductor construction forming methods
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US9406878B2 (en) 2010-11-01 2016-08-02 Micron Technology, Inc. Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells, and methods of forming memory cells
US9412421B2 (en) 2010-06-07 2016-08-09 Micron Technology, Inc. Memory arrays
US9620174B2 (en) 2010-12-02 2017-04-11 Micron Technology, Inc. Arrays of nonvolatile memory cells comprising a repetition of a unit cell, arrays of nonvolatile memory cells comprising a combination of vertically oriented and horizontally oriented memory cells, and arrays of vertically stacked tiers of nonvolatile memory cells
US9705078B2 (en) 2010-10-21 2017-07-11 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2787507A3 (en) * 2008-01-15 2015-04-29 Micron Technology, Inc. Resistive memory cells and their programming, reading and operating methods
US11393530B2 (en) 2008-01-15 2022-07-19 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9343145B2 (en) 2008-01-15 2016-05-17 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US10790020B2 (en) 2008-01-15 2020-09-29 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US10262734B2 (en) 2008-01-15 2019-04-16 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9805792B2 (en) 2008-01-15 2017-10-31 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9257430B2 (en) 2008-06-18 2016-02-09 Micron Technology, Inc. Semiconductor construction forming methods
US9559301B2 (en) 2008-06-18 2017-01-31 Micron Technology, Inc. Methods of forming memory device constructions, methods of forming memory cells, and methods of forming semiconductor constructions
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US9666801B2 (en) 2008-07-02 2017-05-30 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US9697873B2 (en) 2010-06-07 2017-07-04 Micron Technology, Inc. Memory arrays
US9887239B2 (en) 2010-06-07 2018-02-06 Micron Technology, Inc. Memory arrays
US10241185B2 (en) 2010-06-07 2019-03-26 Micron Technology, Inc. Memory arrays
US9412421B2 (en) 2010-06-07 2016-08-09 Micron Technology, Inc. Memory arrays
US10613184B2 (en) 2010-06-07 2020-04-07 Micron Technology, Inc. Memory arrays
US10656231B1 (en) 2010-06-07 2020-05-19 Micron Technology, Inc. Memory Arrays
US10746835B1 (en) 2010-06-07 2020-08-18 Micron Technology, Inc. Memory arrays
US10859661B2 (en) 2010-06-07 2020-12-08 Micron Technology, Inc. Memory arrays
US9705078B2 (en) 2010-10-21 2017-07-11 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell
US9406878B2 (en) 2010-11-01 2016-08-02 Micron Technology, Inc. Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells, and methods of forming memory cells
US9620174B2 (en) 2010-12-02 2017-04-11 Micron Technology, Inc. Arrays of nonvolatile memory cells comprising a repetition of a unit cell, arrays of nonvolatile memory cells comprising a combination of vertically oriented and horizontally oriented memory cells, and arrays of vertically stacked tiers of nonvolatile memory cells
US9257648B2 (en) 2011-02-24 2016-02-09 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells

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Legal Events

Date Code Title Description
PS Patent sealed
435 Patent endorsed 'licences of right' on the date specified (sect. 35/1949)
PLNP Patent lapsed through nonpayment of renewal fees