FR2835096B1 - Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin - Google Patents

Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin

Info

Publication number
FR2835096B1
FR2835096B1 FR0200762A FR0200762A FR2835096B1 FR 2835096 B1 FR2835096 B1 FR 2835096B1 FR 0200762 A FR0200762 A FR 0200762A FR 0200762 A FR0200762 A FR 0200762A FR 2835096 B1 FR2835096 B1 FR 2835096B1
Authority
FR
France
Prior art keywords
substrate
nucleation layer
epitaxial growth
growth temperature
bonding interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0200762A
Other languages
English (en)
Other versions
FR2835096A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0200762A priority Critical patent/FR2835096B1/fr
Application filed filed Critical
Priority to JP2003562365A priority patent/JP2005515150A/ja
Priority to CNB038042789A priority patent/CN100343424C/zh
Priority to PCT/EP2003/000693 priority patent/WO2003062507A2/fr
Priority to KR1020047011356A priority patent/KR100760066B1/ko
Priority to AT03702513T priority patent/ATE534759T1/de
Priority to EP03702513A priority patent/EP1468128B1/fr
Priority to TW092101401A priority patent/TWI259221B/zh
Priority to US10/349,295 priority patent/US6964914B2/en
Publication of FR2835096A1 publication Critical patent/FR2835096A1/fr
Application granted granted Critical
Publication of FR2835096B1 publication Critical patent/FR2835096B1/fr
Priority to US11/212,795 priority patent/US7407869B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/40AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
FR0200762A 2000-11-27 2002-01-22 Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin Expired - Lifetime FR2835096B1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
FR0200762A FR2835096B1 (fr) 2002-01-22 2002-01-22 Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin
CNB038042789A CN100343424C (zh) 2002-01-22 2003-01-21 一种用于制造由单晶半导体材料制成的无支撑衬底的方法
PCT/EP2003/000693 WO2003062507A2 (fr) 2002-01-22 2003-01-21 Procede de fabrication d'un substrat autoportant realise en materiau semi-conducteur monocristallin
KR1020047011356A KR100760066B1 (ko) 2002-01-22 2003-01-21 단결정 반도체 재료로 제작된 프리-스탠딩 기판의 제조 방법
AT03702513T ATE534759T1 (de) 2002-01-22 2003-01-21 Verfahren zur herstellung eines freistehenden substrates aus monokristallinem halbleitermaterial
EP03702513A EP1468128B1 (fr) 2002-01-22 2003-01-21 Procédé de fabrication d'un substrat auto-porteur réalisé en matériau semi-conducteur monocristallin
JP2003562365A JP2005515150A (ja) 2002-01-22 2003-01-21 単結晶半導体材料製自立基板の製造方法
TW092101401A TWI259221B (en) 2002-01-22 2003-01-22 Method for manufacturing a free-standing substrate made of monocrystalline semi-conductor material
US10/349,295 US6964914B2 (en) 2002-01-22 2003-01-22 Method of manufacturing a free-standing substrate made of monocrystalline semi-conductor material
US11/212,795 US7407869B2 (en) 2000-11-27 2005-08-29 Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0200762A FR2835096B1 (fr) 2002-01-22 2002-01-22 Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin

Publications (2)

Publication Number Publication Date
FR2835096A1 FR2835096A1 (fr) 2003-07-25
FR2835096B1 true FR2835096B1 (fr) 2005-02-18

Family

ID=27589549

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0200762A Expired - Lifetime FR2835096B1 (fr) 2000-11-27 2002-01-22 Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin

Country Status (9)

Country Link
US (1) US6964914B2 (fr)
EP (1) EP1468128B1 (fr)
JP (1) JP2005515150A (fr)
KR (1) KR100760066B1 (fr)
CN (1) CN100343424C (fr)
AT (1) ATE534759T1 (fr)
FR (1) FR2835096B1 (fr)
TW (1) TWI259221B (fr)
WO (1) WO2003062507A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3121275A1 (fr) * 2021-03-24 2022-09-30 Soitec Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic poly-cristallin

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US7407869B2 (en) * 2000-11-27 2008-08-05 S.O.I.Tec Silicon On Insulator Technologies Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
JP2005064188A (ja) * 2003-08-11 2005-03-10 Sumitomo Electric Ind Ltd 基板の回収方法および再生方法、ならびに半導体ウエハの製造方法
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DE10355600B4 (de) 2003-11-28 2021-06-24 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiterchip und Verfahren zur Herstellung von Halbleiterchips
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FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
FR2868204B1 (fr) * 2004-03-25 2006-06-16 Commissariat Energie Atomique Substrat de type semi-conducteur sur isolant comportant une couche enterree en carbone diamant
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US7294324B2 (en) * 2004-09-21 2007-11-13 Cree, Inc. Low basal plane dislocation bulk grown SiC wafers
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US8674405B1 (en) * 2005-04-13 2014-03-18 Element Six Technologies Us Corporation Gallium—nitride-on-diamond wafers and devices, and methods of manufacture
US7605055B2 (en) * 2005-06-02 2009-10-20 S.O.I.Tec Silicon On Insulator Technologies Wafer with diamond layer
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US7273798B2 (en) * 2005-08-01 2007-09-25 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Gallium nitride device substrate containing a lattice parameter altering element
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US7601271B2 (en) * 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion
FR2894067B1 (fr) * 2005-11-28 2008-02-15 Soitec Silicon On Insulator Procede de collage par adhesion moleculaire
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TWI334164B (en) * 2006-06-07 2010-12-01 Ind Tech Res Inst Method of manufacturing nitride semiconductor substrate and composite material substrate
FR2905799B1 (fr) 2006-09-12 2008-12-26 Soitec Silicon On Insulator Realisation d'un substrat en gan
CN100505165C (zh) * 2006-12-01 2009-06-24 东莞市中镓半导体科技有限公司 一种制备氮化镓单晶衬底的方法
US7943485B2 (en) * 2007-01-22 2011-05-17 Group4 Labs, Llc Composite wafers having bulk-quality semiconductor layers and method of manufacturing thereof
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FR2914494A1 (fr) * 2007-03-28 2008-10-03 Soitec Silicon On Insulator Procede de report d'une couche mince de materiau
TWI437696B (zh) 2007-09-21 2014-05-11 Semiconductor Energy Lab 半導體裝置及其製造方法
SG181071A1 (en) * 2009-12-15 2012-07-30 Soitec Silicon On Insulator Process for recycling a substrate.
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
US9142412B2 (en) 2011-02-03 2015-09-22 Soitec Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
US9082948B2 (en) 2011-02-03 2015-07-14 Soitec Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
US8436363B2 (en) 2011-02-03 2013-05-07 Soitec Metallic carrier for layer transfer and methods for forming the same
FR2975222A1 (fr) * 2011-05-10 2012-11-16 Soitec Silicon On Insulator Procede de fabrication d'un substrat semiconducteur
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
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KR101420265B1 (ko) * 2011-10-21 2014-07-21 주식회사루미지엔테크 기판 제조 방법
FR2985601B1 (fr) * 2012-01-06 2016-06-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat et structure semiconducteur
US8916483B2 (en) 2012-03-09 2014-12-23 Soitec Methods of forming semiconductor structures including III-V semiconductor material using substrates comprising molybdenum
FR3027250B1 (fr) * 2014-10-17 2019-05-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct via des couches metalliques peu rugueuses
JP6572694B2 (ja) 2015-09-11 2019-09-11 信越化学工業株式会社 SiC複合基板の製造方法及び半導体基板の製造方法
JP6544166B2 (ja) 2015-09-14 2019-07-17 信越化学工業株式会社 SiC複合基板の製造方法
JP6582779B2 (ja) 2015-09-15 2019-10-02 信越化学工業株式会社 SiC複合基板の製造方法
JP6515757B2 (ja) 2015-09-15 2019-05-22 信越化学工業株式会社 SiC複合基板の製造方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3121275A1 (fr) * 2021-03-24 2022-09-30 Soitec Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic poly-cristallin

Also Published As

Publication number Publication date
EP1468128A2 (fr) 2004-10-20
WO2003062507A2 (fr) 2003-07-31
WO2003062507A3 (fr) 2004-01-15
US6964914B2 (en) 2005-11-15
EP1468128B1 (fr) 2011-11-23
CN1636087A (zh) 2005-07-06
JP2005515150A (ja) 2005-05-26
US20040023468A1 (en) 2004-02-05
CN100343424C (zh) 2007-10-17
KR100760066B1 (ko) 2007-09-18
FR2835096A1 (fr) 2003-07-25
ATE534759T1 (de) 2011-12-15
KR20040077773A (ko) 2004-09-06
TW200409837A (en) 2004-06-16
TWI259221B (en) 2006-08-01

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