FR2707425A1 - Structure of semiconductor material, application to the production of a transistor and method of production - Google Patents
Structure of semiconductor material, application to the production of a transistor and method of production Download PDFInfo
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- FR2707425A1 FR2707425A1 FR9308472A FR9308472A FR2707425A1 FR 2707425 A1 FR2707425 A1 FR 2707425A1 FR 9308472 A FR9308472 A FR 9308472A FR 9308472 A FR9308472 A FR 9308472A FR 2707425 A1 FR2707425 A1 FR 2707425A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000463 material Substances 0.000 title claims description 14
- 238000000034 method Methods 0.000 title description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 38
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 33
- 239000012212 insulator Substances 0.000 claims description 24
- 238000000407 epitaxy Methods 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims 1
- 229910017083 AlN Inorganic materials 0.000 abstract 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 abstract 1
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 108091006146 Channels Proteins 0.000 description 15
- 239000000377 silicon dioxide Substances 0.000 description 9
- 239000000969 carrier Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 125000002103 4,4'-dimethoxytriphenylmethyl group Chemical group [H]C1=C([H])C([H])=C(C([H])=C1[H])C(*)(C1=C([H])C([H])=C(OC([H])([H])[H])C([H])=C1[H])C1=C([H])C([H])=C(OC([H])([H])[H])C([H])=C1[H] 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910017214 AsGa Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011979 disease modifying therapy Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012053 enzymatic serum creatinine assay Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000002202 sandwich sublimation Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
STRUCTURE EN MATERIAU SEMICONDUCTEUR, APPLICATION A LASTRUCTURE OF SEMICONDUCTOR MATERIAL, APPLICATION TO
REALISATION D'UN TRANSISTOR ET PROCEDE DE REALISATION PRODUCTION OF A TRANSISTOR AND METHOD OF PRODUCTION
L'invention concerne une structure en matériau semiconducteur, son application à la réalisation d'un transistor (un MISFET ou un MOS notamment) et un The invention relates to a structure of semiconductor material, its application to the production of a transistor (a MISFET or a MOS in particular) and a
procédé de réalisation.production process.
Dans la fabrication de composants semiconducteurs, la réalisation d'une In the manufacture of semiconductor components, the realization of a
couche d'isolant sur le semiconducteur est un problème omniprésent. layer of insulation on the semiconductor is a pervasive problem.
On peut citer en exemple: - la fabrication de MISFETs (Metal Insulator Field Effect Transistors): des transistors à effet de champ dans lesquels la grille de commande est isolée du canal par un isolant; - la passivation de surface afin d'éliminer les effets parasites tels que la We can cite as an example: - the manufacture of MISFETs (Metal Insulator Field Effect Transistors): field effect transistors in which the control gate is isolated from the channel by an insulator; - surface passivation in order to eliminate parasitic effects such as
conduction de surface, ou pour améliorer la tension de claquage. surface conduction, or to improve breakdown voltage.
Les caractéristiques essentielles requises de cette couche d'isolant sont: - un fort champ de claquage On peut citer la silice comme étant un des isolants les plus utilisés. Les The essential characteristics required of this insulating layer are: - a strong breakdown field Mention may be made of silica as being one of the most used insulators. The
meilleurs champs de claquage pour la silice sont environ de 12.106 V/cm. best breakdown fields for silica are approximately 12.106 V / cm.
Le champ de claquage indique la capacité de l'isolant à soutenir une tension et partant à pouvoir commander les charges dans le canal dans le cas du The breakdown field indicates the capacity of the insulator to support a voltage and therefore to be able to control the loads in the channel in the case of
MISFET.MISFET.
- une faible densité d'état d'interface En général les isolants déposés sur des semiconducteurs sont amorphes et - a low density of interface state In general the insulators deposited on semiconductors are amorphous and
de ce fait ils possèdent des états électroniques à l'interface avec le semiconducteur. therefore they have electronic states at the interface with the semiconductor.
Ces états électroniques sont nuisibles à plusieurs titres. Dans le cas de risolant de grille, ils écrantent l'effet du champ électrique de conmmande et limitent la possibilité de moduler le nombre de porteurs sous la grille. Ils introduisent égalemerit des états d'interface qui jouent le rôle de centres diffuseurs pour les porteurs dans le canal et limitent ainsi leur mobilité. La détérioration de la mobilité de canal est une des These electronic statements are harmful for several reasons. In the case of grid riser, they screen the effect of the electric control field and limit the possibility of modulating the number of carriers under the grid. They also introduce interface states which act as diffusing centers for the carriers in the channel and thus limit their mobility. Deterioration of canal mobility is one of the
limitations des MOSFETs sur silicium. limitations of MOSFETs on silicon.
- une forte résistivité afin d'assurer l'isolation entre la grille et le canal et de minimiser - high resistivity to ensure insulation between the grid and the channel and to minimize
les courants de fuite.leakage currents.
Pour les meilleures silices, la résistivité est supérieure à 1015 Ohm.cm. For the best silicas, the resistivity is greater than 1015 Ohm.cm.
Le problème qui consiste à trouver le bon isolant pour un semiconducteur The problem of finding the right insulator for a semiconductor
donné, pour une application donnée est, en général, extrêmement difficile. given, for a given application is, in general, extremely difficult.
On peut remarquer qu'une des raisons qui ont créé le succès du silicium est que la silice est un isolant naturel répondant de manière satisfaisante à toutes les exigences ci-dessus. La silice sur silicium présente une densité d'états d'interface It can be noted that one of the reasons which have created the success of silicon is that silica is a natural insulator satisfactorily meeting all of the above requirements. Silica on silicon has a density of interface states
faible, pour laquelle les meilleurs résultats sont au niveau de quelques 1010cmr2eV-1. weak, for which the best results are at the level of a few 1010cmr2eV-1.
On peut également remarquer que l'obtention d'un couple semiconducteur/isolant dont l'interface est bonne n'est un problème résolu, malgré de très nombreux efforts, ni sur AsGa ni sur InP. Ceux-ci sont pourtant des It can also be noted that obtaining a semiconductor / insulator couple whose interface is good is not a problem solved, despite very many efforts, neither on AsGa nor on InP. These are however
semiconducteurs importants d'un point de vue technologique. technologically important semiconductors.
Afin de remédier aux problèmes cités plus haut, on pourrait épitaxier un isolant sur le semiconducteur. 11 est en effet connu par les spécialistes des surfaces, que sous certaines conditions, les hétérojonctions entre deux matériaux cristallins (un semiconducteur et un isolant) n'induisent pas d'états électroniques dans la bande interdite du semiconducteur. On peut ainsi obtenir des interfaces de grande qualité en In order to remedy the problems mentioned above, an insulator could be epitaxial on the semiconductor. It is in fact known to surface specialists that, under certain conditions, heterojunctions between two crystalline materials (a semiconductor and an insulator) do not induce electronic states in the forbidden band of the semiconductor. We can thus obtain high quality interfaces by
ce qui concerne le nombre d'états et la diffusion d'interface. regarding the number of states and interface diffusion.
Cette idée est à la base d'une sorte de transistor à effet de champ que l'on nomme le DMT (Doped channel Mis-like Transistor) et qui a été décrit dans la thèse de B. Bonte (Université de Lille, Juin 1990). Ainsi qu'il est décrit dans cette thèse, il est intéressant de pouvoir épitaxier un isolant sur semiconducteur, car il serait ainsi possible de s'affranchir des problèmes d'état d'interface, tout en gardant certains des avantages du MISFET. Toutefois, il est très difficile de trouver un couple isolant/semiconducteur dont les paramètres de maille soient accordés. Dans les DMTs décrit dans la thèse de B. Bonte, le canal peut être fait en GaInAs et l'isolant serait de r'AIGaAs dont le paramètre de maille est accordé. L'AlGaAs est utilisé comme isolant faute de trouver un véritable isolant épitaxiable sur GaInAs, mais son utilisafion ne This idea is the basis of a kind of field effect transistor called DMT (Doped channel Mis-like Transistor) and which was described in the thesis of B. Bonte (University of Lille, June 1990 ). As described in this thesis, it is interesting to be able to epitaxialize an insulator on a semiconductor, because it would thus be possible to overcome interface state problems, while retaining some of the advantages of MISFET. However, it is very difficult to find an insulating / semiconductor pair whose mesh parameters are matched. In the DMTs described in the thesis of B. Bonte, the channel can be made in GaInAs and the insulator would be r'AIGaAs whose mesh parameter is tuned. AlGaAs is used as an insulator because there is no real epitaxisable insulator on GaInAs, but its use does not
permnnet pas au DMT de présenter tous les avantages d'un véritable MISFET. does not allow DMT to present all the advantages of a real MISFET.
Les différents polytypes du carbure de silicium sont des semiconducteurs à grande bande interdite dont les qualités intrinsèques leur conf/rent des avantages décisifs sur le silicium ou l'arséniure de gallium pour un très grand nombre d'applications dont on pourra citer: - le fonctionnement à haute température et dans des milieux corrosifs; - l'immunité aux radiations; - les composants de puissance fonctionnant du continu aux hyperfréquences; The various polytypes of silicon carbide are semiconductors with a large forbidden band, the intrinsic qualities of which give them decisive advantages over silicon or gallium arsenide for a very large number of applications, which may be mentioned: - operation at high temperatures and in corrosive environments; - immunity to radiation; - power components operating from continuous to microwave;
- l'intégration monolithique extrêmement dense. - extremely dense monolithic integration.
Parmi les polytypes (Cil y en a plus d'une centaine en tout), les principaux sont le 3C (cubique), le 2H, le 4H, et le 6H (hexagonaux). Leurs propriétés varient Among the polytypes (there are more than a hundred in all), the main ones are 3C (cubic), 2H, 4H, and 6H (hexagonal). Their properties vary
beaucoup (voir un article de M Van Vliet et al. pour l'introduction: Ann. Rev. mater. a lot (see an article by M Van Vliet et al. for the introduction: Ann. Rev. mater.
Sci. 1988. 18:381-421). Jusqu'à récemment, la recherche sur le SiC a été ralentie par le peu de progrès en croissance des monocristaux. Or, il existe actuellement des techniques de préparation de monocristaux Sci. 1988. 18: 381-421). Until recently, research on SiC has been slowed by little progress in growing single crystals. However, there are currently techniques for preparing single crystals
de SiC (dans ses polytypes 4H et 6H) qui sont de très bonne qualité. of SiC (in its 4H and 6H polytypes) which are of very good quality.
Mais il reste un bon nombre de problèmes techniques à résoudre pour pouvoir tirer tout son potentiel du carbure de silicium. Parmi ces problèmes, il y a But there are a good number of technical problems to be solved in order to be able to draw its full potential from silicon carbide. Among these problems are
celui du choix d'un bon isolant.the choice of a good insulator.
Le choix évident en premier lieu, la silice, a été étudié et semble prometteur en ce qui concerne la densité d'états d'interface lorsqu'elle est faite par oxydation sur un matériau SiC dopé n. Chaudhry (J. Appl. phys. 69, 7319 (1991)) a montré que l'on pouvait obtenir quelques 1011 cm-2eV1 en oxydant le carbure de silicium. Toutefois, la composition de cette silice montre qu'elle possède un fort taux de carbone, et à ce titre elle est loin d'&être optimisée. Des transistors MOS avec canal n ont été faits sur SiC (CREE Research, North Carolina, USA, cité dans larticle d'introduction de G. Kelner et M. Shur, 1991 International Semiconductor Device Research Symposium, Charlottesville, Virginia, USA, 4-6 Décembre 1991), en utilisant de la silice comme isolant avec de bons résultats, mais les composants MOS avec canal p semblent plus difficiles à réaliser, en partie à cause de la moindre qualité de rinterface SiO2/SiC dopé p. The obvious choice in the first place, silica, has been studied and seems promising with regard to the density of interface states when it is made by oxidation on an n-doped SiC material. Chaudhry (J. Appl. Phys. 69, 7319 (1991)) has shown that some 1011 cm-2eV1 can be obtained by oxidizing silicon carbide. However, the composition of this silica shows that it has a high carbon content, and as such it is far from being optimized. N-channel MOS transistors have been made on SiC (CREE Research, North Carolina, USA, cited in the introductory article by G. Kelner and M. Shur, 1991 International Semiconductor Device Research Symposium, Charlottesville, Virginia, USA, 4- December 6, 1991), using silica as an insulator with good results, but the MOS components with p channel seem more difficult to produce, in part because of the lower quality of the SiO2 / SiC doped p interface.
L'invention permet de résoudre ce problème. The invention solves this problem.
L'invention concerne donc une structure en matériaux semiconducteurs comportant au moins une couche de carbure de silicium recouverte d'une première couche d'isolant, caractérisée en ce que le carbure de silicium est monocristallin et que The invention therefore relates to a structure made of semiconductor materials comprising at least one layer of silicon carbide covered with a first layer of insulator, characterized in that the silicon carbide is monocrystalline and that
la couche d'isolant est également monocristalline. the insulating layer is also monocrystalline.
L'invention concerne également une application de la structure à la réalisation d'un transistor, caractérisée en ce qu'elle comporte sur un canal en carbure de silicium monocristallin reliant la source et le drain, une couche d'isolant en matériau The invention also relates to an application of the structure to the production of a transistor, characterized in that it comprises, on a monocrystalline silicon carbide channel connecting the source and the drain, an insulating layer of material
monocrista lin.monocrysta linen.
Enfin rinvention concerne un procédé de réalisation d'un composant semiconducteur caractérisé en ce que la couche de carbure de silicium et la couche Finally, the invention relates to a process for producing a semiconductor component characterized in that the layer of silicon carbide and the layer
d'isolant sont déposées par épitaxie. of insulation are deposited by epitaxy.
Les différents objets et caractéristiques de rinvention apparaîtront plus The different objects and characteristics of the invention will appear more
clairement dans la description qui va suivre faite à titre d'exemple et dans les figures clearly in the following description given by way of example and in the figures
annexées qui représentent: - la figure 1, un premier exemple de réalisation d'un dispositif selon l'invention; - les figures 2 et 3, un exemple de procédé de réalisation du dispositif de la figure 1; - la figure 4, un autre exemple de réalisation du dispositif selon l'invention. L'objet de l'invention est de réaliser une couche d'isolant sur du SiC attached which represent: - Figure 1, a first embodiment of a device according to the invention; - Figures 2 and 3, an example of the embodiment of the device of Figure 1; - Figure 4, another embodiment of the device according to the invention. The object of the invention is to produce an insulating layer on SiC
monocristallin par épitaxie d'un composé nitruré sous forme cristalline: ByAlix. monocrystalline by epitaxy of a nitrided compound in crystalline form: ByAlix.
yGaxN. Il a été démontré (R Davis, communication at the 7th Trieste Semiconductor symposium) que rAIN pouvait être déposé sur le SiC 6H, en épitaxie parfaite avec le substrat, et ce jusqu'à des épaisseurs de 500 A. L'épitaxie d'AIN sur SiC est d'ailleurs connue depuis longtemps (W. F. Knippenberg and G. Verspui, Proceedings of the International Conference on SiC, University Park PA, 1968, Pergamon, New Yorsk). Toutefois, l'intérêt cité pour l'épitaxie d'AIN sur SiC est de réaliser un matériau épitaxié de haute qualité et de permettre ainsi l'étude des yGaxN. It has been shown (R Davis, communication at the 7th Trieste Semiconductor symposium) that rAIN could be deposited on SiC 6H, in perfect epitaxy with the substrate, up to thicknesses of 500 A. Epinaxy of AIN on SiC has been known for a long time (WF Knippenberg and G. Verspui, Proceedings of the International Conference on SiC, University Park PA, 1968, Pergamon, New Yorsk). However, the interest cited for the AIN epitaxy on SiC is to produce a high-quality epitaxial material and thus allow the study of
composés AllxGaxN pour leurs propriétés semiconductrices et optiques. AllxGaxN compounds for their semiconductor and optical properties.
L'objet de l'invention est de réaliser une structure en matériaux semiconducteurs dans laquelle les propriétés isolantes de I'AIN sont effectivement utilisées. The object of the invention is to produce a structure of semiconductor materials in which the insulating properties of the AIN are effectively used.
L'objet de rinvention est d'utiliser la structure (SiC monocfistalin/BAll. The object of the invention is to use the structure (SiC monocfistalin / BAll.
x.yGaxN) comme couple de base semiconducteur/isolant. Cela est différent par rapport aux études existantes sur r'épitaxie de All.xGaxN sur SiC qui ont pour but d'étudier les composés nitrurés pour leurs propriétés intrinsèques et ne se servent du SiC que comme substrat L'isolant sera plus particulièrement composé d'AIN et le semiconducteur x.yGaxN) as basic semiconductor / insulator couple. This is different from the existing studies on the epitaxy of All.xGaxN on SiC which aim to study nitrided compounds for their intrinsic properties and only use SiC as a substrate. The insulator will be more particularly composed of AIN and the semiconductor
sera du SiC monocristallin sous une de ses nombreuses formes (3C, 4I-H, 6H ou autre). will be monocrystalline SiC in one of its many forms (3C, 4I-H, 6H or other).
L'intérêt de l'invention réside en la perfection de l'interface, dont dérivent tous les The advantage of the invention lies in the perfection of the interface, from which all the
avantages mentionnés en introduction. advantages mentioned in the introduction.
Nous allons maintenant décrire à titre d'exemple des structures tirant We will now describe as an example structures pulling
avantage de cette interface, ainsi que leur mode de réalisation. advantage of this interface, as well as their embodiment.
I/ MISFET SICI / MISFET SIC
La structure représentant une des réalisations possibles décrites par la The structure representing one of the possible achievements described by the
présente invention est schématisée en figure 1. The present invention is shown diagrammatically in FIG. 1.
La structure est caractérisée en ce qu'elle est fabriquée sur un substrat 1 de carbure de silicium, de polytype 6H par exemple, monocristallin, semi-isolant. En ce qu'elle comporte un canal 2 de type n sur lequel se trouve un isolant 3 monocristallin épitaxié (de 'AIN par exemple), dont linterface avec le canal est de grande perfection. Entre la couche d'AIN et la métallisation de grille 5, on peut The structure is characterized in that it is manufactured on a substrate 1 of silicon carbide, of polytype 6H for example, monocrystalline, semi-insulating. In that it comprises an n-type channel 2 on which there is an epitaxial monocrystalline insulator 3 (from 'AIN for example), whose interface with the channel is of great perfection. Between the AIN layer and the gate metallization 5, we can
intercaler une deuxième couche disolant 4 (amorphe ou cristallin) si besoin est. insert a second desolating layer 4 (amorphous or crystalline) if necessary.
L'épaisseur de la couche 3 d'AIN peut varier de In à 200 nm suivant les applications. Les contacts ohmniques de drain 6 et de source 7 sont déposés sur des zones 8 et 9 ayant été dopées plus fortement. Les différentes dimensions et valeurs des paramètres du MISFET seront choisies suivant les techniques connues. En particulier, elles pourront être égale à: - la longueur de grille Lg = 0.5 Mam - la distance grifflle source Lgs = 1 pim - la distance grille drain Lgd = 3.5 glm - l'épaisseur du canal a = 0.25 gim - le dopage du canal Nd = 3.1017 cm-3 - le développement de la grille W = 1 mm Cette structure est très simplifiée, mais montre la caractéristique essentielle de rinvention qui est d'avoir un canal de transport du courant électronique The thickness of the AIN layer 3 can vary from In to 200 nm depending on the applications. The ohmic drain 6 and source 7 contacts are deposited on zones 8 and 9 having been doped more strongly. The different dimensions and values of the MISFET parameters will be chosen according to known techniques. In particular, they may be equal to: - the gate length Lg = 0.5 Mam - the source claw distance Lgs = 1 pim - the drain gate distance Lgd = 3.5 glm - the thickness of the channel a = 0.25 gim - the doping of the channel Nd = 3.1017 cm-3 - the development of the grid W = 1 mm This structure is very simplified, but shows the essential characteristic of the invention which is to have a channel for transporting electronic current
séparé de la grille de commande par un isolant épitaxié. separated from the control grid by an epitaxial insulator.
Les étapes permettant de fabriquer un tel composant peuvent être agencées de la manière suivante, comme le montre la figure 2: - Sur un substrat semi-isolant 2 de carbure de silicium (de type 4H par exemple) on épitaxie un canal 2 de SiC de même type dopé n, par une des méthodes connues d'épitaxie. Parmi les méthodes connues on peut citer, la sublimation sandwich (telle que pratiquée par les équipes russes de lInstitut IOFFE St Pétersbourg par exemple), la Chemical Vapour Deposition, la Molecular Phase Epitaxy, etc. Ensuite la couche d'isolant 3 est épitaxiée sur le canal SiC. On peut choisir de 'AIN. La technique d'épitaxie est de nouveau choisie parmi les techniques connues. La nature de l'isolant peut dépendre du choix et de l'orientation du polytype de SiC dans le canal. Par exemple, sur du SiC 6H orienté (0001), la couche d'AIN pourra être du 2H orienté (0001). En revanche sur du SiC 3C orienté (100), l'AIN déposé pourra être du The steps for manufacturing such a component can be arranged in the following manner, as shown in FIG. 2: - On a semi-insulating substrate 2 of silicon carbide (of the 4H type for example), a channel 2 of SiC of same n-doped type, by one of the known epitaxy methods. Among the known methods, mention may be made of sandwich sublimation (as practiced by the Russian teams of the IOFFE Institute in St Petersburg for example), the Chemical Vapor Deposition, the Molecular Phase Epitaxy, etc. Then the insulating layer 3 is epitaxied on the SiC channel. You can choose from 'AIN. The epitaxy technique is again chosen from the known techniques. The nature of the insulator may depend on the choice and orientation of the SiC polytype in the channel. For example, on oriented SiC 6H (0001), the AIN layer could be oriented 2H (0001). On the other hand, on oriented SiC 3C (100), the deposited AIN may be of
cubique orienté (100).cubic oriented (100).
- Sur la couche épitaxiée on fait une implantation localisée à l'aide d'un masquage (figure 3). Pour obtenir les zones 8, 9 de type N++, on peut implanter de rAzote. L'implantation se fait en général à haute température. On peut ensuite faire un recuit flash d'activation des porteurs à haute température (typiquement entre 1000 et 2000 C). La couche d'isolant épitaxiée étant elle-même très réfractaire, elle supporte - On the epitaxial layer, a localization is made using masking (Figure 3). To obtain zones 8, 9 of N ++ type, it is possible to implant rAzote. The implantation is generally done at high temperature. One can then make a flash annealing of activation of the carriers at high temperature (typically between 1000 and 2000 C). The epitaxial insulating layer being itself very refractory, it supports
des recuits haute température qui pourraient être problématiques avec de la silice. high temperature annealing which could be problematic with silica.
- La suite de 'élaboration du composant se fait de manière classique si ce n'est que les contacts ohmiques peuvent être recuits à très haute température ce qui - The further development of the component is done in a conventional manner except that the ohmic contacts can be annealed at very high temperature which
est favorable pour former des contacts stables en température. is favorable for forming temperature stable contacts.
2/ Circuits CMOS Dans les circuits CMOS, on fait passer un courant entre la source et le drain par l'application d'une tension sur la grille. Cette tension provoque l'inversion sous risolant de grille et accumule les porteurs à cet endroit. Les porteurs circulent donc juste à linterface et subissent toutes les diffusions dues à des défauts de l'interface. Un isolant épitaxié améle'iore grandement la transconductance de ces 2 / CMOS circuits In CMOS circuits, a current is passed between the source and the drain by applying a voltage to the grid. This tension causes the inversion under the grid riser and accumulates the carriers there. The carriers therefore circulate just at the interface and undergo all the diffusions due to faults of the interface. An epitaxial insulator greatly improves the transconductance of these
transistors.transistors.
La figure 3 montre une coupe de principe des circuits CMOS. Dans un substrat d'un type (p- dans l'exemple donné), on fait des transistors NMOS directement d'une manière similaire à celle décrite pour la réalisation du MISFET précédemment décrit. Les transistors P-MOS sont faits dans un caisson d'isolation qui aura été fabriqué localement soit par implantation soit par diffusion (la méthode de choix sera probablement l'implantation). La réalisation du transistor suit alors celle du Figure 3 shows a principle section of the CMOS circuits. In a substrate of a type (p- in the example given), NMOS transistors are made directly in a manner similar to that described for the realization of the MISFET previously described. The P-MOS transistors are made in an isolation box which will have been manufactured locally either by implantation or by diffusion (the method of choice will probably be implantation). The realization of the transistor then follows that of the
MISFET.MISFET.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9308472A FR2707425A1 (en) | 1993-07-09 | 1993-07-09 | Structure of semiconductor material, application to the production of a transistor and method of production |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9308472A FR2707425A1 (en) | 1993-07-09 | 1993-07-09 | Structure of semiconductor material, application to the production of a transistor and method of production |
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| FR2707425A1 true FR2707425A1 (en) | 1995-01-13 |
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| FR9308472A Pending FR2707425A1 (en) | 1993-07-09 | 1993-07-09 | Structure of semiconductor material, application to the production of a transistor and method of production |
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| FR (1) | FR2707425A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996019834A2 (en) * | 1994-12-22 | 1996-06-27 | Abb Research Ltd. | Semiconductor device having an insulated gate |
| WO1996032743A1 (en) * | 1995-04-10 | 1996-10-17 | Abb Research Limited | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR LAYER OF SiC COMPRISING A MASKING STEP |
| US5763905A (en) * | 1996-07-09 | 1998-06-09 | Abb Research Ltd. | Semiconductor device having a passivation layer |
| US5847414A (en) * | 1995-10-30 | 1998-12-08 | Abb Research Limited | Semiconductor device having a hetero-junction between SiC and a Group 3B-nitride |
| EP1253647A2 (en) * | 2001-04-27 | 2002-10-30 | Philips Corporate Intellectual Property GmbH | Dielectric for a semiconductor device |
| WO2005010974A1 (en) * | 2003-07-28 | 2005-02-03 | Japan Science And Technology Agency | Field effect transistor and method for manufacturing same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989004056A1 (en) * | 1987-10-26 | 1989-05-05 | North Carolina State University | Mosfet in silicon carbide |
| DE4009837A1 (en) * | 1989-03-27 | 1990-10-11 | Sharp Kk | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE |
| US5184199A (en) * | 1989-06-07 | 1993-02-02 | Sharp Kabushiki Kaisha | Silicon carbide semiconductor device |
-
1993
- 1993-07-09 FR FR9308472A patent/FR2707425A1/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989004056A1 (en) * | 1987-10-26 | 1989-05-05 | North Carolina State University | Mosfet in silicon carbide |
| DE4009837A1 (en) * | 1989-03-27 | 1990-10-11 | Sharp Kk | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE |
| US5184199A (en) * | 1989-06-07 | 1993-02-02 | Sharp Kabushiki Kaisha | Silicon carbide semiconductor device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996019834A2 (en) * | 1994-12-22 | 1996-06-27 | Abb Research Ltd. | Semiconductor device having an insulated gate |
| WO1996019834A3 (en) * | 1994-12-22 | 1996-08-22 | Abb Research Ltd | Semiconductor device having an insulated gate |
| WO1996032743A1 (en) * | 1995-04-10 | 1996-10-17 | Abb Research Limited | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR LAYER OF SiC COMPRISING A MASKING STEP |
| US5654208A (en) * | 1995-04-10 | 1997-08-05 | Abb Research Ltd. | Method for producing a semiconductor device having a semiconductor layer of SiC comprising a masking step |
| US5847414A (en) * | 1995-10-30 | 1998-12-08 | Abb Research Limited | Semiconductor device having a hetero-junction between SiC and a Group 3B-nitride |
| US5763905A (en) * | 1996-07-09 | 1998-06-09 | Abb Research Ltd. | Semiconductor device having a passivation layer |
| EP1253647A2 (en) * | 2001-04-27 | 2002-10-30 | Philips Corporate Intellectual Property GmbH | Dielectric for a semiconductor device |
| EP1253647A3 (en) * | 2001-04-27 | 2004-03-17 | Philips Intellectual Property & Standards GmbH | Dielectric for a semiconductor device |
| WO2005010974A1 (en) * | 2003-07-28 | 2005-02-03 | Japan Science And Technology Agency | Field effect transistor and method for manufacturing same |
| JPWO2005010974A1 (en) * | 2003-07-28 | 2007-11-01 | 独立行政法人科学技術振興機構 | Field effect transistor and manufacturing method thereof |
| US7622763B2 (en) | 2003-07-28 | 2009-11-24 | Japan Science And Technology Agency | Field effect transistor and method for manufacturing same |
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