FR2593621A1 - Break point apparatus for a microprocessor - Google Patents

Abstract

The present invention relates to an apparatus generating break points 30 integrated into the same chip as a microprocessor. This apparatus makes it possible to determine break points with specific reference to programme instructions or to data. The range of a break point address may be modified; the apparatus comprises a logic circuit for determining whether the reference represented by the break point address covers the current virtual address.

Description

 The present invention relates to the field of breaking points implemented by hardware for computer programs, essentially used to analyze or correct the initial faults (commonly called in the technique "bugs") of the programs.

 Many techniques are used to analyze the performance of computer programs, especially during their development. It is recognized that the process of correcting initial faults is a significant part of the development of a computer program and, in some cases, the time required to correct initial faults exceeded that required to write the program.

 A first technique used to correct the initial faults of computer programs consists in interrupting the program at predetermined events and then examining, for example, the contents of the registers. One such event is the generation of predetermined addresses which may constitute references for the computer program or data. When the address produced by the computer adapts to one of the predetermined addresses, a "breaking point" occurs. Computer operation is interrupted to allow analysis.

 One method of providing a breakpoint interrupt is to modify the computer program itself. At certain addresses in the program, the program ensures an interruption. This process is relatively inexpensive; however, it has the disadvantage that breakpoints cannot be established for addresses referenced to data.

 In another method, hardware external to the computer or microprocessor is used for breakpoint interruptions. This material compares the addresses produced by the computer to predetermined addresses and provides a breaking point or interrupt signal. This process is generally expensive and requires a significant amount of printed circuit board space. In addition, for high speed processors, it does not react quickly enough to provide a "real time" breaking point. A notable problem arises when the microprocessor includes an address translation module such as a memory management module in the microprocessor itself. The only addresses produced by the computer accessible to a user are the physical addresses typically communicated to a random access memory, i.e. virtual addresses used by the programmer may not be available. It is difficult to establish breaking points based on physical addresses.

 As will be seen, the present invention provides an apparatus for generating break points which solves the above problems and further provides for improved selection of break points.

 The present invention provides an apparatus for generating breakpoint signals useful for correcting initial faults in computer programs. The apparatus is particularly useful in an integrated circuit microprocessor formed on a single substrate which includes address generation means for producing virtual addresses to refer to program instructions or data, a virtual address bus , address translation means for converting the virtual address on the bus to a physical address, interpretation means for interpreting the instructions of the program, and arithmetic means for acting on the data according to the interpreted instructions. The apparatus includes a first register for storing a predetermined address in the form of a virtual address at which a breakpoint is to take place. A second register is used for storing command bits which allow the user to choose certain conditions of breaking point such as to choose if the breaking point should take place in relation to the program of the computer or with data. A comparator means compares the predetermined virtual address with the address produced by the computer (current virtual address). A first logic means determines whether the current virtual address refers to program instructions or data by examining the address control signals. This logic means is also controlled by the control bits stored in the second register. Gate means used to provide the break point signal and interrupt computer operation are coupled to the output of the comparator means and the first logic means. The complete apparatus is formed on the same substrate as the microprocessor.

 The apparatus also comprises a second logical means for determining whether the current virtual address is inside the reference represented by the predetermined address or whether the reference represented by the predetermined address is inside the reference domain defined by the virtual address. In fact, this allows the width of the address of the predetermined breaking point to be chosen by control bits stored in the second register.

These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of particular embodiments made in relation to the attached figures among which
Figure 1 is a block diagram illustrating the overall microarchitecture of a microprocessor in which the apparatus according to the present invention is used.

Figure 2 is a block diagram illustrating the apparatus generating break points according to the present invention
Figure 3 is an electrical diagram of a stage of one of the registers used in the block diagram of Figure 2
FIG. 4a is a diagram used to represent the case where the memory reference represented by the predetermined address (breaking point) is more extensive than a memory address reference; and
FIG. 4b is a diagram used to represent the case where the memory reference represented by the predetermined address (breaking point) is narrower than a memory address reference.

 There is described an apparatus generating break points which is particularly suitable for use in a microprocesseùr where.

the microprocessor comprises an address translation module manufactured in an integrated manner with the microprocessor. Typically, in such cases, the virtual addresses are not accessible to the user, making it difficult to establish the breaking points. In the particular embodiment described, the device generating break points is formed integrally on the same substrate as the microprocessor and its address translation module.

 In the following description, many specific details are set forth, such as particular bit numbers, etc., to allow a deep understanding of the present invention. However, it will be clear to those skilled in the art that the present invention can be implemented without these particular details. In other examples, well-known structures are not shown in detail so as not to unnecessarily obscure the present invention.

 In the particular embodiment described, the microprocessor 10 of FIG. 1 is fabricated on a single silicon substrate using a CMOS (complementary metal semiconductor oxide) technology. Any of the many well known CMOS technologies can be used; it will however be clear that the present invention can be implemented with other technologies, for example MOS technologies with -N channel, bipolar technologies, SOS technologies, etc.

 In FIG. 1, the single chip microprocessor 10 cojm * - takes a bus interface module 14, an instruction decoder module 16, an execution module 18, an address deduction module 20, and the circuit generating break points 30 f4is # t object of the present invention which is included in the module 20. The 32-bit microprocessor is shown coupled to an external random access memory 13. The bus module 14 comprises buffers 14- 1 to transmit the address at 32 bits and to receive and send the 32 bits of data. Internally to the microprocessor, the bus module includes a pre-search module 14-2 for searching instructions from memory 13 and a pre-search queue 14-3 which communicates with module # - # instruction 16 -1 of the instruction decoder. The queued instructions are interpreted and queued (16-2) in the module 16. The arithmetic and logic module (ALU) 18-1 of the execution module 18 generally executes the instructions.

 For the microarchitecture shown, the address translation module 20 provides two address translation functions; a first associated with segment description registers 20-1 and the other associated with a page description cache memory 20-2. This module is associated with the bus interface 14.

These functions are described in detail in American patent application NO 744 389 filed on June 13, 1985 and having as title
MEMORY MANAGEMENT FOR MICROPROCESSOR SYSTEM, assigned to the applicant.

The circuit generating breakpoints 30 is coupled between the segment description registers 20-1 and the page description cache memory 20-2 on a bus 19. The virtual addresses are transmitted on this bus. These virtual addresses are easily accessible for a programmer, but the physical addresses are not. It's hard to predict break points based on physical addresses, as mentioned,
A control module (not shown) is coupled to the modules in FIG. 1 to ensure control of the assembly.

 As shown in Figure 2, the circuit generating breakpoints 30 of Figure i comprises a 32-bit register / comparator 34. In the presently preferred embodiment, the register and the comparator are incorporated into a circuit unique; a stage of this register / comparator is shown in FIG. 3. The registredcornparator 34 stores the predetermined addresses at which breakpoints must occur, sometimes called hereinafter breakpoint addresses. The register / comparator 34 compares the stored breaking point address with the virtual address produced by the microprocessor, sometimes referred to hereinafter as the current virtual address or the current address. When the loading signal 35 is present, an address of 32-bit breakpoint is loaded on the bus 19a in the register / comparator 34. Then, the register / comparator 34 compares the breakpoint address with each address in progress on the bus 19 and when an agreement takes place, provides a "HIT" signal on a line 46. The two least significant bits of the breakpoint address in the register / comparator 34 are not used as elements of this comparison for reasons which will be explained below, but are instead coupled to the programmable logic network (PLA) 38.

 The instruction decoding unit 16 of FIG. 1 interprets a predetermined instruction towards the microprocessor as an order to load the register / comparator 34 and allows the user to thus load the register / comparator 34 by the point address of rupture. Another instruction allows the address stored in the register / comparator 34 to be read by the user.

 In the particular embodiment described, four registers / comparators 34 are used to allow four different breaking point addresses to be stored. For each comparator register 34, there is an associated register 32, allowing the storage of the control bits for each breaking point address as will be explained. For explanatory purposes, the circuit of Figure 2 is treated as comprising a single first register / comparator 34 and a single second register 32. However, it will be clear to those skilled in the art that any number of registers / comparators 32 and registers 34 can be used thereby allowing an interrupt for any one of a plurality of breaking point addresses.

 The control register 32 stores four control bits for each breakpoint address. A first bit determines whether the breakpoint address represents a reference to data or to the computer program. In the case of a reference to data, two control bits are used to determine the extent of the break point. In the embodiment currently described, the breaking point can have a range of 1, 2 or 4 bytes. Again, for data breakpoints, another control bit is used to allow interruption at read only or read-write cycles. As is the case with the register / comparator 34, a predetermined instruction to the microprocessor 10 is interpreted by the module 16 to allow the user to load the register 32. This can be the same instruction as that used to load the register / comparator 34.

 The validation logic circuit 36 is coupled to receive bus control signals. These lines contain the control signals which determine whether a current address refers to a program or to data; and in the case of references to data, whether it is a read-only cycle or a read-write cycle. The validation logic circuit 36 compares these control signals with two control bits from the register 32 and, if the memory cycle agrees with that chosen by the user, a validation clock is produced towards the AND gate 40. Classic logic circuits are used for this purpose.

 As mentioned, the break point can have a range of 1, 2 or 4 bytes and this range chosen by the user is stored in register 32. The two bits required for this selection are coupled to PLA 38. In furthermore, as has been mentioned, the two least significant bits stored in the register / comparator 34 are coupled to the PLA 38.

Synchronization and control signals from the lines 20 are also coupled to the PLA 38. The PLA is not user programmable but, instead, is permanently programmed upon manufacture. The PLA implements the logic established in the following paragraph. The use of a PLA is not critical for the realization of the invention, that is to say that other logic circuits can be used instead of the PLA. The PLA provides a signal to gate 40 when an "agreement" takes place.

 In FIG. 4a, a relatively large breaking point address reference is represented (for example four bytes). The current virtual memory address can be referenced to only part of the reference 70. In the case of a narrow breakpoint address reference, as shown in FIG. 4b, as reference 74, a relatively wide virtual address reference can embrace the narrower breaking point address reference 74. The two cases represented in FIGS. 4a and 4b are resolved by PLA 38.

As mentioned, conventional logic can be used to determine whether the current memory address reference falls into an extended breakpoint address reference, or whether a more breakpoint address reference narrow falls into the more extensive current memory address reference. If either of these conditions occurs, an "agree" signal is provided on line 52.

 The AND gate 40 receives three inputs, the HIT signal from the register / comparator 34, the validation clock from the logic circuit 36 and the tuning signal from the circuit 38. The HIT signal is produced when the 30 the most significant bits of the current virtual address match the 30 most significant address bits of the stored breakpoint address. The output of gate 40 provides the break point signal which is used to interrupt the operation of the microprocessor.

 The single stage shown in the register / comparator 34 shown in FIG. 3 comprises a static memory cell 53 and a comparator 54. The bus lines 19a and 13b transport a single address bit and its complement. The HIT line 46 is shown coupled to the comparator 54 and to a P-channel transistor 56.

This transistor is used to preload line 46 before each virtual address bus cycle. Line 46 is coupled to the other stages of the register / comparator 34.

 The coupled inverters form a flip-flop or conventional static memory cell 55. This cell is loaded from lines 19a and 19b when the load signal is present on line 35. Once the register is loaded, the load signal drops in potential, to effectively decouple cell 55 from lines 19a and 19b. After that, when the current virtual address appears on these lines and the + 1 signal is present, the contents of cell 55 are compared to bus address 19 by comparator 54. If any of the pairs at 32 bits which are compared do not match, line 46 is discharged preventing the AND gate 40 of FIG. 2 from being validated. The circuit of FIG. 3 is described in more detail in the aforementioned patent application where the circuit is used as part of a memory addressable by #on content.

 In use, the user determines up to four breakpoint addresses, and chooses whether the addresses are references to programs or to data, and in the case of references to data, the width of the reference and whether the breaking point must occur on a read-only cycle or on a read-write cycle. By means of a particular instruction, the user can then load up to four breakpoint addresses in the register / comparator 34 and establish the corresponding control bits for each breakpoint in the register 32. Then, using each virtual address bus cycle, a comparison takes place in the register / comparator, 34 and the logic circuits 36 and 38 determine whether the conditions chosen by the user exist. If the addresses match and the conditions match, then a breakpoint signal is produced at gate 40.

 Unlike prior art methods, a real time breakpoint signal is produced. The comparisons take place while the virtual address is present on the bus and since there is very little propagation delay, the interrupt signal can be produced at the appropriate time.

 Thus, there has been described an apparatus generating improved breaking points. This device is particularly useful for single chip microprocessors where virtual addresses are translated into physical addresses on the chip

Claims (10)

 1. Microprocessor in the form of an integrated circuit formed on a single substrate which comprises an address generation means for producing virtual addresses for referring to program instructions and data, a virtual address bus, a means for address translation (20) for converting virtual addresses on the bus into physical addresses, an interpretation means for interpreting the program instructions, and an arithmetic means for acting on the data in accordance with the interpreted instructions, characterized in that it comprises means for supplying a breaking point signal comprising  a first register (34) for storing an address at which a breaking point must take place;  a second register (32) for storing control bits  comparator means (34) for comparing at least part of the stored address with a current address on the bus, this comparator means being coupled to the first register;  first logic means (36) for determining whether the current address is a reference to program instructions or to data, the first logic means being coupled to the second register for detecting at least one of the stored control bits  gate means (40) for providing the breakpoint signal, said gate means being coupled to said comparator means and said first logic means  the first and second registers, the comparator means, the first logic means and the gate means being incorporated on the substrate,  where it follows that a real time breakpoint signal is supplied to the microprocessor.  2. Microprocessor according to claim 1, characterized in that the interpretation means interprets a certain instruction to validate the load of the first register (34) from the bus.  3. Microprocessor according to claim 2, characterized in that the interpretation means interprets a predetermined instruction to validate the load of the second register (32).  4. Microprocessor according to claim 3, characterized in that another of the control bits stored in the second register (32) determines whether a break point should take place as a result of a reference to data during a read cycle only or a read-write cycle.  5. Microprocessor according to claim 3, characterized in that some of the control bits stored in the second register (32) determine the extent of an address at which the breaking point must occur, and in that it comprises in in addition to a second logical means (38) for determining (i) whether the reference of the current address is included in the reference represented by the stored address when the reference of the current address is narrower than the stored address or, (ii) if the reference represented by the stored address is included in the reference of the current address when the current address is more extensive than the reference of the stored address.  6. Integrated circuit microprocessor formed on a single substrate which includes address generation means for producing virtual addresses for referring to program instructions and data, a virtual address bus, translation means for 'addresses (20) for converting virtual addresses on the bus into physical addresses, an interpretation means for interpreting the program instructions and an arithmetic means acting on the data according to the interpreted instructions, characterized in that it comprises means to provide a breakpoint signal comprising  a first register (34) for storing a virtual address at which a breakpoint must occur (breakpoint address)  a second register (32) for storing the control bits, at least some of the control bits determining the extent of the breakpoint address;  comparator means (34) for comparing at least part of the stored virtual address with the current virtual address on the bus, this comparator means being coupled to the first register  first logic means (38) for determining whether the current virtual address is included in the reference represented by the breakpoint address or whether the reference represented by the breakpoint address is included in the formed reference by the virtual address, this first logical means being coupled to the first and to the second registers;  gate means (40) for providing the break point signal, said gate means being coupled to the comparator means and the first logic means ;;  the first and second registers, the comparator means, the first logic means and the gate means being incorporated into the substrate;  where it follows that a real time breakpoint signal is supplied to the microprocessor.  7. Microprocessor according to claim 6, characterized in that the interpretation means interprets a certain instruction to validate the load of the first register (34) from the bus.  8. Microprocessor according to claim 7, characterized in that the interpretation means interprets a predetermined instruction to validate the load of the second register (32)  9. Microprocessor according to claim 8, comprising a second logic means (36) for determining whether the current virtual address is a reference to a program or to data, this second logic means being coupled to the second register (32) for detecting at least one of the stored control bits, this second logic means providing an output to the door means (40).  10. Microprocessor according to claim 9, characterized in that another of the control bits stored in the second register determines whether a breakpoint must occur by referring to data during a read-only cycle or a read cycle -writing