FR2569323B1 - Dispositif d'adaptation plesiochrone - Google Patents
Dispositif d'adaptation plesiochroneInfo
- Publication number
- FR2569323B1 FR2569323B1 FR858512508A FR8512508A FR2569323B1 FR 2569323 B1 FR2569323 B1 FR 2569323B1 FR 858512508 A FR858512508 A FR 858512508A FR 8512508 A FR8512508 A FR 8512508A FR 2569323 B1 FR2569323 B1 FR 2569323B1
- Authority
- FR
- France
- Prior art keywords
- plesiochronous
- adaptation device
- adaptation
- plesiochronous adaptation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
- H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59172031A JPS6150435A (ja) | 1984-08-18 | 1984-08-18 | プレジオクロナス整合装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2569323A1 FR2569323A1 (fr) | 1986-02-21 |
FR2569323B1 true FR2569323B1 (fr) | 1989-05-05 |
Family
ID=15934244
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR858512508A Expired FR2569323B1 (fr) | 1984-08-18 | 1985-08-19 | Dispositif d'adaptation plesiochrone |
Country Status (3)
Country | Link |
---|---|
US (1) | US4821227A (fr) |
JP (1) | JPS6150435A (fr) |
FR (1) | FR2569323B1 (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2600474B1 (fr) * | 1986-06-18 | 1988-08-26 | Alcatel Thomson Faisceaux | Procede de synchronisation de deux trains binaires |
US4922438A (en) * | 1986-12-11 | 1990-05-01 | Siemens Aktiengesellschaft | Method and apparatus for reading packet-oriented data signals into and out of a buffer |
JP2875287B2 (ja) * | 1989-07-19 | 1999-03-31 | 株式会社日立製作所 | フレームアライナおよびその制御方法 |
JP2806657B2 (ja) * | 1991-09-26 | 1998-09-30 | 日本電気株式会社 | プレジオクロナス/ドップラーバッファとプレジオクロナス同期/ドップラー効果抑圧方法 |
US5617088A (en) | 1994-01-26 | 1997-04-01 | Sony Corporation | Sampling frequency converting device and memory address control device |
US5872823A (en) * | 1997-04-02 | 1999-02-16 | Sutton; Todd R. | Reliable switching between data sources in a synchronous communication system |
US6389553B1 (en) * | 1998-05-26 | 2002-05-14 | Nortel Networks Limited | Redundant link delay maintenance circuit and method |
CN1299464C (zh) * | 2003-06-04 | 2007-02-07 | 中兴通讯股份有限公司 | 在同步系统中实现时钟主备用的方法和装置 |
JP4852963B2 (ja) * | 2005-10-14 | 2012-01-11 | 株式会社日立製作所 | 伝送装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3909795A (en) * | 1973-08-31 | 1975-09-30 | Gte Automatic Electric Lab Inc | Program timing circuitry for central data processor of digital communications system |
FR2320023A1 (fr) * | 1975-07-28 | 1977-02-25 | Constr Telephoniques | Procede et dispositif de resynchronisation d'informations entrantes structurees en trames |
US4358823A (en) * | 1977-03-25 | 1982-11-09 | Trw, Inc. | Double redundant processor |
GB2066627B (en) * | 1979-12-13 | 1983-12-07 | Plessey Co Ltd | Pcm frame aligner with frame slip characteristic |
US4387394A (en) * | 1980-12-31 | 1983-06-07 | Rca Corporation | Sensing focus of a color kinescope |
US4429386A (en) * | 1981-01-05 | 1984-01-31 | Siemens Corporation | Buffer arrangement of a PCM exchange system |
-
1984
- 1984-08-18 JP JP59172031A patent/JPS6150435A/ja active Granted
-
1985
- 1985-08-19 US US06/767,192 patent/US4821227A/en not_active Expired - Fee Related
- 1985-08-19 FR FR858512508A patent/FR2569323B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4821227A (en) | 1989-04-11 |
JPH0213499B2 (fr) | 1990-04-04 |
JPS6150435A (ja) | 1986-03-12 |
FR2569323A1 (fr) | 1986-02-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
D6 | Patent endorsed licences of rights | ||
D6 | Patent endorsed licences of rights | ||
ST | Notification of lapse |