FR2541545A1 - DIGITAL AUTOMATIC TUNING APPARATUS OPERATING DURING VERTICAL SCAN RETURN - Google Patents

Abstract

THE INVENTION RELATES TO A DIGITAL AUTOMATIC TUNING APPARATUS OPERATING DURING THE VERTICAL SCAN RETURN. THE APPARATUS INCLUDES A COUNTER 30 WHICH ALTERNATIVELY MEASURES THE LOCAL OSCILLATOR FREQUENCY AND THE INTERMEDIATE FREQUENCY OF THE IMAGE CARRIER. DEPENDING ON THE METERING OBTAINED, SIGNALS ARE GENERATED TO CONTROL A PRECISE AUTOMATIC TUNING CIRCUIT. APPLICATION TO TELEVISION RECEIVERS.

Description

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  The present invention relates to the field of precise automatic tuning digital apparatuses in which a counter is used to measure the frequency of a carrier supporting information of an intermediate frequency signal to develop a tuning control signal which is applied to a local oscillator to correct frequency deviations of the information carrier. Such a precise automatic tuning digital apparatus is desirable because it eliminates expensive discrete circuits, including tuned circuits that must be precisely aligned, associated with each other.

  with a precise automatic tuning device of the analog type

  logic commonly used in television receivers.

  A precise automatic digital tuning apparatus is also desirable because it enables a substantial part of the tuner control apparatus of a receiver to be integrated into digital signal processing integrated circuits for others. parts of

receiver.

  A problem posed by such a digital apparatus

  precise automatic agreement is that if the carrier of information

  the received high frequency signal is over-modulated,

  the corresponding carrier of the intermediate frequency signal

  It can also be over-modulated and may be too small for a counter used to measure its frequency to react safely. This can cause troublesome interruptions in the tuning process which, for example in a television receiver, can cause

  corresponding disturbances of the image and sound.

  According to the invention, a digital apparatus

  automatic tuning for a television receiver

  vision makes it possible to measure the frequency of an information carrier of the intermediate frequency signal during scan return intervals, such as during a portion of the vertical scan return interval in which the image carrier has not trend

  to be over-modulated, and therefore, has an

  suitable for frequency measurement.

  In another provision, only one

  positive counting is used selectively for S to measure the frequencies of the local oscillator signal

  of the intermediate frequency signal during the inter-

  respective valle Specifically, before a first measurement interval during which the frequency of the local oscillator signal is to be measured, a number related to the desired frequency of the local oscillator signal is loaded into the counting device and, before a second measurement interval during which the frequency is to be measured, a number related to the desired frequency of the intermediate frequency signal is loaded into the same counting device During each measurement interval, the respective one of the local oscillator signal

  or the intermediate frequency signal is coupled with-

  the counting device so that the latter can

  count in response to this signal from the initial number

  At the end of each measurement interval, regardless of the signal that has been measured, the count of the counting device is compared with the same predetermined count to produce signals representing frequency deviations if there is a signal measured by relative to the respective desired frequency. Preferably, when the invention is used in a television receiver, the counting device is controlled in response to the deflection timing pulses so that the frequency of the local oscillator signal is measured repetitively except in a portion of the time interval. scan return in which the frequency of the image carrier of the intermediate frequency signal is measured Since the image carrier does not tend to be over-modulated during the scan return intervals, as can be done during the image intervals between the return intervals, this ensures that the frequency carrier measurement of the intermediate frequency signal

can be relatively safe.

  Other features and advantages of the invention will be better understood when reading the

  description which follows of an example of realization and

  with reference to the accompanying drawings in which: Figure 1 is a schematic representation of a tuning device in which the invention can be used with advantage;

  Figures 2,3,4,5 and 6 are representative

  schematic representations in logical form of

  of one embodiment of the invention,

  Figures 4a, 5a and 6a are representative

  graphical representations of different waveforms

  signals that provide a better understanding of how

  2, 3, 4, 5 and 6, FIGS. 7a and 7b are diagrammatic diagrams of a particular embodiment of structural parts diagrammatically shown in FIG. 2, FIGS. schemas in logical form of respective parts of the structure of Figure 1, and Figure 9a is a graphical representation of signal waveforms for understanding the

  operation of the structure of Figure 9.

  In the figures, the lines between boxes with transverse markings indicate circuits

multiples of signals.

  According to FIG. 1, a source 1 of high frequency signals delivers several television signals

  radio frequency to a television receiver, corresponding to

  Each high frequency signal contains modulated carriers of images, colors and sounds. The high frequency signals provided by the source 1 are applied to a high frequency amplifier 3 which is tuned according to an

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  tuning voltage (TV) for selecting one of the high frequency signals corresponding to a user-selected channel The selected high frequency signal is applied to a mixer 5 This latter also receives a local oscillator signal produced by by a local oscillator 7 This also reacts to the attention

  okay to control the frequency of the oscil-

  The mixer mixes the high frequency signal operated by the amplifier 3 with the local oscillator signal produced by the oscillator 7 to produce an intermediate frequency signal containing modulated carriers. images, colors and sounds corresponding to those of the selected high-frequency signal In the United States of America,

  the image carrier has a nominal frequency of 45.75 M Hz.

  The color carrier has a nominal frequency of 42.17 MHz. The sound carrier has a nominal frequency of

41.25 M Hz.

  The high frequency amplifier 3 and the local oscillator 7 each comprise circuits

  granted to determine their frequency response.

  Each tuned circuit has an inductance coil

  and a voltage controlled variable capacitance diode.

  The variable capacitance diode is biased in opposition by the tuning voltage to present a capacitive reactance. The amplitude of the tuning voltage determines the capacitance of the capacitive reactance and therefore the frequency response of the tuned circuit. only one variable capacity diode tuned circuit pattern can be tuned throughout the television range, several different configurations are allowed successively in response to band selection control signals produced according to

  of the frequency band of the chosen channels.

  The intermediate frequency signal produced by the mixer 5 is applied to the intermediate frequency filter 9 which filters the received intermediate frequency signal. This filtered signal is amplified by an intermediate frequency amplifier 11 and applied to an image detector 13. the filtered and amplified intermediate frequency signal for producing a baseband video signal representing the luminance, chroma and timing information The baseband video signal is applied to an image processing unit and a separator synchronization signal 17 The intermediate frequency signal is also applied

  a sound processing unit 19 which extracts the information

  of the intermediate frequency signal to produce the audible signal. The latter is amplified by

  the sound processing unit 19 and applied to a built-in

speaker 21.

  The image processing unit 15 separates the baseband video signal into signals representing the lunimence and chroma information and processes its separated signals to produce the R, G and B signals respectively representing the red information, green and blue signals R, B and G are applied to the respective electron guns of an image tube 23 which, in response to these signals, produces beams

respective electrons.

  Synchronization separator 17 extracted

  video signal in baseband a synchronization signal

  The composite synchronization signal is applied to a deflection unit 25 which produces the horizontal and vertical deflection signals.

  deviation signals are applied to the deviation coils.

  27 associated with the image tube 23 to deflect the electron beams produced by the barrels of the image tube 23 in the form of the usual weft More specifically, the horizontal and vertical deflection signals cause the beams of electrons produced by the guns of the tube 23 scan horizontally the screen in successive lines After each horizontal line, the electron beams are brought back to the beginning of the next scan line At the end of a complete frame of scan lines ( 525 in the United States of America), the electron beams are brought to the top of the next frame during an interval of

vertical scan back.

  A blocking unit 29 responds to the horizontal and vertical deflection signals produced in the deflection unit 25 producing horizontal and vertical blocking pulses during the horizontal and vertical return intervals respectively. The blocking pulses are applied to the unit of rotation. image processing to inhibit the production of a

  image during the return intervals.

  The part of the television receiver

  Fig. 1 described above is current and does not need to be described in detail. The remainder of the television receiver shown in Fig. 1 includes a tuning control device for producing the tuning voltage and the signals. of band change for the high frequency amplifier 3 and the oscillator

local 7.

  For the most part, the control device

  tuning has two frequency lock loops.

  When a new channel is selected, the operation of the first loop is allowed The first loop measures the frequency of the local oscillator (LO) signal and produces control signals of the amplitude of the tuning voltage up to that the frequency of the signal LO is within a certain range of the nominal value of the selected channel When the first loop has finished operating, the operation of the second loop is allowed The second loop measures the frequency of the image carrier of the signal intermediate frequency and produces control signals of the tuning voltage amplitude until the frequency of the image carrier is within a predetermined range of its nominal value. The first frequency locked loop synthesizes the local oscillator rated frequency for the selected channel This nominal frequency LO is the frequency needed to tune the signal to

  high frequency broadcast associated with the respective channel.

  In the United States of America, broadcast high-frequency signals must adhere to very specific standard frequencies imposed by the administration. The second frequency-locked loop allows for precise automatic tuning of the receiver on high-frequency signals that are shifted in a frequency-dependent manner. Frequency vs. High Frequency Broadcast Signals These non-standard high frequency carriers may be produced by cable-by pilot antenna television systems, video tapes

  or disc players, video games or computer

  individual sources that can constitute the source 1

at high frequency.

  According to one aspect of the invention, the two frequency-locked loops share a common frequency sampler 30 which selectively measures the measurement of the LO signal in the operation synthesis mode and measures the frequency of the signal carrier of the signal. intermediate frequency

  during the precise automatic tuning mode.

  The frequency selector 30 is selectively enabled to measure the frequency of the LO signal in response to the logic level O of a synthesis authorization control signal, and it is allowed to measure the frequency of the intermediate frequency signal in response to a signal. The synthesis authorization signal and the automatic tuning authorization signal are produced by a tuning control unit 45 in a manner which will be

described below.

  The local oscillator signal is applied to a first frequency divider 3 which divides the frequency of this signal to produce a split frequency version which is applied to the frequency sampler 30 The intermediate frequency signal is applied to a second divider of frequency 65 which divides the frequency of the intermediate frequency signal by a second division factor to produce a divided frequency version of the frequency signal

  intermediate which is also applied to the sample

  Since the dominant carrier in the intermediate frequency signal is the image carrier, a frequency divider 65 is responsive to the image carrier rather than to other carriers.

  in the intermediate frequency signal Therefore, -

  the user output signal 65 is in fact a split frequency version of the intermediate frequency signal carrier. The first factor and the second factor of the frequency divisors 33 and 65 are selected so that The split signals produced by the frequency sampler 30 are within the operating frequency range of this sampler. Suitable division factors for the United States of America are two hundred and fifty six and eight as indicated at By way of example, with these dividing factors, the frequency divider 33 produces one pulse for one hundred and fifty six cycles of the local oscillator signal and the divider 65 produces one pulse for eight cycles of

  the image carrier of the intermediate frequency signal

  diary. Since the image carrier of the received high frequency signal can be overmodulated, the imager carrier of the intermediate frequency signal can be low enough so that the divider 65 and hence the frequency sampler 30 can not be used. respond to it safely For a safe measure of frequency

  of the image carrier of the international frequency signal

  medium can be obtained by the frequency sampler 30, the latter is selectively authorized to

  measure the frequency of the intermediate frequency signal

  in the fine tuning mode, during only a portion of the vertical scan return interval in which the image carrier does not tend to be over-modulated and therefore has a relatively high amplitude suitable for a measurement

  For this purpose, the synchronization signal

  The composite produced by the separator 17 is applied to a vertical pulse detector 71. At the beginning

  of the vertical return interval, the pulse detector

  verticals 71 produces a vertical impulse

  is applied to the bone frequency sampler 30

  local oscillator The vertical pulse triggers the carrier frequency measurement of the intermediate frequency signal during a predetermined portion of the vertical return interval as shown in FIG.

figure 5 a.

  In FIG. 5a, a waveform A illustrates a baseband video signal with a particular focus on the vertical return interval. It should be noted that in the image interval, the amplitude of the video signal between successive horizontal synchronization pulses (separated by horizontal scanning intervals H) can be very low depending on the

  modulation of the image carrier But in the inter-

  vertical return range, the video signal amplitude is relatively high As shown in waveform B, the vertical pulse is produced just after the end of the first vertical sync pulse in the vertical scan return interval As indicated by the waveform E, the local oscillator frequency measurement interval begins a little after the generation of the vertical pulse and ends just before the portion of the vertical return interval reserved for teletext information and signals

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  This is desirable because the image carrier can be overmodulated by teletext and

  test, as indicated by dotted lines in the inter-

  Teletext signal and test waveband A. As will be described in more detail with reference to FIGS. 2 and 3, the frequency sampler includes a counting device which is selectively allowed to count pulses. either the frequency-divided version of the local oscillator signal or the frequency-divided version of the frequency signal

  intermediate during respective measurement intervals.

  The measurement intervals are established by timing signals applied to the frequency sampler 30 by a reference counter 35.

  produces the timing signals by dividing successively

  For example, as shown in FIG. 1, the crystal oscillator 37 is arranged to produce a reference frequency signal of 4. M Hz The lowest frequency delay signal produced by the reference counter 35 has a frequency of 488.3 Hz (4 Mhz: 213) or a period of 2048 microseconds and is designated R Other timing signals used in the structures of the figures are designated 2 R, 4 R, -64 R and 256 R, the coefficient of R indicating the inverse relationship of the period of the particular timing signal, with the period of R For example, 2 R a a period of 1024 microseconds, 4 R a period of 512 microseconds, 64 R a period of 32 microseconds and 256 R a period of

8 microseconds.

  Just before the measurement intervals, the counting device is prepared under predetermined and respective conditions corresponding to the numbers

  related to the nominal frequencies of the signals to be measured.

  Although the nominal frequency of the intermediate frequency image carrier is the same for each channel, the nominal frequency of the local oscillator signal differs with each channel Therefore, binary signals representing the channel number and the frequency band of the channel selected are applied to the sampler by a channel number register 41 and a band decoder 50 respectively to determine the conditions under which the counting device is placed just before the oscillator frequency measurement interval.

local.

  During the measurement intervals, the content of the counting device is decremented in response to the pulses of the divided frequency version of the measured signal Just after the end of the measurement, the

  The content of the counting device shall be examined to determine

  the frequency error if there is a measured signal.

  If the counter reaches a zero count during the measurement interval, it starts again at the beginning so that a high count is produced at the end of the measurement interval. If the frequency of the measured signal is low, the count is low and a corresponding low count error pulse is generated If the frequency of the measured signal is high, the count is high and an error pulse of

high count is produced.

  The high count and low count pulses are applied to the counting and down counting inputs of a down counter. In response to high counting error pulses, the contents of the up / down counter 55 are decremented. In response to low counting error pulses, the contents of the counter-counter 55 are incremented.

  counter 55 is applied to a binary multiplier 57.

  The latter receives the reference frequency signal at

  4 M Hz from the crystal oscillator 37 The multi-

  Binary encoder 57 produces a pulsed signal containing in a given interval a number of pulses depending on the contents of the countdown counter 55. The pulsed signal produced by the multiplier 57 is applied to a hashing filter 59 which filters the received pulsed signals so that to produce a continuous signal The continuous signal is applied to an amplifier 61 which amplifies it for

produce the tuning voltage.

  The channels are selected by means of a channel selector 43 which may for example consist of a computer type keyboard by which a two-digit number corresponding to the chosen channel can be entered in the channel number register 41.

  binary signals representing the selected channel number

  The tape decoder 50 is transmitted to a tape decoder 50 as well as to the frequency sampler 30. The tape decoder 50 produces binary signals representing the band of the selected channel, which signals are applied to the amplifier. For example, for receivers used in the United States of America, the band decoder produces a high level VLL signal for VHF channels. 2, 3 and 4, a high level signal VH for the VHF channels 5 and 6, a high level signal VH for the VHF channels 7 to 13 and a high level signal U for the

HF channels 14 to 83.

  When a new channel is selected, the selector 43 produces a high level new channel signal that is applied to a control unit. In response, the unit 45 passes the authorization signal.

  The result is that the exchange of

  Frequency Tiller 30 measures the frequency of the LO local oscillator signal in response to the high count and low count error pulses produced by

  the frequency sampler 30, the content of the counter-

  Down counter 55 and therefore the amplitude of the tuning voltage are set until the frequency of the signal LO is within a predetermined range of its nominal frequency. At this time, the tuning control unit 45 passes the summary authorization signal at the

  low level and raise the signal to high

  The result is that the frequency sampler 30 is allowed to measure the frequency of the intermediate frequency signal. But this frequency is actually measured only when the vertical pulse is produced by the vertical pulse detector 71 during the vertical return interval. The high count and low count error pulses produced as a function of the measurement of the vertical pulse. frequency of the intermediate frequency signal are applied to the up-down counter 55 to determine its content and hence the tuning voltage amplitude to control the frequency of the LO signal until the frequency of the image carrier is located in a

  predetermined range of its nominal value.

  During operation in fine tuning mode, when the automatic tuning signal is high, except during the control of the frequency carrier measurement of the intermediate frequency signal in the range of vertical return, the frequency sampler 30 measures the frequency of the local oscillator signal. This is so to determine if the frequency of the signal LO has changed with respect to the value established during the preceding synthesis mode of a predetermined offset, for example 1.25 M Hz If the predetermined offset of the frequency of the local oscillator signal is detected, the frequency sampler 30 produces an offset pulse which is applied to the tuning control unit 45 In response, the latter interrupts the high level of the precise automatic tuning authorization control signal and again produces the synthesis authorization control signal at the high level. This triggers the mode again

of synthesis.

  To quickly synthesize the local oscillator nominal frequency in the selected channel,

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  as will be described hereinafter in more detail with respect to FIG. 8 which shows a logical realization of the up-down counter 55, the binary multiplier 57 and the low-pass filter 59 during the synthesis mode, lower order groups of the down-counter are successively allowed to respond to the high count and low count error pulses in response to coarse tuning, and medium tuning and fine tuning signals generated by the control unit

  agree 45 The control unit 45 sequential product-

  These control signals detect whether the direction of the error pulses produced by the frequency sampler 30 changes during operation in the synthesis mode. It should also be noted that the clear and fine tuning authorization control signals are applied to the low-pass filter 59 by the tuning control unit 45. The function of this is to change the time constant. of the filter 59 in the different operating modes More particularly

  in the synthesis mode when the elimination of

  pulsed signals of the continuous signal applied to the ampli

  61 is not critical, the bandwidth of the filter

  59 is relatively wide in response to the self-signal

  However, in the automatic tuning mode, in which the final tuning voltage is produced and in which pulsed components appearing could produce visible interference to the reproduced image, the bandwidth of the filter 59 is made relatively small in response to

  precise agreement authorization signal at high level.

  With regard to now the realization of a frequency sampler portion 30 shown

  in FIG. 2, the counting device mentioned above

  above includes a main down counter 201 and a

auxiliary down counter 203.

  A multiplexer or main switch

  selectively transmits BCD (decimal-coded)

  binary) representing the selected channel number, BCD signals representing the band of the selected channel (eg 49 for the VHF lower channels 2-4, 93 for the VHF lower channels 5-6, 179 for the VHF upper channels 7-13 and 433 for UHF channels 14-83 in the United States of America) or BCD signals representing a number related to the number of cycles of the frequency-divided version of the intermediate frequency signal carrier appearing in the frequency interval of this signal (for example 366 in the United States of America) to the JAM inputs of the main down counter 201 in response to a respective one of the high level channel selection signal n, the selection signal band

  high level and the international frequency selection signal

  Since the highest numbers represented by the BCD signals applied to the JAM inputs of the main down counter 201 are a three-digit number as shown in FIG. 2, the counter 201 is a three-digit decimal counter. this has been indicated with regard to FIG. 1, the BCD signals representing the channel number are stored in a channel register 41 The BCD signals representing the band number are produced by a logic matrix designated after 207 in response to the selection signals Bandwidth produced by the band decoder 50 BCD signals representing the number linked to the intermediate frequency frame carrier frequency, indicated as the main intermediate frequency number are produced by

  a logical matrix designated 209.

  A zero count detector delivers a high level signal "= O" when the count of the down counter 201 is equal to zero A "> 5" detector 213 delivers a high level signal "> 5" when the count of the down counter 201 is greater A detector 215 of '<max 4' produces a high level signal '<max 4' when the contents of the down counter 201 are lower than the count

maximum decreased by 4.

  FIG. 7a represents a logical embodiment of the main counter 201, the main multiplexer 205, the logic matrices 207 and 209 and the

detectors 211, 213 and 215.

  An auxiliary multiplexer 217 selectively transmits binary signals representing, in actually binary code, a first number identified as the synthesis and shift number (e.g. 28) used in conjunction with the measurement of the LO frequency in the synthesis mode to produce error pulses and also in the automatic tuning mode for frequency offset detection LO, or signals representing, also a direct binary code, a second number called auxiliary IF number, for example 4, used together with the measurement of the intermediate frequency image carrier frequency in the automatic tuning mode, to the JAM inputs of the auxiliary down counter 203 in response to a control signal designated by "IF cycle" The control signal "IF cycle" is at the high, except during part of the vertical return interval (see waveform of Figure Sa) in which the intermediate frequency is measured at this time

  the control signal "If cycle" being low.

  When the "IF cycle" control signal is high, the auxiliary multiplexer 217 transmits the binary signals representing the number of syntheses and offsets to the JAM inputs of the auxiliary down counter 203 When the "IF cycle" command signal is at the logic level bottom, the auxiliary multiplexer 237 transmits the binary signals representing the auxiliary input IF number 212 of the auxiliary down counter 203 The binary signals representing the number of syntheses and offsets are generated by a logic matrix 219 The binary signals representing the IF number Auxiliary is produced by a logic array 221 Since the highest number represented by the binary signals applied to the auxiliary down counter 203 in the embodiment of Figure 2 is 28, the auxiliary counter 203 is a step down as indicated. A detector "1" 223 delivers a signal of

  level "= 1" when counting the counter

  Maire 203 is equal to unity An inverter 225 inverts this signal to produce a signal "T 1" A detector "4" 227 produces a high level signal "= 4" when the count

the auxiliary counter 203 is = 4.

  FIG. 7b is a logical representation of the auxiliary counter 203, the multiplexer 217, the logic matrices 219 and 221 and the detectors 223 and 227. Before describing the remainder of the structure of FIG.

  Figure 2 and that of Figure 3, a description

  their operation is useful.

  As already indicated, in each frequency measurement, the counting device of the frequency sampler 30 is essentially allowed to count down from a predetermined number in response to pulses of a divided frequency version of the signal. Measured during the measuring interval The predetermined number is loaded into the mounting device just before the measurement interval. After the end of the measuring interval, the contents of the counting device are examined to determine the error of the measuring device.

frequency if it exists.

  In particular, by referring to the structure

  In FIG. 2, the predetermined number is set by loading the binary signals supplied to the JAM inputs of the main down counter 201 by the main multiplexer 205 in the down-counter 2:01 and loading the binary signals supplied to the JAM inputs of the auxiliary down counter 203 from the multiplexer 217 in the down-counter 203 in response to positive authorization signals applied to the respective preparation inputs PR of the counters 201 and 203. Binary signals applied to the JAM inputs of the counters 201 and 203 at this time differ according to the frequency of the signal. local oscillator

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  the frequency of the intermediate frequency signal is measured. Then, in response to the high level of a counter authorization signal, the divided frequency version of the signal to be measured is applied by a gate circuit to the clock input. As long as the count enable signal is high, the contents of the main down counter 201 are decremented by one unit in response to each pulse of the divided frequency of the measured signal. The duration of the signal level O counting authorization depends on the measured signal Whenever the contents of counter 201 are

  equal to zero, until the counting of the up-down timer

  203 reaches the unit, the contents of the counter

  auxiliary 203 is reduced by one unit and a signal from

  The main counter is generated by the application of the binary signals to the JAMs of the main counter 201. The binary signals applied to the JAM inputs of the main counter 201 by the multiplexer 205 at this time differ depending on whether the frequency of the signal LO is measured or the frequency of the intermediate frequency signal is measured and the frequency of the signal LO is then measured on the specific counter of the auxiliary counter 203 At the end of the measurement interval, when the high level of the pulse of authorization of counter disappears, the divided frequency version of the measured signal is decoupled from the clock input of the main counter 201. Then, in response to a sampling pulse, the contents of the main counter 201 are examined by the structure shown in FIG. 3 Depending on the contents of the main counter 201 and according to the frequency of the signal LO or the frequency of the frequency signal e is measured, the structure of Figure 3 produces a high count or counting error pulse or a pulse of

offset.

  If the frequency of the local oscillator signal is at its nominal value for the selected channel, with a division factor of 256 for example as shown in Figure 1, the number of cycles of the divided frequency version of the LO signal appearing in an inter

  measuring range having a duration for example of 1024-

  microseconds, is equal to 4 times the frequency in M Hz of

the nominal LO frequency.

  The counting device of FIG. 2, comprising the main counter 201 and the auxiliary counter 203 takes advantage of the fact that the channels of each band of the television range are uniformly separated into a frequency band for measuring the frequency of the LO signal by allowing the counting device to be counted from a prepared number equal to four times the nominal LO frequency in M Hz, without the need for a relatively large permanent memory for

  memorize the frequency of each particular channel

  the local oscillator frequency, f LO for each channel, can be expressed by the following equation BLO = (channel number) (frequency separation) + band-dependent constant (1) Therefore, with a factor for example, the preset number of each channel can be expressed by the following equation: (prepared number) = <4) <channel number) (separation of the local oscillator of 256 and a measurement interval of 1024 microseconds for example). frequency) + band-dependent constant (2) For example, local oscillator signal frequency ratings for channels broadcast in the United States of America according to equation (2) are indicated in FIG. table below Band N Band constant f Lo (M Hz)

VHFLL 2 89 101 = (2) (6) + 89

4 89 113 = (4) (6) + 89

VHFL 5 93 123 = (5) (6) + 93

6 93 129 = (6) (6) + 93

VHFH 7 179 221 = (7) (6) + 179

13 179 257 = (13) (6) + 179

UHF 14 433 517 = (14) (6) + 433

83,433,931 = (83) (6) + 433

  With the values shown in the table above, equation (2) becomes: Prepared number = (24) (channel number) + (4) (band constant) (3)

  With equation (3) in memory, the function

  the structure of Figure 2 to measure

  the sequence of the local oscillator signal will be explained.

  Just before the oscil-

  In the local spreader, the binary signals representing the channel number produced by the channel number register 41 are loaded in the main down counter 201 and binary signals representing 28 (i.e. 24 + 4) produced by the logic matrix 219. are loaded into the auxiliary down counter 203 During the frequency measurement interval LO, the frequency divided version of this signal is applied to the clock input of the main down counter 201 In response to each pulse of the version

  divided into the frequency of the LO signal, the counting of the

  201 is reduced by one unit during the inter-

  until the count of the auxiliary counter 203 reaches the unit, when the count of the main down counter 201 reaches zero, the counter of the auxiliary counter 203 is reduced. In addition, until the count in the counter is reached. 203 auxiliary counter reaches 4, each time the count in the down-counter

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  the principal 201 reaches zero, the binary signals

  with the channel number are again loaded in the main down counter 201 When the countdown of the auxiliary down counter reaches four, the binary signals representing the band-dependent constant produced

  by the logic matrix 207, are loaded into the decompo-

  Then, the count of the auxiliary down counter 203 continues to decrease by one unit each time the count of the up-down counter 201 reaches zero until the counter of the auxiliary counter 203 reaches the unit If the oscillator frequency local is at its nominal value, the measurement interval ends, the countdown of the main down counter 201 has just reached zero during the interval in which the count of the auxiliary counter 203 is the unit according to the equation

(3) above.

  Depending on the actual local oscillator frequency, at the end of the measurement interval, the structure shown in Fig. 3 produces a low count or high count error pulse during the synthesis mode and a pulse of offset during the mode

automatic tuning.

  The main down counter 201 and the auxiliary counter d 203 are also used to measure the frequency of the image carrier of the frequency signal.

  intermediate When the frequency of the image carrier-

  is at its nominal value, 45.75 M Hz in the United States of America, with a division factor of the intermediate frequency divider equal to eight, as shown by way of example in Figure 1, the number of cycles of the frequency-divided version of the intermediate frequency signal appearing in a measurement interval

  for example, 256 microseconds is 1464 or (4) (366).

  By keeping in memory the count of 1464 which corresponds to the nominal frequency of the intermediate frequency image carrier, the operation of the structure of FIG. 2 for measuring the frequency of the intermediate frequency image carrier will now be described. Just before the intermediate frequency measurement interval, binary signals produced by the logic matrix 209 representing the number 366 are loaded into the main down counter 201 and binary signals produced by the logic matrix 221 representing the number four are loaded into the down-counter During the intermediate frequency measurement interval, in response to each frequency-divided version pulse of this signal, the count of the up-down timer 201 is reduced by one.

  unit Until the timer countdown

  203 reaches the unit, each time the count of the main down counter 201 reaches zero, the count of the auxiliary down counter 203 is reduced by one and the binary signals produced by the logic matrix 209 representing the number 366 are loaded again into the main down counter 201 During the interval in which the count of the auxiliary down counter 203 is the unit, if the frequency of the image carrier of the intermediate frequency signal is at its nominal value, the count of the main down counter 201 reaches just zero when the intermediate frequency measurement interval ends According to the actual frequency of the intermediate frequency image carrier,

  At the end of the measurement interval, the structure

  shown in Figure 3 produces an error pulse

  high counting or low counting.

  The structure shown in FIG. 4, which will be described below, produces pulse signals

  local oscillator counter preparation, auto-

  oscillator counter sampling, local oscillator counter sampling, shown in FIG. 4a for controlling counters 201 and 203 for

  measure the frequency of the local oscillator signal.

  Under the effect of the local oscillator counter preparation pulses, the counters 201 and 203 are loaded with the appropriate binary signals just before the

  local oscillator frequency measurement intervals.

  The logic high level of the local oscillator counter enable pulses allows the frequency divided version of the LO signal to be applied to the clock input (C) of the main down counter 201 to thereby determine the duration of the interval. The local oscillator counter sampling pulses appear immediately after the end of the local oscillator frequency measurement intervals and cause the structure of Figure 3 to evaluate the count in the main down counter. 201 to produce the error pulses Local oscillator counter preparation, authorization, and sampling pulses * are continuously generated by the device of FIG. 4 in response to the timing signals 4 R, 2 R, and R produced by the reference counter 35 of the

figure 1 -

  The structure of Figure 5 which will be described

* below produces the impulses of preparation, authorization

  An intermediate frequency counter sampling and sampling, shown in Figure 5a, and having functions similar to those of the local oscillator counter pulses to control the counters 201 and 203 to measure the carrier frequency

  In addition, the structure of

  Figure 5 also produces "IF cycle" impulses (G waveform) shown in Figure 5a,

  which encompass the impulses of preparation, authorization

  These pulses are produced in response to the timing signal 64 R also produced by the reference counter. In contrast to the local oscillator counter pulses, the intermediate frequency counter pulses are not generated. continuously generated but are selectively allowed to be produced in response to the vertical pulses (waveform B) only during part of the vertical return interval, i.e. starting after the first vertical synchronization pulse. hold and ending just before the interval of

  teletext and test signals (waveforms A and G).

  This ensures that an over-modulation of the intermediate frequency image carrier does not impair the ability of the main down counter 201 to count pulses of the split frequency version of the intermediate frequency signal. The "IF cycle" pulse waveform G) is used to prevent the devices of FIGS. 2 and 3 from responding to oscillator counter pulses

  local during intermediate frequency measurement.

  Referring now specifically to the structure of Fig. 2, the local oscillator counter preparation signal is applied to the S-RFF forcing input S9 and an input of OR gate 231 The output of the OR gate 231 is applied to the quiescent input R of a flip-flop SR FF 233 The channel number selection signal produced at the output Q of the flip-flop 229 and the signal The signal "1 = 41 generated by the detector 227 is applied to an input of an OR gate 235. The output of the OR gate 235 is outputted to the output Q of the bistable circuit 231. quiescent input R of the bistable circuit 231 The "IF cycle" signal is applied to the

  second entry of OR gates 231 and 235.

  The "IF cycle" signal is at the low level except during the frequency measurement of the intermediate frequency cycle in which it is at the high level. The high level of the "IF cycle" signal is applied to the quiescent inputs R of the bistable circuit 229. and 233 by the OR gates 231 and 235 respectively and holds them at "O" and therefore unable to react to the high levels of the read signals

  of local oscillator counter and "= 4".

  If it is assumed for the moment that the'TF cycle 'signal is low, when the local oscillator counter preparation pulse appears, i.e. when the counter preparation signal goes to high level, the bistable circuit 229 is set to "1" and the bistable circuit 233 to "0" As a result, the channel number selection signal is high and the band number selection signal is at Therefore, in response to the counter read signal, the main multiplexer 205 transmits the binary signals representing the selected channel number stored in the channel number register 41 to the JAM inputs of the countdown counter.

principal 201.

  As already indicated, the signal "IF cycle", that is to say the complement of the signal "IF

  cycle "is applied to the control input of the multi-

  If it is assumed that the "IF cycle" signal is at the low level, the "IF cycl-e" signal is at the high level. As a result, the binary signals representing the synthesis and shift number, for example 2 S, produced by logical matrix 219 are

  applied to the JAN inputs of the auxiliary down counter 203.

  The local oscillator counter readout signal and the "IF cyc-le" signal are applied to the respective inputs of the AND gates 237 The output of the AND gate 237 is connected to an input of an OR gate 239 The output of the OR gate 239 is connected to the forcing input S of an SR FF 241 bistable circuit and to an input of an OR gate 243 The Q output of the bistable circuit 241 is connected to the preparation input PR of the main down counter 201 The output of the OR gate 243 is connected to the preparation input PR of the auxiliary down counter 203. Therefore, if it is still assumed that the "IF cycle" signal is high, when the counter preparation pulse local oscillator appears, the binary signals representing the channel number loaded in the main down counter 201 and the binary signals representing the number of synthesizers and shifts, for example 28, are loaded into the auxiliary down counter 203 The version divided into f the local oscillator signal (f LO / 256), the local oscillator counter enable signal, and the "IF cyc-le" signal

  are applied to the respective inputs of an AND gate 245.

  The output of the AND gate 245 is connected to an input of an OR gate 247 The output of the OR gate 247 is connected to the clock input C of the main down counter 201 Therefore, if it is still assumed that the "IF cycle" signal is at the low level, when the intermediate frequency counter authorization signal is high, the divided frequency version of the local oscillator signal is applied to the clock input C of the main down counter Then, the contents of the main down counter 201 are reduced by one in response to each pulse of the divided frequency version of the local oscillator signal. The output of the zero detector 211, associated with the main down counter 201 and the output of the inverter 225 which inverts the output signal of the unit detector 223 associated with the auxiliary down counter 204

  are connected to respective inputs of an AND gate 249.

  The output of the AND gate 249 is connected to the clock input of the auxiliary down counter 203 and to a second input of an OR gate. The AND gate 249 is opened to pass the high level of the "= O" signal. at the output of the detector 211 as the signal "= 1" produced at the output of the inverter 225 is high As already indicated, when the high level is produced at the output of the OR gate 239, the bistable circuit 241 is set to "1" 1 so that a high level authorization signal is generated at the preparation input PR of the main down counter 201. Therefore, whenever the contents of the main down counter 201 are equal to zero, and as long as the contents of the auxiliary down counter 203 have not reached unity, the contents of this auxiliary counter 203 are reduced by one and the binary signals applied to the JXM inputs of the main down counter 201 of a main multiplexer 205 are

  loaded in the main down counter 201.

  It should be noted that the exit of the door OR

  247 is also connected to the input of an inverter 251.

  The output of the inverter 251 is connected to the "0" input of the bistable circuit 241. As a result, the latter is set to "O" about half of a cycle of the divided frequency signal applied to the signal. clock input C of the main down counter 201 after being set to "1", for example in response to the signal "= O" of high level when the contents of the main down counter 201 is a zero This ensures that the authorization signal of the main down counter 201 does not last long enough for the binary signals applied to the JAM inputs of this down-counter to be loaded, but end before the next pulse of the divided frequency inversion applied to the clock input C of the down-counter This is important because, during the measurement of the frequency of the LO signal, the main counter 201 must be prepared between pulses of the frequency divided version of the LO signal on the number.

  every time the contents of the down-counter

  203 reaches zero and on the tape number when

  the content of the auxiliary counter 203 reaches four.

  The way this happens will now be described

  in relation to the specific structure of Figure 2.

  The signal "'= 4" is applied by the output of the detector "4" 227 to the forcing input S of the bistable circuit 233 and to an input of the door 235. When the contents of the auxiliary counter 203 reach 4, the high level at the output of the detector 227 is applied to the input S of the bistable circuit 233 and, by the OR gate 235, to the input R of the bistable circuit 229 -It follows that the bistable circuit 233 goes to "1" Assuming again, that the "IF cycle" signal is low, it results that only the main multiplexer 205 band number selection control signal is high. This causes the main multiplexer 205 to transmit the binary signals representing the band number, produced by the logical matrix 207 at the JAM inputs of the main down counter 201 Since the authorization signal of the up-down counter 201 produced at the output Q of the bistable circuit 241 has been set high when the contents of the main down counter 201 reached the new count that was passed to

  four the contents of the auxiliary meter 203, the -

  Binary signals representing the tape number are loaded into the main discounter 201. Then, the contents of the main down counter 201 are reduced by one unit in response to each pulse of the disc version.

  divided frequency of the local oscillator signal.

  Until the content of the auxiliary counter 203 reaches the unit, each time the contents of the main down counter 201 reaches zero the content of the auxiliary down counter 203 is reduced by one unit and the binary signals representing the band number are again charged to the main down counter 201 in response to the high level of the signal O applied to the clock input C of the auxiliary down counter 203 and to the input of the OR gate 239, thereby opening the AND gate 249 When the contents of the auxiliary down counter reaches the unit, the AND gate 249 no longer transmits the level of the signal "= O" to the clock input C-of the down-counter

  auxiliary-203, and OR gate 139.

  When the high level of the local oscillator counter enable signal ceases, the split frequency version of the local oscillator signal is

  decoupled from the clock input C, the main down-counter

  When the local oscillator counter sampling pulse 541545 appears just after the end of the logic level of the local oscillator counter enable signal, the device of FIG. 3 examines the contents of the main counter 201 and according to whether the synthesis authorization control signal or the automatic tuning authorization control signal is high and depending on the contents of the main down counter 201, the device of FIG. appropriate error or issue selectively or

  not an offset pulse as will be described hereinafter

next to Figure 3.

  To now switch to the intermediate frequency measurement, the "IF cycle" signal is applied to the main multiplexer 205, as the intermediate frequency number selection control signal When the high level of the "IF cycle" signal appears, the bistable circuits 229 and 233 are set to "011, so that the channel number select and band number select control signals for the main tipper 205 are low and the intermediate frequency number select signal for the main multiplexer 205 goes high. Therefore, the main multiplexer has: 205 transmits the intermediate frequency number, by way of example 366 produced by the logic array 209 to the JAM inputs of the main down counter 205 When the "IF cycle" signal is at the level high, the "IF ce" signal is at the low level. Therefore, the auxiliary multiplexer 217 transmits the binary signals representing

  the number of auxiliary intermediate frequency, that is,

  say four, at the JAM inputs of the auxiliary down counter 203.

  When the intermediate frequency counter preparation pulse appears high, it is applied by the OR gate 239 to the preparation input PR of the main down counter 201 and by the OR gate 243,

  at the preparation inlet PR of the auxiliary down counter 203.

3, LqouI The recufla-

  Therefore, the binary signals representing the intermediate frequency numbers of the main and auxiliary counters are loaded into the counters

201 and 203 respectively.

  The counter authorization signal

  intermediate frequency and the frequency version-

  The output of the AND gate 253 is connected to a second input of an OR gate 247 When the high level of the signal If the intermediate frequency counter is enabled, the divided frequency version of the intermediate frequency signal is transmitted by the AND gate 253 and the OR gate 247 to the clock input C of the main down counter 201 in response to each pulse of the version. of divided frequency of the intermediate frequency signal, the content of the main down counter 201 is reduced by one unit When the contents of the main counter 201 reach zero, until the contents of the auxiliary counter 203 reach the unit, the signal " = 0 "high level is applied by the AND gate 249 to the clock input C of the auxiliary down counter -203 and by the AND gate 249 and the OR gate 239 to the forcing input S of the bistable circuit 241 As a result, the contents of the auxiliary down counter 203 are reduced by one

  unit and that the binary signals representing the number of frequencies

  intermediate quency are loaded into the main counter 201.

  When the high logic level of the intermediate frequency counter authorization signal disappears, the AND gate 253 disconnects the frequency-divided intermediate frequency signal from the input

  the main countdown timer C 201 When the pulse of exchange

  Intermediate Frequency Counter Timer appears immediately after the end of the high level of the intermediate frequency counter authorization signal, the device of Figure 3 evaluates the contents

  the main counter 1201 to produce a pulse error or not.

  The structure of FIG. 3 will now be described. If the main counter 201 goes through zero counting during the interval where the content of the auxiliary counter 203 is the unit, the frequency of the measured signal is high and otherwise the frequency is low. Therefore, the structure of FIG. 3 comprises a data bistable circuit (D FF) 301 for determining whether the contents of the main counter 201 have reached zero count or not when counter counting.

  Auxiliary 203 was limited during the measurement interval.

  The bistable circuit 301 is placed at 0 "

  in response to the high levels of preparatory impulses

  oscillator counter and preparation

  intermediate frequency counter which are

  at its input R by the OR gate 303 just before the respective measurement interval The bistable circuit 301 receives the signal "1 = 111 at its data input D and the signal 1" = 01 "at its clock input C If the main counter 201 does not reach the zero count when the count of the auxiliary counter 203 is the unit, the bistable circuit remains at "0" and therefore, the signal produced at the output Q is at the low level and the signal at the output Q is at the high level at the end of the measurement interval If the main counter 201 reaches a zero count when the counter of the auxiliary counter 203 is the unit, the bistable circuit 301 is in the "1" state therefore, the signal at its output Q is high and the signal at its output Q is low at the end

of the measurement interval.

  AND gates 305 and 307 are used to produce a local oscillator high count pulse or a local oscillator low count pulse if the local oscillator signal frequency is high or low respectively in the mode operation. For this purpose, the authorization signs

  oscillation counter synthesis and sampling

  The output Q of the bistable circuit 301 is connected to an input of the AND gate 305 and its output Q is connected to an input of the AND gate 307.

  ET 305 and 307 are connected to the first

  Either the respective inputs of the OR gates 309 and 311 The low count and high count error pulses for the up / down counter 55 of the structure of FIG. 1 are generated at the outputs of the OR gates 309.

and 311.

  The AND gates 305 and 307 are open in response to the high level of the synthesis authorization signal to react to their other two inputs. If the frequency of the local oscillator signal LO is high, the bistable circuit 301 is set to "11". so that its output signal Q is high and its output signal Q is low during the local oscillator measurement interval Therefore, when the positive local oscillator counter sampling pulse appears just after the end of the measurement interval, it is applied by the AND gate 305 and the OR gate 309 to the up / down counter 55 as a high count error pulse If the frequency of the local oscillator signal is low, the bistable circuit 301 remains at "O" so that its output signal Q is low and its output signal Q is high at the end of the local oscillator measurement interval Therefore when the positive pulse of sampling of local oscillator counter appears; it is transmitted by the AND gate 307 and the OR gate 311 to the up / down counter 55

  as a low count error pulse.

  It should be noted that if the local oscillator frequency is correct, the bistable circuit 301 is set to

  - "1" just before the end of the oscil-

  It follows that a high counting pulse is produced even if the local oscillator frequency is correct. For this purpose, the device of FIG. 3 is arranged so as to always produce a low count error pulse or high count 33 - in operation in synthesis mode, so that

  the tuning voltage always exceeds its final value.

  The reason will be explained by referring to the organization

  logic of the tuning control unit 45.

  The AND gates 313 and 315 are used to produce an intermediate frequency low count error pulse or a high frequency intermediate count error pulse if the frequency of the intermediate frequency image carrier is low or high. During this operation, the automatic tuning and intermediate frequency counter sampling signals are applied to the respective inputs of the AND gates 313 and 315, the Q output of the circuit. bistable 301 is linked to an input of the AND gate 313 and its output U is connected to an input of the AND gate 315 Moreover, the output of an inverter 317 used to invert the "= O" signal is connected to an input of the AND gate 315 The outputs of the AND gates 313 and 315 are connected to the second gate entrances

OR 309 and 311.

  The AND gates 313 and 315 cooperate with the bistable circuit 301 in the same manner as the AND gates 305 and 307 to produce the low count and high count error pulses if the frequency of the IF carrier is However, the presence of the inverter 317 prevents the AND gate 313 from passing the local oscillator counter sampling pulse to the OR gate 309 if the contents of the main counter 201 are zero, so that the signal "= O" is low at the end of the intermediate frequency measurement Thus, if the intermediate frequency image carrier frequency is correct, no counting pulse

  low or high count is produced.

  It should be noted that the beginning of the measurement intervals is not synchronized with the respective frequency-divided signals Therefore, although the correct number of positive pulse transitions can be counted by the main counter 201 during a measurement interval, there may be a frequency error corresponding to at most one cycle of the divided frequency divided signal. This corresponds to an accuracy of 250 kHz for oscillator frequency measurement.

  and 31.25 kHz for the measurement of

  These accuracies are sufficient for the tuning of the television receivers The accuracy of the frequency measurements can be improved by reducing the division factor of the respective divider or by increasing the duration of the respective measuring interval. The first solution is undesirable. because it increases the frequency of the signal to which the sampler must operate

  The second solution is also inde-

  sirable with respect to the frequency measurement of the intermediate frequency signal because the frequency measurement interval may extend in the range of teletext and test signals in which the intermediate frequency image carrier can, under certain circumstances, be overmodulated for reasons already mentioned. The AND gates 319 and 321 and the OR gates 323 are used in conjunction with the detectors 213 and 215 of the circuit of Fig. 2 and with the flip-flop 301 to produce an offset pulse during the operation of the frequency lock loop. automatic tuning if the local oscillator frequency has changed from the value set in the previous operation of the frequency-locked loop of

  synthesis, a predetermined offset, for example 1.25 M Hz.

  During the local oscillator frequency measurement, as already indicated, each count of the main down counter 201 corresponds to an increment of 0.25 M Hz. Therefore, the detection of a frequency offset greater than 1.25 M Hz imposes the detection of a count 254 t 545

at i 5 zeros.

  As already indicated, the detector 213 "> 5" produces a high level "> 5" output signal if the contents of the main down counter 201 are greater than 5 at the end of the frequency measurement interval of local oscillator The output signal of the detector 215 "> 5" is applied to an input of an AND gate 319 which also receives the tuning authorization signal, the "IF cycle" signal, the Q output signal of the bistable circuit 301 and the local oscillator counter sampling signal to the other inputs When opened by the high level of the autotune enable signal and the high level of the "IF cycle" signal the AND gate 319 produces a positive pulse in response to the positive counter sampling pulse

  oscillator if the contents of the main down-counter

  pal 201 is greater than 5 at the end of the local oscillator frequency measurement interval Since, after the main down counter 201 has counted to zero, it continues to count down from the maximum count, the applying the output signal G of the bistable circuit 301 to an input of the AND gate 319 ensures that no positive pulse is produced by the AND gate 319 in response to the local oscillator counter sampling pulse, unless the count is

  actually greater than 5 above zero and not in

  response to the detection of a large count at the end of the measurement interval resulting from a count having

passed through zero.

  As already indicated, the detector 215 "<max 4" produces a high level "<max 4" output signal if the main down counter 201, after a count of zero, has reached its maximum count for which the counter 201 can count, the detector 629 detects whether the contents of the counter 201 go to 4 below the maximum count The output signal of the detector 215 is applied to an input of an AND gate 321 which also receives the authorization signal from automatic tuning, the "IF cycle" signal, the Q output signal of the bistable circuit 301 and the sampling signal

  oscillator counter to the other inputs

  When opened by the high level of the auto tuning enable signal and the high level of the "IF cycle" signal, the AND gate 321 produces a pulse.

  in response to the positive impulse of sampling

  local oscillator counter buffer if the contents of the main down counter 201 are less than 4 at the maximum count at the end of the local oscillator frequency measurement interval Since the frequency measurement operation begins with authorization of the down-counter

  201 to count from a relative number of

  Although large, the application of the Q output signal of the bistable circuit 301 to an input of the AND gate 321 ensures that no positive pulse is produced by the AND gate 321 in response to the counter sample pulse. oscillator-unless the count has already passed through zero and therefore

more than five below zero.

  The outputs of the AND gates 319 and 321 are

  connected to the respective inputs of the OR gate 323.

  The positive shift pulse is generated at the output of the OR gate 323 when a positive pulse appears at the output of either one of the AND gates 321 and 319. Figure 4 shows a logic circuit.

  intended to produce the impulses of preparation, self-

  oscillator counter sampling and sampling

  shown in Figure 4 a More particularly

  In fact, an inverter 401 and an AND gate 403 combine the delay signals R and 2 R to produce the

  Local oscillator counter preparation pulses.

  The timing signal R, of a period of 2048 microseconds, is used as the local oscillator counter authorization signal. The inverter 401, the inverter 405 and the AND gate 407 combine the delay signals R, 2 R. and 4 R to produce the pulses

  sample of the local oscillator counter.

  FIG. 5 shows a logic circuit for producing intermediate frequency counter preparation, authorization and sampling pulses and the "IF cycle" and "IF cycle" signals.

  of Figure 5a During the description that follows

  of Figure 5, it will be useful to refer to the

figure 5 a.

  As already indicated, the vertical pulse detector 71 shown in FIG. 1 produces a positive vertical pulse (waveform

  B) after the first synchronization pulse ver-

  during the vertical return interval.

  vertical is applied to the D data entry

  of a DFF 501 bistable circuit The delay signal

  64 R (C waveform) from a period of 32 micro-

  seconds is applied to the clock input C of the bistable circuit 501 This last goes to "1" so that its output

  Q at the high level in response to the first transi-

  of the 64 R timing signal occurring after the generation of the vertical pulse (form

uncles B).

  The Q output of the bistable circuit 501 is linked to the input D of the flip-flop circuit D FF 503 The delay signal 64 R is applied to the input C of the flip-flop 501 The flip-flop 503 is set to "1" so that a low level appears at its output b in response to the second positive transition of the reference signal produced after the emission of the vertical pulse (waveform B). The output Q of the bistable circuit 501 and the output Q of the Bistable circuit 503 are connected to inputs of a NAND gate 505 Therefore, a negative pulse D of a duration equal to the cycle time of the timing signal 64 R is produced at the output of the NAND gate 505 after the

-2541545

  first positive transition of the timing signal 64 R which occurs after the generation of the vertical pulse (waveform B) The output signal of the NAND gate 505 is applied to an inverter 507 which produces the pulse positive intermediate frequency counter preparation (waveform D) in response to the negative pulse D. The intermediate frequency counter preparation pulse is applied to the forcing input S of a bistable circuit D FF 509 The "IF cycle" signal (G waveform) is produced at the Q output of the bistable circuit 509 and the complementary signal is produced at the output d of this bistable circuit In response to the frequency counter preparation pulse intermediate, the bistable circuit 509 is set to "1" so that the "IF cycle" signal goes to

  high level and the complementary signal at the low level.

  The negative pulse b is applied to the clock input C of a bistable circuit D FF 511 A high level "1" is applied to the input D of this bistable circuit 511 The frequency counter authorization signal intermediate (waveform E) is produced at the output Q of the bistable circuit 511 This latter goes to "1" in response to the positive transition of a negative pulse D causing that the intermediate frequency counter authorization signal produces at its output Q goes high while the signal at its output

goes low.

  The duration of the high level of the authorization signal

  intermediate frequency counter, that is to say

  the duration of the interval frequency measurement interval

  The intermediate frequency counter preparation pulse is applied to the quiescent input R of the counter 513 to reset its count to zero before the measurement interval. counter 513 counts the pulses of the timing signal 64 R applied to

41545

  its clock input C When eight periods of the timing signal 64 R have been counted, a high level appears at the output of its fourth stage Q 4 The output Q 4 of the counter 519 is connected to the idle input R of the circuit In response to the high level of the signal produced at the output Q 4 of the counter 513, the bistable circuit

  511 is reset to zero so that the authorization signal

  intermediate frequency counter produced at the output Q of the low-level bistable circuit 511, this

  which ends the interval of measurement of international frequency

  Since each period of the signal of

  delay 64 R has a duration of 32 microseconds, the

  Intermediate Frequency Measuring Range has a duration of 8 x 32, ie 256 microseconds. The intermediate frequency counter preparation pulse is applied to the quiescent input R of counter 513 to return it to zero count before measurement interval. The intermediate frequency counter sampling pulse (F waveform) is produced by a FF 515 bistable circuit, an AND gate 517 and an inverter 519. The output signal Q (E) of the bistable circuit 511 is applied. at the clock input C of the bistable circuit 5150 A logic high level "1" is applied to the data input D of the bistable circuit 515. The Q output of the latter is connected to an input of an AND gate 517. timing signal 64 R is inverted by the inverter 519 and the resulting signal is applied to the other input of the AND gate 517 In response to the positive transition produced at the output O of the bistable circuit 511 when the measurement interval is ends, a high level appears at the Q output of the bistable circuit 515 which opens the AND gate 517 The signal produced at the output Qi of the first stage of the counter 513 is applied to the R input of the bistable circuit 515 Therefore, the latter is brought back to "O" which ends the high level at its output Q and closes the AND gate 517, a cycle of the timing signal 64 R after the end of the intermediate frequency measurement interval Thus, the AND gate 517 is open to pass a pulse of the signal of timing 64 R at its output as the intermediate frequency counter sampling pulse after the end of the interval

  intermediate frequency measurement.

  The intermediate frequency counter sampling pulse is applied to an inverter 521 The output of the inverter 521 is connected to the clock input C of the bistable circuit 509 The data input D of the latter receives the level Therefore, in response to the negative transition of the intermediate frequency counter sampling pulse, the bistable circuit 509 changes from 0 "so that the" IF cycle "signal produces at its output Q goes low. and the "IF cycle" signal at its output Q goes high. The synthesis authorization signal is applied to the quiescent inputs R of the circuits

  bistable 501 and 509 The high level of the

  The synthesis process prevents the generation of intermediate frequency counter preparation, authorization, and sampling pulses and causes the IF cycle signal to go high during operation.

in synthesis mode.

  Fig. 6 shows a logic embodiment of a vertical synchronization pulse detector 71 shown as a box in Figs.

  and during the description of Figure 6, it will be

  It is useful to refer to the waveforms in Figure 6a.

  The embodiment of the pulse detector

  FIG. 6 shows two-stage quiescent counters 601 and 603. The timing signal 256 R of an 8 microsecond period is applied to the clock input C of counters 601 and 603. The composite signal 254154 i

  synchronization pulse containing the synchronization pulses

  horizontal and vertical correction and correction is applied to the R input of counter 601

  and at the input of an inverter 605 The output of the invert-

  605 is connected to the idle input R of the

counter 603.

  The intervals between the relatively narrow positive pulses of the output signal of the inverter

  605 correspond to the durations of the synchronization pulses

  relatively large positive vertical

  during the vertical return interval As the

  Figure 6a shows the duration of a sync pulse.

  The counter 603 is held at rest by the high level of each positive pulse of the output signal of the inverter 605. Thus, the presence of the pulses is the same as the duration of three consecutive cycles of the timing signal 256 R. of vertical synchronization is indicated if three positive clock pulses are counted by the counter 603 between consecutive positive quiescent pulses. To detect this event, an output of the first and second stages of the counter 603, Q1 and Q2 are connected. at the inputs of an AND gate 607 When the signals produced at the outputs Qi and Q 2 of the counter 603 are high, the AND gate 607 delivers a high level at its output The output of the AND gate 607 is connected

  at the S forcing input of a S-R FF 609 bistable circuit.

  The high level produced at the output of the AND gate 607 changes to "1" the bistable circuit 609, thus producing a high level at its output Q This latter is connected to an input of an AND gate 613 The output of a 615 synchronization validity detector is connected

  at the other entrance of the AND gate 613 The vertical impulse

  hold is produced at the exit of the AND gate 613 when the bistable circuit 609 is at "1" and when a high level is produced at the output of the detector 615 of validity

  synchronization as will be described below.

  As shown in FIG. 6A, the interval between relatively narrow, positive post-correction consecutive pulses (as well as the interval between relatively narrow consecutive positive pre-correction pulses) roughly corresponds to the

  duration of three consecutive cycles of the time signal

  The counter 601 and an AND gate 611 are arranged similarly to the counter 603 of the AND gate 607 to produce the high level when three clock pulses have been counted between two consecutive positive post-correction pulses to detect thus the beginning of a post-correction interval The output of the AND gate 611 is connected to the input R of the bistable circuit 609 to bring it back to "O", thus ending the high level produced at the output Q of

this bistable circuit.

  It should be noted that some sources of high frequency television signals, such as games

  video, may not produce the pulses of pre-

  correction and post-correction But the device shown in Figure 6 operates in substantially the same manner as described, except that the bistable circuit 609 is reduced to "O" when three clock pulses are counted by the counter 601 between horizontal synchronization pulses

  consecutive rather than post-impulse

consecutive correction.

  The synchronization validity detector 615

  It responds to the composite sync signal and produces the high level output signal which opens the AND gate 613 to produce the vertical pulse when the composite sync signal is correct and relatively free of noise. Synchronization may simply consist of an average detector. Another suitable arrangement for the synchronization validity detector 615 is operating by examining the frequency and period of the composite timing signal to determine its validity, and is described in the patent application. No. 261,449 filed May 8, 1981, in the name of MP French and J Tults. In a relatively pest-free environment, the detector 615 and the AND gate 613 can be suppressed. vertical pulse is produced directly at the Q output of the bistable circuit 609.

  FIG. 8 represents a specific embodiment

  of a structure including the multiplier

  binary 57, the low-pass filter 59 and the counter-

  upcounter 55 which will now be described.

  The number of stages of the binary multiplier 57 is chosen to ensure that the steps of the voltage

  okay do not produce oscillating frequency steps

  In this example, 14 stages have been found suitable for this purpose. The frequency of the clock signal for the binary multiplier 57

  is chosen to give sufficient time to this multi-

  to complete its operating cycle and for the tuning voltage to change between the error pulses which appear once per frame in the automatic tuning mode As indicated by way of example in FIG. 4 MHz has proved to be suitable for this purpose As indicated above, the operation in the synthesis mode is divided into magnified, mean and precise chord intervals in each of which the number of states of the multiplier that can be changed is limited to ensure that the clock signal at 4 M Hz allows a suitable time for the tuning voltage to change between error pulses. Moreover, the choice of a frequency of 4 MHz clock for the binary multiplier 57 allows the use of practical values of resistance and capacitance for the low-pass filter 59, as shown in FIG. 8, to ensure that in the worst case,

  the ripple of the tuning voltage produces fluctuations

  local oscillator frequency

  less than those which may cause

  visible frequencies (eg fluctuations at 50 K Hz).

  The binary multiplier 57 can be -

  realized in a manner similar to the commercially available CD 4089 integrated circuit binary multiplier

  by RCA Corporation, Somerville, New Jersey.

  With regard now to the realization of the low-pass filter of FIG. 8, the output signal of the multiplier 57 is applied to the first inputs

  AND gates 801 and 803 The control signal of

  The synthesis signal is applied to the second input of the AND gate 801 and an automatic tuning authorization control signal is applied to the second input of the AND gate 803. During operation in synthesis mode, the authorization signal of synthesis is at the high level, thereby opening the AND gate 801 to apply the output signal of the multiplier 57 to a first low pass filter section of the filter 59 consisting of a resistor 805 and a capacitor 807. automatic tuning, the auto tuning enable signal is high, thereby opening the AND gate 803 to transmit the output signal of the binary multiplier 57 to a second section of the low pass filter 59 comprising a resistor 809 and a capacitor 807 The common point of the resistors 805 and 809 and the capacitor 807 is connected to the input of an amplifier 61 which amplifies the DC voltage produced by the low-pass filter 5 9 as indicated by the

  Figure 1 Since the structure of the filter passes

  59 is relatively simple, consisting simply of two resistors and a capacitor, a significant saving is obtained with respect to more complicated active low-pass filter arrangements generally used in loop-loop tuning control devices.

phase lock.

  The down-counter 55 shown in FIG. 8 is a fourteen-stage counter in which

  a two-stage up-down counter 55a, a counter-

  Four-stage down-counter 55b, a four-stage down-counter c and a four-stage up-down counter 55d are connected in cascade, with the back-off outputs CO of the up-down counters 55a, 55b and 55c connected by OR gates 811a, 811b and 811c at the IC inlets of the up / down counters 55b, 55c and d respectively The counters 55a to 55d can be made in a manner similar to that of a counter. binary down counter in integrated circuit CD 4516

  broadcast by RCA Corporation, Somerville, New Jersey.

  The low count or high count error pulses from the frequency sampler 30 are transmitted by a NOR gate 813 directly to the clock input C of the up-down counter

  d and selectively at the clock inputs of the counters-

  downcounters 55c, 55b and 55a, respectively by the NOR gate 813 and the AND gates 815c, 815b and 815a The coarse tuning, middle tuning and tuning control signals are reversed by inverters 817c, 817b and 817a and the resulting signals are applied to

  inputs respectively of the AND gates 815c, 815b and 815a.

  Therefore, the AND gates 815c and 815b and 815a can not transmit the error pulses to the respective clock inputs in response to the high levels of the coarse tuning, middle tuning, and tuning control signals. precise agreement produced by the control unit

agree 45.

  When the coarse tuning control signal is high, the AND gates 815c, 815b and 815a are closed and the error pulses are only

254 1545

  applied to the clock input of the counter 55 d When the average tuning control signal is high, the AND gates 815b and 815a are closed and the error pulses are applied only to the clock inputs 55 d and 55 c When the precise tuning control signal is high, the AND gate 815 a is

  closed and the error pulses are applied only-

  At the clock inputs of the counters 55d, 55c and b When none of the coarse tuning, medium tuning and tuning tuning signals are high, the error pulse is applied to the clock inputs of all counters 55 d, 55 c, 55 b and 55 a The coarse tuning, medium tuning and tuning control signals are also applied to the inputs of OR gates 811 c, 811b and 811a and when they are high they produce high level restraint signals at

  intake of the meters 55 d, 55 c and 55 b respec-

  As will be described in more detail with respect to the structure of Fig. 9, the tuning control unit 2b 43 passes the coarse tuning, medium tuning, and tuning tuning control signals. At the high level for successive intervals as shown in Fig. 9a In the automatic tuning mode, all control signals are set low so that the complete 14-bit resolution of the counter 55 is available. An SR FF 819 bistable circuit receives the high counting error pulses at its forcing input S and the low count error pulses at its idle input R, and its output Q is connected to the count control inputs and counting countdowns a-55 b When high counting error pulses are generated, the bistable circuit 819 is set to

  "1" so that a high level appears at its output.

  When low count error pulses are pro-

  8e is set to "O" so that a low level appears at its output Q When a high level is developed at the output Q of the bistable circuit 819, the contents of the counters 55a-55b progress in response to error pulses When a low level appears at the Q output of the bistable circuit 819, the contents of the counters 55 a-55 d decrease in response to the error pulses. FIG. 9 represents a logical embodiment of the tuning control unit 45 shown

  in the form of a box in Figure 1.

  the figure in Figure 9, it will be useful to

  refer to the waveforms in Figure 9a.

* In the structure of Figure 9, the confi-

  logic gating including an AND gate 901 and bistable circuits 903 and 905 selects one of the local oscillator counter preparation pulses to produce a start pulse after the high level of the new channel signal has been generated when A new channel is selected. The AND gate 901 is opened in response to the signals generated at the Q output of the flip-flop 903 and at the U output of the flip-flop 905 for an interval long enough to allow just one readout pulse. be applied from its input to its output as the start impulse

shown in Figure 9 a.

  The start pulse is applied to an input S of an S-R FF 907 flip-flop which, in response, produces the high-level synthesis enable signal at its Q output.

  The start pulse is also applied

  at the respective inputs S of the bistable circuits 909 and 911 which cooperate with an AND gate 913 to produce a positive quench pulse which overlay a local oscillator counter sampling pulse as shown in FIG. will be

explained later.

  A S-R FF 915 bistable circuit, a FF 917 bistable circuit and a FF 919 bistable circuit with a NOR gate 921, an OR gate 923, and a NOR gate 925 produce the tuning signals.

  rude, of average agreement and precise agreement for the dis-

  positive of Figure 8 More particularly, the coarse tuning control circuit is set high in response to the new channel signal and then, the tuning and tuning control signals are set high, one at a time and successively in response to the respective variations in the direction of the frequency error detected by the local oscillator frequency sampler 31, which is manifested by corresponding alternating productions of the low count pulses.

and high counting.

  With regard to now more particularly

  In the structure shown in FIG. 9, the high counting and low counting error pulses produced by the frequency sampler 30 are respectively applied to the forcing and S forcing inputs R of the SR FF 915 tilting circuit. The outputs U and Q of the bistable circuit 915 are applied to the clock inputs C of the bistable circuit D 917 and 919 respectively. The outputs Q and the inputs D of the circuits

  917 and 919 are connected together to

  these bistable circuits as trickle circuits

  The "0" pulse is applied to the R inputs of the bistable circuits 917 and 919. The precise tuning authorization signal produced at the Q output of the bistable circuit 907 is applied to the inputs S of the bistable circuits 917 and 919. the Q output of the bistable circuit 917, identified by A is applied to a first input of a NOR gate 221 and a first input of an XOR gate 923 and the signal to the Q output of the circuits bistables 917, designated A is applied to a first input of the NOR gate 925 The signal at the Q output of the bistable circuit 919, identified by B, is applied to a second input of the NOR gate 921 and to a second input of the XOR gate 923 and the signal of the U output of the bistable circuit 544 identified by B is applied to a second input of the XOR gate 925 The automatic tuning enable signal is applied to a third input of the

NOR gate 925.

  During the auto tuning mode, when the auto tuning enable signal is high, the NOR gate 925 is closed and does not respond to signals I and B as it still delivers.

  the low level at its output in response to the signal of auto-

  In the synthesis mode, when the automatic tuning enable signal is low, the NOR gate 925 is allowed to respond to the signal levels A and B. coarse tuning is produced at the output of the NOR gate 921 The average tuning signal is generated at the output of the XOR gate 923 The tuning signal

  accurate is produced at the exit of the NOR gate 925.

  The positive quiescent pulse produced in response to the new high level channel signal, returns the two bistable circuits 917 and 919 to "0." As a result, the signals A and B are both low and in response. at the positive idle signal, the coarse tuning signal at the output of the NOR gate 921 goes high. At the same time, the average tuning signal at the output of the XOR gate 923 goes low and the precise chord signal at the output of

OR gate 925 is low.

  During the coarse tuning interval, the frequency of the local oscillator signal is higher or lower than it should be, and low count and high count error pulses are successively generated. It will be assumed that example that the local oscillator frequency is lower than it should be after the selection of a new channel so that low count error pulses are produced as shown in Figure 9 a Then

2541545

  the operation of the frequency sampler 31

  of local oscillator together with the counter-

  down counter 55, the binary multiplier 57, the filter

  low-pass 59 and the amplifier 61 cause the increase

  the local oscillator frequency increases until it exceeds its final or correct value and high counting error pulses are generated instead of the error pulses of As a result, the bistable circuit 915 switches to "10" so that a positive pulse is produced at its output Q. The bistable circuit 917 thus goes to "1" so that the signal A goes high and the At this time, B is still low and B is still high. As a result, the coarse tuning signal is at the low level, the average tuning signal is at the low level.

  high and the precise tuning signal at the low level.

  In response to the high counting error pulses, the local oscillator frequency decreases. When the local oscillator frequency again exceeds its final value, the low count error pulses are generated again instead of the pulses of the local oscillator. high counting error This again causes the bistable circuits 915 and 919 to change to "1" so that A and B are at level and X and B at low level. As a result, coarse tuning and tuning signals medium are low and the fine tuning signal goes high.As already indicated, the logic part comprising the elements 901 to 913 produce

  the impulse of resting which covers the first impulse

  sampling pulse and therefore, the first high count or low count error pulse produced after the high channel new signal This ensures that the bistable circuit states 917 and 919 are not changed until the direction of frequency correction changes under normal operating conditions If the quiescent pulse did not cover the first error pulse, a

  change from one type of error pulse to another

  This could lead to a change of the states of the bistable circuit 915 of one of the bistable circuits 917 and 919, thus disrupting the correct sequence of production of the bistable circuits 917 and 919, thereby disrupting the correct sequence of production of the bistable circuits 917 and 919. control signals

  rough agreement, medium agreement and precise agreement.

  The output of the NOR gate 925 is connected to the input S of the bistable circuit 927.

  the latter is connected to an input of an AND gate 929.

  The output of the NOR gate is also connected to the input of an inverter 931 whose output is connected to a second input of the AND gate 929 The output of the latter is connected to the R input of the bistable circuit

  907 As already noted, the authorization signal

  synthesis is produced at the Q output of the circuit

  bistable 907 and the auto-tuning authorization signal

  This is produced at the U output of the 907 bistable circuit.

  In response to the high tuning signal at the high level, the bistable circuit 907 is set "1" so that its output

  Q goes high, which opens door D 929.

  When the precise tuning signal is set low, a corresponding high level is produced by the inverter 931 and applied by the open AND gate 929 to the R input of the 907 bistable circuit. the automatic tuning authorization signal produced at the output U of the bistable circuit 907 The start pulse is applied to the input R of the bistable circuit 927 and places it at O "j This closes the AND gate 929 and avoids that the appearance of a low level at the output of the NOR gate 925 during the synthesis mode causes "0" to turn on the bistable circuit 907 until after the

  production of the precise tuning signal at the high level.

  Due to the high level automatic tuning enable signal, the binary circuits 917

  and 919 remain at "1" during auto tuning mode.

  As a result, A and B remain at the high level and A and B at the low level during the automatic tuning mode. As already indicated, the high level automatic tuning enable signal also prevents the NAND gate. OR 925 to react to the X and B signals by placing its output at the low level. As a result, in the automatic tuning mode, all the coarse tuning, middle tuning, and tuning tuning signals are at the same level. low. The shift signal is applied to a second forcing input S of the bistable circuit 907 Ce

  last is set to "1" in response to the deceleration impulse.

  This completes the automatic tuning mode and triggers the synthesis mode again. In response to the signal, the synthesis authorization signal goes high and the automatic tuning authorization signal low. automatic tuning authorization, the NOR gate 925 is allowed to respond to signals A and 3 which are

  low (having been put into this state by the self-signal

  The result is that the precise tuning control signal is at the high level. Then, when the oscillator frequency

  exceeds its final value, one of the

  917 and 919 go to "O". As a result, the precise tuning signal goes low. As described above, when the high level of the precise tuning signal ceases, the bistable circuit 907 switches to "O" 'so that the automatic tuning authorization signal goes high and the authorization signal of

low level synthesis.

  The invention has been described above in the context of a frequency locked loop tuning system but it can also be used in a phase locked loop tuning system, for example in the described type. in the US patent

  No. 4,078,212 In addition, in the mode of

  the specific tone that has been described, the measurement of the intermediate frequency of images is made during the interval of the vertical scan return, but it should be noted that it could be done during the horizontal scan return intervals The specific mode of The embodiment described has a single counting device operating in time-sharing for measuring the local oscillator frequency and the intermediate frequency, but separate counters could be used for these functions. Of course, various other modifications may be made by those skilled in the art to the embodiment described and illustrated by way of example

  in no way limiting without departing from the scope of the invention.

Claims (11)

  A tuning control apparatus for a television receiver of the type comprising an input for high frequency television signals corresponding to respective channels, each high frequency signal comprising an image carrier modulated with video information containing information images in image intervals appearing between horizontal scan return intervals appearing themselves between vertical scan return intervals, a high frequency stage (3) for processing said high-frequency signals;   frequency, a local oscillator (7) to produce an oscillation signal   localizer (LO) having a frequency related to said selected channel in response to said tuning control signal, a mixer (5) which is coupled to said high frequency stage and responsive to said signal   local oscillator by producing an intermediate frequency signal   diary containing an image carrier modulated in the same way   that the image carrier in said high frequency signal cor-   responding to the selected channel, an image processing device (13, 15, 23) responsive to said intermediate frequency signal for producing an image signal which represents said information   images contained in the said intervals of images, and a   synchronization processing system (17, 25, 27, 29) responsive to said intermediate frequency signal by producing signals   of horizontal and vertical synchronization respectively representing   the occurrence of said horizontal scan return intervals   zontal and vertical, characterized in that it comprises a tuning control signal generating device (55, 57, 59, 61) which produces said tuning control signal, a tuning device   precise tuning control (30) coupled to said generic device   a tuning control signal generator responsive to said intermediate frequency signal, when authorized to do so, by controlling said tuning control signal to bring said intermediate frequency carrier to its nominal frequency and a precise tuning authorization device (71) coupled to said precise tuning control device (30) and responsive to some of the timing signals by selectively enabling said precise tuning controller (30) to react to said intermediate frequency signal during predetermined portions of certain respective ones   said scan return intervals.   Apparatus according to claim 1, characterized   in that said authorization device   (71, 501-521) selectively authorizes the said provision   precise tuning control system (30) to react to the audit   intermediate frequency signal in a predefined   completed said vertical scan return intervals.   Apparatus according to claim 2, characterized   in that said authorization device   (71, 501-521) selectively authorizes the said provision   precise tuning control system (30) to react to the audit   intermediate frequency signal during a pre-   determined from said scan return interval -   vertical which is outside the auxiliary intervals,   reserved for test or teletext information.   Apparatus according to any one of the   1 to 3, characterized in that said precise tuning control device (30) comprises a counting device (30; 201-205, 209, 211, 217, 221-225, 237-253)   for counting the cycles of said intermediate frequency signal   when it is authorized to do so by the said   precise tuning authorization device (71; 501-521).   Apparatus according to claim 4, characterized in that it comprises a synthesis tuning control device (41-45, 50, 213, 215, 219, 227-233, 305, 307, 401-407) coupled with said tuning control signal generating device responsive to said local oscillator signal by controlling the control signal   agree so that the frequency of the oscil-   the local frequency is related to its nominal frequency for   channel selected in a predetermined manner.   An apparatus according to claim 5, wherein said counting device (30) comprises a counter (201,203) characterized in that the same counter (201,203) is selectively enabled to count cycles of said intermediate frequency signal during a first interval and selectively allowed to count cycles   of the local oscillator signal during a second inter- valle.   Apparatus according to claim 2, characterized   in that said precise tuning control device   has an intermediate frequency counter (30; 201-   205, 209, 211, 211, 221-225, 237-253) to count cycles   said intermediate frequency signal during an inter-   predetermined intermediate frequency measurement range when authorized to do so by said accurate tuning authorization device and an intermediate frequency error signal generating device (301, 303, 309-315) coupled with said counter to produce either   a low frequency counting error signal   mediary, ie a high count error signal of intermediate frequency according to the direction of the deviation if it exists, of the counting of said intermediate frequency counter at the end of said measurement interval of   intermediate frequency in relation to a predetermined count   an intermediate frequency signal corresponding to the nominal frequency of said intermediate frequency image carrier, said tuning control signal generating device having a count-down device (55) coupled to said error signal generating device for counting or counting according to whether said intermediate frequency low count error signal or said intermediate frequency high count error signal is produced by said intermediate frequency error signal generating device, a pulse generating device ( 35,37,57) coupled to said count-downcounting device for producing a pulsed signal whose average value depends on the mounting of said counting counting device and a filtering device (59) of said pulsed signal for   producing said tuning control signal.   Apparatus according to claim 7, characterized in that said pulse generating device comprises a binary multiplier (57) which produces, in a given interval, a number of pulses which depends   counting said counting counting device (55).   Apparatus according to claim 8, characterized   characterized in that it comprises a synthesis tuning control device (41-55,50,213,215,219,227-233, 305, 307, 401,407) coupled to said tuning control signal generating device for controlling said control signal of whereby the local oscillator signal is at the desired frequency related to its nominal frequency for the selected channel in a predetermined manner, said synthesis tuning controller (301, 303, 309-315) including a counting device oscillator (213,215,219, 227-233, 401-407) for counting cycles of said local oscillator signal during a predetermined interval   oscillator measurement and a general device   a local oscillator error signal driver (305,307) coupled to said local oscillator counting device for producing either a local oscillator low count error signal or a high count error signal of local oscillator as a function of the count of said local oscillator counting device at the end of said local oscillator measurement interval in relation to a predetermined local oscillator count corresponding to the desired local oscillator frequency, said counting device -discounting (55) also being coupled to said local oscillator error signal generating device for counting or counting according to a low count error signal 2541 '545   of local oscillator or high counting error of oscil-   local filter is produced by the generating device   of local oscillator error signal.   Apparatus according to claim 9, characterized   characterized in that it comprises a control device   mode (45) which controls said counting device-   downcounting (55) to respond to local oscillator error signals in a synthesis mode after a new channel has been selected and which controls said up / down counting device to respond to said counter signals; intermediate frequency error in a precise tuning mode after the frequency of said local oscillator signal has been brought within a predetermined range of its nominal frequency in the synthesis.   Apparatus according to claim 10, characterized   characterized in that said counting-counting device (55) comprises a multi-stage up-down counter (55a, 55b, 55c, 55d) and a stage selection device (811a, 811b, 811). c, 813, 815a, 815b, 815c, 817a, 817b, 817c, 819) coupled with said mode control device (45) for allowing successively lower order group stages of said up-down counter multiple stages to react to said local oscillator error signals   during operation in the synthesis mode.   Apparatus according to claim 10, characterized   characterized in that said mode control device (45) comprises a sense detection device (915, 917, 919) coupled to said local oscillator counting device (305; 307) for detecting whether the direction of said error signals of local oscillator produced by said local oscillator counting device changes during said synthesis mode, and a frequency control device (921-925) coupled with said sense detection device (915,917,919) and said selection device stages (811a, 811b, 811c, 813, 815a, 815b, 815c, 817a, 817b, 817c, 819) for controlling some of said lower order group of stages successively said up-down counter multi-stage (55 A, 55 b, 55 c, 55 d)   to react to said oscillation error signals   when the direction of the oscillator error signals   the local variable changes during said synthesis mode, and   being coupled with said counting device   counting (55) to control the latter so that it   responds to said intermediate frequency error signals   when the direction of said local oscillator signals   has changed a predetermined number of times.