FR2481553A1 - PHOTOSENSITIVE DEVICE LU BY CHARGE TRANSFER AND TELEVISION CAMERA COMPRISING SUCH A DEVICE - Google Patents

Abstract

THE PRESENT INVENTION CONCERNS A PHOTOSENSITIVE DEVICE READ BY TRANSFER OF CHARGES. THIS DEVICE INCLUDES A PHOTOSENSITIVE ZONE 1 CONSTITUTED OF A MATRIX OF PHOTOSENSITIVE POINTS. EACH PHOTOSENSITIVE POINT CONTAINS A LOAD READING DIODE D. CAC METAL CONNECTIONS CONNECT THE READING DIODES OF A SAME COLUMN TO A SINGLE DIODE D FOLLOWED BY A GRID G BROUGHT TO A CONSTANT POTENTIAL V. THE OPERATION OF THE DEVICE CONTAINS REPETITION IN TWO STEPS, STEP T AND STEP T. DURING STEP T, PARASITIC CHARGES, DUE FOR EXAMPLE TO TOO INTENSE ILLUMINATION, ARE TRANSFERRED FROM DIODES D TO DIODES D AND EVACUATED BY DIOD D DURING STEP T, THE SIGNAL LOADS STORED BY THE POINTS OF A LINE OF THE MATRIX ARE TRANSFERRED INTO A MEMORY THEN IN A READ REGISTER FOR LOAD TRANSFER R. THE READING OF THESE LOADS BY THE REGISTER S ' THEN CARRIED OUT DURING THE FOLLOWING STEPS T AND T UNTIL THE REGISTER RECEIVES THE LOADS CORRESPONDING TO THE READING OF THE FOLLOWING LINE. APPLICATION TO TELEVISION CAMERAS.

Description

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  The present invention relates to a photosensitive device read by charge transfer. It also concerns a camera of

  television with such a device.

  It is known in the prior art, in particular by the work of C.H. SEQUIN and M.F. TOMPSETT entitled "Charge transfer defects", pages 152 to 169, essentially two types of photosensitive devices using charge transfer. These are: - on the one hand, the photosensitive charge transfer devices in which the light radiation is sent on charge transfer registers. Various possible organizations are known of radiation registers and charge transfer registers which serve to store charges before they are read; the most common organizations are of the "frame transfer" or "structural" type

  These devices have the disadvantage of requiring

  to have large areas of charge transfer devices while it is currently difficult to obtain high yields for the manufacture of these large areas;

  on the other hand, photosensitive devices of the type C.I.D.

  (Charge Injection Devices) that do not exhibit this incon-

  venient. These devices comprise a matrix of photosensitive points consisting of two MOS capacitors coupled by a grid. One of the capabilities is subject to radiation

  luminous. The charges induced under this capacity are

  transferred to neighboring capacity and reading

  charges are made by a MOS transistor. Two registers

  very digital offsets allow the addressing of each point for reading: -the capabilities of the same line that are subject to radiation are connected in parallel and addressed by one of the register while the capabilities of the same column that are used for reading are connected in parallel

  and addressed by the other register. The devices C.I.D. pre-

  have the disadvantage of requiring re-injection of

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  in the semiconductor substrate where capabilities are

  integrated during or after the reading of the loads. This re

  In order to be effective, injection requires the use of epitaxial substrates or collector diffusions. It is also difficult to control and can be the occasion for a remanence, in case it is incomplete. Moreover, in the devices of the type C.I.D., the reading of the loads is done on a strong capacity which reduces the report - signal / noise and this capacity

depends on the number of lines.

  Also known from the article published in the journal "I.E.E.E. Journal of Solid-state circuits", volume SC 14, number 3, June 1979, pages 604 to 608, a photosensitive device which comprises a matrix type C.I.D. read by transfer of charges (see

  particularly Figures 7 and 8 of this article and their commentary).

  In this device, the addressing of the reading capacities is carried out

  by a shift register C.C.D. (Charge Coupled Devices).

  The reading of each row of the matrix is done in two steps: - in a first step, one fixes the potential of all the capacities of reading. There is charge transfer transversely in the C.D. C. register and evacuation of these charges by MOS transistors TG2; - in a second. step, the transfer of charges under the reading capabilities causes the injection into the C.C.D. of

  signal charges which are read in series by longitudinal transfer.

  The transfer of charges is of the "Bucket Brigade" type, that is,

  to say that it is done through the analog of a transistor

MOS polarized in saturation.

  A disadvantage of this device is that to be effective, this type of transfer requires a relatively long time. For this device to be operable by a television camera, the first step and the second until the injection of the signal charges into the C.C.D. should take place during the line return time, which is only 12 ps in the standard 625 lines. During the

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  reading time line, the charges injected into the C.C.D.

  are read in series and re-injection of the charges into the semiconductor substrate. On the other hand, an advantage of this device with respect to C.I.D. classics is that the reading of the charges is only done

  more on a strong capacity and no longer depends on the number of lines.

  The present invention relates to a photosensitive device read by charge transfer which has great advantages by

compared to known devices.

  The device according to the present invention comprises:

  - n lines of m photosensitive points, each point

  sensitive being constituted by the integration on a semi-

  conductor with a capacitance MOS C0, comprising a gate G0 common to the points of the same line, and a reading diode DI, separated from the gate G0 by a screen gate G1 brought to a potential

  constant (V1), m metallic connections (CI ... Cm) connecting in parallel

  lele n diodes belonging to different lines;

  - m diodes D2, integrated on the same semi-con-

  ductor, which end the m metal connections, these diodes being followed by a gate G2 brought to a constant potential (v2); means for discharging on a diode (D5) the charges accumulated on the diodes D1 and D2 during each time interval where none of the gates Go are at zero; at least one shift register (R1) which enables the setting

  periodic zero of each grid G0 and the evacuation of charges

  signal on the diodes D1 then on the diodes D2; means for transferring the signal charges arriving under the diodes D2 into a charge transfer reading register

  (R2) with m parallel inputs and serial output.

  According to a preferred embodiment, the device according to

  the invention comprises an integrated memory on the semi-

  conductor following the D2 diodes and under which the

  signal are collected before being transferred to the register of

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reading (R2).

  Among the main advantages of the device according to the invention, mention may be made of: the fact that, at the same time as the reading of the signal charges, they are evacuated from the photosensitive zone of the device by transfer of these charges from the diodes of the reading D1 to diodes D through metal connections C ilCn * No longer necessary as in the case of CID devices in the case of the C.I.D. I.E.E.E. cited to re-inject the charges into the substrate. - likewise, the fact that the reading diodes D1 fill

  also a function commonly called "anti-blocking"

  oming "(anti-glare).

  sensitive is too intensely lit, the charge storage capacity C% for this point overflows in the adjacent diode D1. Between two readings of a line (step T2), the charges which have overflowed in the diodes J D1 are discharged (step T1). In addition, n diodes D1 are connected in parallel by each connection C., the charges due to too intense illumination can therefore be distributed on these n diodes before overflowing in the substrate; The diodes D1 which ensure both the evacuation of the charges of the photosensitive part and the

  anti-blooming function make it possible to avoid the use of

  horizontal collector fusions and vertical electrodes for isolating cells from each other as is generally the case in C.I.D. (see the "guard stripes" and "field shield electrodes" in figures 2, 3 and 4 of the document I.E.E.E. cited as well as the commentary of these figures);

  the fact that the device according to the invention generally comprises

  memory where the charges corresponding to the reading of a line of photosensitive points are stored temporarily before being transferred into the memory register.

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  charge transfer reading. In the device according to the invention

  tion, as in the one described by LE.E.E., the transfer of charges from each line to the

  reading is of the "Bucket Brigade" type. The addition of a

  memory allows a time equal to that of a line reading (ie 52 ps for the TV standard 625 lines) to perform the evacuation of parasitic loads on the diodes D1 and D2 and the transfer of a line in memory while in the device described by the article of the EEA, these times were reduced to that of the

return line (12 ips).

  Other objects, features and results of the invention

  will emerge from the following description given as an example

  limiting and illustrated by the accompanying figures which show: - Figure 1, a schematic top view of an embodiment of the device according to the invention; - Figure 2a, a longitudinal sectional view of the device shown in Figure 1 and Figures 2b to 2g diagrams illustrating the operation of this device; - Figure 3, a schematic representation seen from above of another embodiment of the photosensitive area of the device according to the invention; FIG. 4, control signals that can be applied to the device according to the invention; FIG. 5 is a diagrammatic representation, seen from above, of an embodiment of a device for injecting an additional quantity of charges Q0 into the photosensitive device according to the invention; FIG. 6a, a sectional view of the device represented on FIG.

  FIG. 5, and FIGS. 6b to 6e, diagrams illustrating the function

  do not lie of this device; FIG. 7, a schematic representation seen from above

  another embodiment of the memory, the evaluation device

  cuation parasitic charges and the read register of the photosensitive device according to the invention;

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  FIGS. 8a and 9a, two cross-sectional views of the embodiment shown in FIG. 7 and FIGS. 8b, 8c and 9b,

  9c, diagrams illustrating the functioning of this mode of

  lisation; FIGS. 10a to 10d, control signals capable of

  to be applied to the device according to the invention.

  In the different figures, the same references designate the same elements, but, for the sake of clarity, the dimensions and

  proportions of the various elements are not respected.

  In Figure 1, there is shown schematically from above an embodiment of the device according to the invention. FIG. 2a shows, in longitudinal section, the device represented

in Figure 1.

  The photosensitive device according to the invention comprises substantially

  three parts: - a photosensitive zone 1; a memory and a device for evacuating parasitic charges, this part being marked with 2;

- a reading register 3.

  We will successively describe each of these parts and explain

  how they are connected to each other.

  The photosensitive zone 1 comprises a matrix of photosensitive points. In Figure 1, this matrix comprises four

  lines and four columns, and therefore 16 photosensitive points.

  Each photosensitive point is constituted by the integration on a semiconductor substrate 4, which is generally silicon:

  an MOS capacitor C0 constituted by a gate G0,

  zontal and common to the points of the same line. On each gate Go, vertical isolation diffusions dl determine the capacitance C0 of each photosensitive point; a collector diode D1o which is sensitive to the short wavelengths at which the gates G0 are opaque. The diodes D1o are scattered locally near the gates Go. The diodes D1 are arranged in a matrix. In Figure 1, each line of

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  diodes D is disposed at the edge of one of the long sides of one of the grids Go which are rectangular; a screen gate G, which is brought to a constant potential V1. In FIG. 1, the gate G1 is horizontal and common to all the photosensitive points of the same line. Like the grid G0, the gate G is rectangular and borders the other large side of Go which is not occupied by the diodes D - of a reading diode D1. The reading diodes Di are arranged in matrix and four vertical metal connections, C1 to C4, which are generally made of aluminum, connect in parallel

  the four reading diodes D of the same column.

  The collecting diodes D must be strongly coupled to the gates G0 by significant CB edge capacitances.

  to the capacitors, CD, DIO diodes to the semiconductor substrate.

  4. Must have: CB> C01. For this purpose, the common perimeter between each diode D10 and the neighboring gate Go is maximized. Thus the potential of diodes D0o follows exatement the

  surface potential under the neighboring gate G0.

  It can be noted that diodes D10 could also be

  placed between the grids G0 and G1.

  Grids G0 receive two kinds of polarization: on the one hand, all grids G0 of the photosensitive zone are subjected to a constant potential V9 which allows the integration of the charges at each photosensitive point as a function of the illumination received by this region. point. Each gate G0 is connected to one of the electrodes of a MOS transistor T1 to T 4, the other electrode of which is connected to the DC voltage V9 and whose gate receives a potential V8 which makes it possible to restore the potential V9 on all the Go0 grids The V8 potential may be a DC or variable voltage depending

  In the case where V8 is a DC voltage, the reinstatement

  V9 potential on the Go grid which was previously zero is done with a relatively long time constant and the value of the C0 charge storage capacity increases with

  the weather. This reduces the amount of charges collected per generation.

  thermal ration. In the case where the potential V8 is a variable signal as a function of time, it is generally the passage of. V8 at the high level which causes the conduction of transistors T1 to T4 and the instantaneous recovery of the potential V9 on all the gates Go, on the other hand, each gate G0 periodically receives a zero potential which causes the transfer of the signal charges stored under this grid under the diodes D1, while the other gates Go are maintained at the potential V9 and integration charges continues under these grids. To periodically zero one of the gates Go, each gate G0 is connected to one of the electrodes of a MOS transistor T01 to T04 whose other electrode is connected to ground and whose gate receives control signals L1 to L4 from four successive stages of a shift register R1. The passage of a control signal Li at the high level causes the zeroing

from one of the grids G0.

  We will now examine the memory and the evaluation device

  cuation parasitic charges 2 which are generally integrated on the same semiconductor substrate 4 as that on which is integrated l! photosensitive zone 1. The connection between the parts 1 and 2 of the photosensitive device according to the invention is provided by four diodes D2 which are integrated on the semiconductor substrate 4 and which terminate the metal connections C1 to C4. The diodes D2 are followed by a grid G2, horizontal and common to all the diodes which is brought to a constant potential V2. The gate G2 sets at V2 - VT the potential on the diodes D2 and on the diodes of

  reading Di connected to the diodes D2, VT representing the voltage of.

threshold under the G2 grid.

  The gate G2 which is connected to the constant potential V2, like the gates G1 connected to the constant potential V1 make it possible to avoid the sending of parasites on the connections C1 to C4, which would have the effect of introducing into the memory parasitic charges superimposed on the signal charges. In charge transfer devices, it is

  particularly important to protect against

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  sites whose amplitude may vary from one point to another of the circuit according to

  the geometric variations of the elements and which limit the dynamic

signal.

  In addition, the gates G1 isolate the photosensitive zone l parasites from the connections Ci and the part 2 of the device and, similarly, the gate G2 isolates the part 2 parasites from

connections C and part 1.

  The grid G2 is followed by a grid G3, which like G2 is horizontal and unique. The gate G3 is controlled by a periodic signal V3. The passage of V3 from a high level to a low level makes it possible to avoid the backtracking of the charges transferred from the

diodes D1 and D2 to the memory.

  The memory is constituted by four diodes D4 which are aligned and which are followed by a single horizontal gate G4 which is brought to a variable potential V4. In this memory, two types of charges are successively stored: on the one hand, the parasitic charges accumulated under the diodes Di and D2 during each time interval where none of the gates G0 are at zero; - on the other hand, the signal charges from zeroing

a grid G0.

  The memory is followed by a parasitic charge evacuation device which consists of a single horizontal G5 gate followed by a single diode D5, the gate G5 and the diode D5.

  being connected to a variable potential V5.

  On the semiconductor substrate 4, isolation diffusions d delimit in a known manner the area of the substrate which is reserved for the treatment of the charges coming from each column of photosensitive points and isolates the diodes D2 from the diodes DI '. third part of the device

  photosensitive according to the invention, that is to say the read register 3.

  The reading register 3 is generally integrated on the same

  semiconductor substrate 4 that the memory and the evaluation device

  cuation parasitic charges 2, but it is isolated by a

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  d3 isolation diffusion zone in slots.

  Inside the slots, there are four diodes D6 which are aligned and which are connected by metal connections C'I to C'4 to the four diodes D4 of the memory. This is done by transferring the signal charges from the memory to the read register. The diodes D6 are followed by a grid G6, which is horizontal and unique and which is connected to the same variable potential V4 as the grid

G4 of memory.

  The grid G6 is followed by a grid G7, which is also horizontal and unique and which is connected to a variable potential V7 and which makes it possible, when it passes to the high level, the transfer of

  signal charges to the actual read register R2.

  In FIG. 1, the reading register R2 is a C.C.D. two phases 01 and 02. This register comprises a succession of storage electrodes and charge transfer electrodes which

  are arranged on an extra thickness of insulation with respect to electri-

  storage trodes. One out of two storage electrodes leads to the lower end of the d3 isolation diffusion zone and therefore does not receive charges. The transfer of the charges in the register R2 takes place horizontally as indicated by an arrow in FIG. 1. The reading of the signal charges of a line

  of photosensitive element is therefore carried out in series.

  An isolation diffusion d4 determines the lower limit of the

  load transfer channel in the RT2 register.

  It is because of the presence of the parasitic charge evacuation device that the connection between the memory and the read register 3 must be made by external connections to the substrate C'1 to C'4. As in the case of diodes Dl. and of the gate Go, it is necessary that a good coupling exists between the diodes D4 and the

  gate G4 as well as between diodes D6 and gate G6.

  It can then be covered by an insulating layer, then by a

  aluminum layer each diode and a part of the neighboring grid.

  We then take electrical contact through the insulation at the level

of each grid.

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  The previous description was placed in the case of a

  matrix with four lines and four photosensitive columns,

  it is obvious that this description applies to the case where the

  matrix has n lines of m photosensitive dots, o n and mr

are positive integers.

  We will now explain the operation of the device according to the invention shown in Figures 1 and 2a by describing Figures 2b to 2g. Figures 2b to 2g show the evolution of the surface potential OS in the semiconductor substrate 4 at various times t1 to t6. The hatched areas indicate the presence of minority carriers. In FIGS. 2b to 2g, only the interface 5 and 7 of the substrate 4 and of the insulating layer which covers them are shown. The times t1 to t6 are indicated in FIGS. 4a to 4f, which represent the control signals that can be applied to the device according to the invention. These control signals are periodic signals whose amplitude varies between a low level and a

high level.

  In FIGS. 4a and 4b, the signals V4 and V3 of the same period T are represented. The signal V3 returns to the low level for a moment?

very short before V4.

  FIGS. 4c and 4d show the signals V5 and V7 of the same period T. The signals V5 and V7 are in phase opposition with V3. In FIGS. 4e and 4f, the signals Li and Li + 1 are represented. These signals have the same period nT. They go to

  high level one moment Y; very short after the passage of V3 level.

  high and return to the low level at the same time as V3.

  The operation of the device according to the invention comprises the repetition of two distinct stages of durations T1 and T2 which we will hereinafter denote by "step T" I and "step T2Y1, the sum of T1 and T2 being equal to T. of step T1, all the gates Go are brought to the potential V 9. The parasitic charges which are on all the diodes D and D of the device are then removed to the memory and

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  then to the device for discharging parasitic charges.

  During step T2, only one of the grids G0 of the photosensitive zone is at potential 0, while the other grids G0 are at potential V9. The signal charges stored under the gate at the potential 0 are transferred to the diodes D1 and D2 and then to the memory before being transferred to the reading register.

  R2 where they will be read during the next T1 step.

  We will now study in detail each of the steps T1 and T2. Step T1:

  at time t1, only the signals V3 and V4 are at the high level.

  All the gates Go are at potential V9 and integration of charges continues in each capacitor C. and on each diode D10. The parasitic loads picked up by the diodes D1 and D2 of the entire device are discharged into the memory as allowed by the gate G3 which is at the high level. These parasitic charges come from

  essentially an overflow of C0 capacity due to

  too intense: this is the anti-blooming function of diodes D1.

  The parasitic charges may also be charges collected laterally by the diodes D1 and D2; at time t2, signal V3 returns to zero and gate G3 then isolates the memory from the photosensitive zone. At time t2 also, the signal V5 goes high, the gate G5 and the diode D5 are ready to receive the parasitic charges; at time t2, the signal V4 returns to zero and the parasitic charges which were distributed evenly under the diodes D4y the gates G4, the diodes D6 and the gates G6 are evacuated under the evacuation diode D5 at the time t3 , -new, as at time t1, only the

  V3 and V4 signals are high, this is the end of step T1.

  Step T2: at time t4, the signals V3, V4 and Li are at the high level. The gate G0 of the photosensitive zone which is connected to the MOS transistor T0, controlled by the signal Li, is then connected to zero.

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  then transferring the signal charges stored by all the photosensitive points under this gate Go on the diodes D 1 and D 2 and then in the memory. As in the case of the evacuation of the parasitic charges, the transfer of the charges in memory is done at a constant potential V2 - VT thanks to the gate G2. It has already been seen that the transfer of the charges into memory whether they are the parasitic charges or the signal charges is of the Bucket-Brigade type, that is to say that it is done via the analog a

  saturation biased MOS transistor whose source would be

  staggered by the diodes D1 and D2, whose gate would be constituted by the gate G2 carried at the constant potential V2 and whose drain would be constituted by the diode D4 carried by the gate G4 at a potential V4 greater than V3. We have seen that to be effective this type of transfer takes a relatively long time. In the device according to the invention, the existence of the memory makes it possible to have a time equal to that of a line reading in order to carry out the evacuation of the parasitic charges on all the diodes D1 and D2 and the transfer of a Li line in memory; in fact, during this time, the register R2 ensures the reading of a previous line Li 1 of the matrix; - At time t5 - Y, the transfer of the signal charges in memory being completed the signals V3 and Li go low while the signal V7 goes high. The gate G3 again isolates the connections Ci from the memory. The gate G7 is raised to the high level and opens the gateway to the read register R22; at time 5, the signal V4 goes low and there is then transfer of the signal charges which have been distributed under the diodes D4, D6 and the gates G4 and G6 in the reading register R2. The

  transfer of the signal charges to the reading register must be

  perform during the line return time, however all previous steps from t1 to t5 -bise occur during the line read time. After the time t5, the signal V0 restores the potential Vs on the gate Go whose content has just been transferred into the reading register; in the case where the signal V9 is a periodic signal, it may be identical to the signal V7;

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  at time t6, the control signals resume their value of time t1. A new step T1 begins while the line Li is read by the register R2, this reading is prolonged during the step T2 where the content of the following line L. is transferred into memory and ends at the next time t5 -Z. The photosensitive device according to the invention can receive the light radiation to be detected either by its front face where are the gates Go and G1, or by its rear face. In the case where the light radiation is sent on the front face of the device, the grids G0 must be photosensitive; they are then consis-

  stained with polycrystalline silicon or semi-transparent metal. The reading diodes D1 are then completely covered with an insulating layer, then with aluminum in order to avoid parasitic illumination. Similarly, the memory, the parasitic charge evacuation device and the reading register are covered with an opaque layer which protects them from light radiation, and which may be a metallization. In the case where the light radiation is sent on the rear face of the photosensitive device, the semiconductor substrate 4 which carries the photosensitive zone 1 then has a reduced thickness. The metal connections C1 to C4 make it possible to dispose the memory, the parasitic charge evacuation device and the reading register at a certain distance from the photosensitive zone and on a part of the substrate 4 whose thickness has not

  been reduced. This avoids parasitic illumination of these elements.

  FIG. 3 relates to a schematic representation seen from above of another embodiment of the photosensitive zone 1 of the

device according to the invention.

  In this embodiment, the photosensitive spots are

  organized in a staggered line from one line to another.

  Go grids which consist of a first level of polycrystalline silicon are arranged horizontally.These grids have

  a rectangular shape and have indentations,

  also gulars. In each indentation there is a reading diode D1. The reading diodes D1 are arranged in staggered rows

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  because the indentations are shifted half a step from one Go grid to the next. On each grid Go there is between two notches an opening which constitutes a collecting zone D ^ O In the case of Figure 3 o the collector zones D10 are constituted by a simple thin oxide zone without diffusion and no longer by diodes as in the case of FIG. 1, the carriers created by the photons under these collector zones join the capacitors C0, created by the G0 grids, by simple diffusion rather than by conduction. In the case of FIG. 3, each gate G0 receives the carriers generated on each collector zone D1 (all around this collector zone.) The replacement of the diodes by a single layer of thin oxide to constitute the collector zones is interesting.

  in the case where the condition: CB "> CD10 can not be realized.

  In this embodiment, the grids G1 consist of a second level of polycrystalline silicon. These grids are vertical. Each grid G1 partly covers on the one hand one of the vertical edges of an indentation made on each gate Go and

  on the other hand the reading diode D1 found in this sample.

  mandibular notch. The reading diodes D1 are thus situated alternately, from one line to the other, to the right and to the left of the vertical electrode G1. On grids G1, isolated by a thick oxide layer, the aluminum connections Ci are found. In FIG. 3, the connections C1, C2, C3 are represented in broken lines. These connections address the reading diodes D10 by making contacts at

through the oxide layer.

  The advantages of the arrangement of the photosensitive points staggered, and no longer matrix, are as follows:

  - the horizontal resolution of the photosensitive spots is increased

  mented; the connections Ci are totally protected from any parasite by the gates G1 brought to the constant potential VI; - moreover, the interval between the grids realized on the same

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  polycrystalline silicon level is not critical. Indeed, the shortcircuit of two grids G0 affects only two lines of the photosensitive area. For the first line, the read signal is the sum of the signals of the two lines. The second line is read as a line

  black because it was emptied by the previous reading. Finally a short

  circuit on the gates G1 has no effect- on the operation of the device. The pitch of the shift register R1 which is used for the periodic zeroing of each gate G0 is generally larger than the pitch of the gates G0. Two registers R1 and R'1 can be used whose pitch is double that of the gates G0. The registers are then placed on either side of the photosensitive zone. One of the registers addresses the even-numbered G0 grids and the other addresses the odd-numbered Go grids. Interlacing is facilitated by this organization that can be used in conjunction with the staggered arrangement. So one of the registers can address. the grids G0 of odd rank and the photosensitive points placed to the right of the connections Ci, then, the other

  register addresses the even rank G0 grids and the photo-points

  Sensitive placed to the left of the connections Ci.

  We have seen in the description of the operation of the device

  shown in Figure 1 that this operation included the repetition of two steps T1 and T2. The anti-blooming function is only performed during the steps T1. Surplus charges due to photosensitive spots that are too intensely lit and that overflow on their reading diode D are taken into account during the steps

  T2. Surplus charges due to a photosensitive dot too much.

  intensely lit are distributed over all the LEDs

  which are connected to the read diode Di of this point too intensely

  The average level of the signal on this connection Ci is thus high. If this

  point is illuminated with an intensity B times greater than that which.

  produces the quantity of charges, Q maximum at a photosensitive point, the average level for the diodes connected to the connection C. is high in the quantity:

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  B T1i o N represents the number of GO grids in the zone

N 'T-'QI'

  I. Thus a photosensitive zone which has 500 grids GB and for which T1 = T2, can tolerate an over-light B of

the order of 1000.

  It is advantageous to improve the resistance of the device to over-illumination by increasing the duration of step T2 relative to

that of step T1.

  The time T2 is limited by the time required for the transfer of the signal charges QS along each connection Ci to the memory. We have seen that this transfer takes place

  through the equivalent of a saturation MOS transistor.

  If we call ci the capacity of the connection Ci, the residual charge Qr under the reading diodes D1 connected by Ci is expressed: = Q5 T, with B '= W' Co Qr QSE 'Cx

1 + B T

  c. where COx is the capacity of the grid G2 per unit area, W the width of this grid, L its length and / the mobility of the carriers

minority of the substrate.

  So we see that to reduce the residual load we have

  advantage to decrease the capacity ci.

  It also appears that QS signal charges of low values

  are less well transmitted than higher value loads.

  The sensitivity of the device is therefore lower for low light levels. The transfer of the small quantities of signal charges QS can be significantly improved by superimposing on them a fixed charge Q0 obtained by increasing the potential of the gate G2 at time t4 by A V. In this case the transferred load is written: Q5 + QO with QO = ci. a V. At the output of the reading register R2, a signal superimposed on a load base Q0 is obtained which also facilitates the

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  transfer of charges into the register.

  The disadvantage of this method may be in certain cases to add to the signal a noise d to the variations of the capacitance ci of a connection C. to the other which- introduce variations on the quantity Q 0 introduced from a column to the other.

  Figures 5 and 6a relate to a schematic representation of

  view from above and longitudinal sectional view of an embodiment of a device for injecting a quantity of charges

  additional Q0 in the photosensitive device according to the invention.

  With this device the quantities of injected charges Q0 are

  identical for all points in the photosensitive and inde-

  pending values of the capacitances ci of the connections Ci.

This device consists of the integration on a semiconductor substrate (which may be the same as that on which the rest of the photosensitive device is integrated) of a number of diodes D7 equal to the number of connections Ci. In FIG. four diodes D7 are shown. These diodes are brought to a potential

  variable V7. Two coplanar grids G8 and Gg follow these diodes.

  These grids are brought to two constant potentials V8 and Vq, with V8 less than V9. Thus the passage of diodes D7 from a low level to a high level makes it possible to store, under G9, a quantity of charges Q0 such that: Q0 (V9 - Va). CG, where CG represents the storage capacity under the grid. 9

  Thus the quantity of charges Qo stored under Ggest inde-

  the threshold voltage variations under G8 and G9 from one photosensitive point to the other and depends only on the geometry of G9, the variation of which from one end to the other of the device can be reduced to

second order.

  Vertical isolation diffusions d4 delimit in a known manner the area of the substrate which is reserved for the treatment of charges originating from a single diode D. FIGS. 6b to 6e show diagrams illustrating the operation of the device represented in FIGS. 1a to

  times t4, t2 t3 and again t4.

  In these figures, only the interface 9 of the substrate

  8 and the insulating layer which covers it.

  Figures 6b and 6c show the storage of the

  quantity of charges Q0 under the gate Gg.

  The gate G9 is followed by a gate G1l and an electrode of

  G12 storage which are brought to a variable potential V11.

  At time t3, each quantity of charges Q0 is transferred from

G9 under G12.

  The gate G12 is followed by a screen gate G13 brought to a constant potential V13. After the gate G13, there are four diodes D13 which are connected by metal connections C "I to C" 4

to the diodes D1 and D2.

  At time t4, the potential V1 goes to zero and causes the transfer of each quantity of charges Q0 under the diodes D13, D1 and D connected in parallel. The charge Q0 is therefore introduced at the same time t4 as the signal charge QS of the line read. The generation of Q0 is done by reading each line of elements

photosensitive.

  The geometry of the memory and the read register must be provided so that the total charge equal to: Q0 + Q can be stored, where Q is the maximum signal charge at a photosensitive dot. Another embodiment of the memory, the device for evacuating parasitic charges and the reading register of the photosensitive device according to the invention, that is to say parts of this device which are marked by 2 and 3

in Figure 1.

  In this embodiment, it was desired to transfer the signal chargers from the memory to the reading register R2 without using diodes such as diodes D and D6 which are connected in pairs by external metal connections to the substrate C'1 to C14. . This embodiment thus has the advantage over that shown in FIG. 1 of eliminating the parasites that can be introduced by a variable coupling, from one photosensitive point to the other between, on the one hand, each diode D4 or D6 and the adjacent gate G4 or G6 and secondly between each pair of diodes D and D6

(C 'connection) ..

  It was also desired in this embodiment to obtain a better homogeneity over the width. of the gate G2 brought to the constant potential V2 which follows the diodes D2; we also wanted

  to be able to make this width much smaller.

  Thus, this embodiment has the advantage of eliminating the parasites that can be introduced by a variable penetration of a photosensitive point to the other of the diodes D2 under the gate G2; this variable penetration can lead to transfer times

  variables of the signal charges of each diode D to the memory in.

  because of the variable width of the gate of the equivalent MOS transistor through which the charges are transferred in memory; in addition, this embodiment has the advantage of increasing the transfer speed of the signal charges of and D2 in memory, to

  because of the decrease in the width of G2.

  Finally, this embodiment has the advantage of simplifying

the control signals.

  In counterpart of these advantages, this embodiment imposes manufacturing constraints a little more severe with regard to

  the dimensions of the different elements.

  FIG. 7 relates to a schematic representation of

above this embodiment.

  Figures Sa and 9a show cross sectional views of

  of the embodiment shown in FIG. 7.

  After the diodes D2 connected by the connections C1 to C4 to the reading diodes DI, there is the gate G2 carried at the constant potential V. The gate G2 is surrounded by two coplanar gates G14 and G4 which are maintained at a constant potential V'4 greater than V2. So

248 1-553

  the width ú of the gate G2 is determined in a single photogravure operation by the interval between the gates G14 and G4. Thus we obtain a better homogeneity on the width ú which can, by

  elsewhere, be made much smaller.

  The grid G4, like the gates Go of FIG. 3, is a grid

  rectangular with rectangular indentations as well.

  Fig. 8a is a cross-sectional view of the embodiment shown in Fig. 7 in a narrow area.

  of G4, that is to say at a notch.

  Fig. 9a is a cross-sectional view of the embodiment shown in Fig. 7 in the gap between two indentations. In each part of the substrate placed under a notch of

  G4, there is a D5 evacuation diode.

  A "U" Isolation Diffusion Zone d5 surrounds each

diode D5.

  This isolation diffusion zone determines two channels on each part of the substrate 4 reserved by the diffusion zone d2 for the treatment of the charges coming from one of the connections C1 to Cm: the channel 1, (FIG. 9a), which leads reading register R2; this access being regulated by a gate G7, brought to a variable potential V'7 and which straddles the end of G4 and the beginning of R2; - Channel 2, (Figure 8a), which leads to the evacuation diode D5. Each diode D5 is then common at two memory points

  adjacent to save space.

  Access to diode D5 is then regulated by an electrode

  rectangular G15 raised to a variable potential V15. This election

  trode straddles the horizontal part of the G4 indentations. It is separated from G4 by a non-oxide layer

  represented. Potential V15 is also applied to D5 diodes.

  FIGS. 8a and 9a represent cross-sectional views along the channels 2 and I,

248 1553

  We will now examine the operation of this mode of

  with reference to FIGS. 8b, 8c and 9b, 9c which

  feel the evolution of the surface potential in the semi-

  conduct 4a at different times t'1, t'2, t'3.

  These instants are marked in FIGS. 10a to 10d, which represent the control signals that can be applied.

in this embodiment.

  FIGS. 10c and 10d show the signals Li and Li + 1

  already shown in Figures 4e and 4f.

  FIGS. 10a and 10b show the signals V15 and V17. These signals are periodic of period T and vary between

low level and a high level.

  The signal V15 is at the high level when the signals Lp,

  Li + - and the signal V'7 are low.

  The signals L, Li +. go high a momentZ * after V15 has gone low. The signal V'7 goes to the level

  high a moment T; after the passage of Li, Li + 1 ... at low level.

  Finally, the signal V'7 returns to the low level for a moment ?: before the

passage from V15 to high level.

  Stage T1 takes place from the moment V15 is at the level

  up until the moment when Li, Li + 1 ... pass to the high level.

  Stage T2 takes place during the remainder of period T.

  We will examine steps T1 and T2.

Step T1:

  at time t'1, only the signal V15 is at the high level.

  Figure 8b shows the surface potentials at this time

  the. The parasitic charges of all the photosensitive points are discharged from the diodes Di to the diodes D21 then under the gate G4 and finally under a discharge diode D. The transfer is at the constant potential V2 - VT through the gate G2; Step T2: at time t'2, only the signal Li is at the high level. The

248-1553

  Figures 8c and 9b show the surface potentials in the substrate at that time. The signal charges of the line Li are then transferred from the diodes D1 to the diodes D2 and then

  stored under the G4 grid that serves as memory.

  at time t'3, only the signal V'7 is at the high level. Figure 9c shows the surface potential in the substrate at that time. There is then transfer of the signal charges of the line

  Li which are stored under G4 under the R2 read register.

  A new stage T1 then begins while the line Li

is read by register R2.

  If the reading register R2 is a register where the transfer of charges takes place in volume, there exists under the electrodes of the register a diffused zone z which can stop in the middle of the gate G7. In this case, the potential under register R2 is higher than

  - under G4 which facilitates the transfer of charges.

  The superposition of a fixed charge Q0 to the signal charges QS can be done in the two ways indicated above, that is to say: by increasing by A V the potential of G2 at the time t'2; or, using the device of FIGS. 5 and 6a to 6e. In this

  case, the step represented lafir -made at time t'2.

  It is understood that the present invention relates generally to

  a built-in photosensitive device on a semi-

  silicon conductor. It is also possible to report on a silicon substrate photosensitive detectors made of a material

different.

  The device according to the invention can also function as data

  results as satisfactory as those obtained by the

  described in Article I.E.E.E by transferring the charges

  signal as they arrive in the reading register

R2 without storing them in memory.

  Finally, the device according to the invention is preferably a CCD device, where the charge transfer takes place on the surface or in volume.

248 1553

Claims (19)

  1. A photosensitive device read by charge transfer, characterized in that it comprises:   n lines of m photosensitive points, each photosensitive point being constituted by the integration on a semiconductor substrate (4) of a capacitance MOS (C0) comprising a gate Go common to the points of the same line, and of a reading diode D1, separated from the gate Go by a screen gate G1 brought to a constant potential VI, m metal connections (CI ... Cm) connecting in parallel n diodes belonging to n different lines; - m diodes D2, integrated on the same semiconductor substrate, to which end the m metal connections, these diodes being followed by a gate G2 carried at a constant potential (V means of evacuation on a diode (D5) parasitic charges accumulated on the diodes D1 and D2 during each time interval o none of the gates Go is at zero, - at least one shift register (R1-), which allows the periodic zeroing of each gate G0 and the evacuation of the loads. signal on the diodes D1 then on the diodes D2; means ensuring the transfer of the signal charges arriving on the diodes D2 in a charge transfer reading register (R2) to   m parallel and serial output inputs.   2. Device according to claim 1, characterized in that it comprises a memory integrated on the semiconductor substrate at the   diodes D2 and under which the signal charges are collected.   before being transferred to the reading register (R2).   3. Device according to claim 2, characterized in that this memory is constituted by m diodes (D4) followed by a grid (G4) common to the m diodes and brought to a variable potential (Vy). 4. Device according to claim 3, characterized in that it comprises, integrated on the substrate following the memory, a gate G5 and a diode D5 connected to a variable potential (V5), the diode receiving parasitic loads. accumulated under diodes D1 and D2 248 1553   during the time interval o none of the light-sensitive grids Go is at zero.   5. Device according to claim 4, characterized in that it comprises, integrated on the semiconductor substrate (4): - M diodes D6 followed by a single gate G6, each of these diodes being connected by a metal connection (C 'IC') to the corresponding diode (D4) of the memory and the gate G6 being brought to the same variable potential (V4) as the gate (G4) of the memory; a single gate G7 brought to a variable potential (V7); the load transfer reading register (R2) whose previous gate G7 allows loading, after the signal charges resulting from the reading of a line have been collected by the memory. 6. Device according to Claim 5, characterized in that an oxide layer and an aluminum layer cover the diodes (D4) of the memory and the diodes D6 and a part of the neighboring grids (G4 and G6). , an electrical contact being established through the insulation at level of each grid.   7.Device according to one of Claims 2 to 6, characterized   a grid (G3) brought to a variable potential (V3) is inter-   stalled on the semiconductor substrate between the gate G2 carried to a   constant potential (V2) and memory.   & A device according to claim 2, characterized in that the gate G2 is surrounded by two coplanar grids set at a constant potential lower than V2, one of these gates (G14) being   adjacent to the diodes D2 and the other gate G4 constituting the memory.   9. Device according to claim 8, characterized in that: - the gate G4 is a rectangular grid having rectangular notches; each part of the substrate (4) placed under a notch comprises a charge evacuation diode (D5); a "U" isolation diffusion zone surrounds each charge evacuation diode (D5) and determines two channels on the part of the substrate dedicated to the treatment of the charges coming from 2,248,1553   one of the metal connections (C1 * Cm); - one of the channels (channel 2) which leads to an evacuation diode   (D5) allows the evacuation under the diode parasitic loads ac-   accumulated under the diodes D1 and D2 during the time interval o none of the photosensitive grids Go is at zero, this transfer being controlled by a grid (G15) placed astride the horizontal part of the indentations of G4; the other channel (channel 1) makes it possible to transfer the signal charges of a line stored under the gate G4 into the charge transfer reading register (R2), this transfer being controlled by a   grid (G7) straddling the end of G4 and the beginning of the register.   10. Device according to one of claims 1 to 9, characterized   in that each photosensitive point comprises, close to the gate (G.), a collector zone (D10) sensitive to the short wavelengths to which (Go) is not sensitive, the charges created by the radiation on these zones (Di .) being collected under the grids (GB). He. Device according to claim 10, characterized in that each collecting zone (Di.) is constituted by a diode or by a simple zone of thin oxide.   Device according to one of Claims 2 to 11, characterized   in that the constant potential (V2) applied to the gate G2 according to the diodes D2 is increased by a constant amount A V during the   transfer of the signal charges under the memory. -   13. Device according to one of claims 2 to 11, characterized   in that it includes, integrated on the same semiconductor substrate: - m diodes (D7) brought to a variable potential (V7) followed by; two coplanar grids G8 and Gg carried at two constant potentials V8 and V9, with V8 less than (Vy), so that a quantity of constant charges (Q) is stored under Gg during the passage of the potential applied to the diode from low level to high level: - a grid (G1U) and a storage electrode (G12) brought to a 248 1553   variable potential (V l) - a screen gate (G13) carried at a constant potential (V, 3) - m D13 diodes connected by metal connections (C "1.   C "M) to the diodes D2, the quantity of charges (Q0) being transferred under each diode D13 during the transfer of the signal charges under the memory ... CLMF: 14. Device according to one of claims 1 to 13, characterized   in that the portion of the semiconductor substrate (4) carrying the photosensitive area (1) has a reduced thickness and receives illumination by its back side.   15. Device according to one of claims 1 to 13, characterized   in that the portion of the semiconductor substrate (4) carrying the photosensitive area (1) receives illumination from its front face and that the grids (Go) are photosensitive and the readout diodes (D 1) are   completely covered with aluminum.-   Device according to one of Claims 1 to 15, characterized   in that the reading diodes (D) are arranged in staggered rows and are located in rectangular indentations made on the horizontal gates Go0 17. Device according to Claim 16, characterized in that it comprises m vertical gates G1 brought to the potential V1 which cover partly on the one hand, one of the vertical edges of each notch made on each gate Go and secondly, each reading diode D1 located alternately from one line to another to   right and left of the vertical electrode G1.   18. Device according to claim 17, characterized in that the vertical grids G1 are covered with an insulating layer on which are deposited the m metal connections (C1 to Cm) which connect in parallel through contacting through the insulating layer n read diodes D1 belonging to n grids GB different.   19. Device according to one of claims i to 15, characterized   in that the reading diodes D1 and the diodes D2 are arranged in matrix. 248 1553   20. Device according to one of claims 1 to 19, characterized   in that it comprises two shift registers which address one   rows of even rank and the other rows of odd rank.   21. Device according to one of claims 1 to 20, characterized   in that each gate G0 is connected to one of the electrodes of a MOS transistor (Toi ... Ton) whose gate is connected to a shift register (R1) and whose other electrode is connected to the ground, the shift register ensuring the periodical conduction of   each transistor and zeroing each gate Go0.   22. Device according to one of claims 1 to 21, characterized   in that each gate G0 is connected to one of the electrodes of a MOS transistor (Ti *** Tn) whose other electrode is connected to a constant potential (Vy) and whose gate receives a variable potential (Vs ), which causes the conduction of the transistors and the setting at the constant potential (Vy) of the gates Go after the transfer of the signal charges of a line in the charge transfer register (R2) has been performed.   23. Device according to one of claims 1 to 21, characterized   in that each gate G0 is connected to one of the electrodes of a MOS transistor (T il-T n) whose other electrode is connected to a constant potential (V9) and whose gate receives a constant potential, these transistors ensuring the recovery, after a constant time, of the constant potential (V9) under all the G0 grids after   the transfer of signal charges from one line to the trans-   charge (R2) has been made.   24. Device according to one of claims 1 to 23, characterized   in that the semiconductor substrate used is silicon.   25. Television camera, characterized in that it comprises   a device according to one of the preceding claims.