EP4174938A1 - Leadframe package with metal interposer - Google Patents

Leadframe package with metal interposer Download PDF

Info

Publication number
EP4174938A1
EP4174938A1 EP22199565.7A EP22199565A EP4174938A1 EP 4174938 A1 EP4174938 A1 EP 4174938A1 EP 22199565 A EP22199565 A EP 22199565A EP 4174938 A1 EP4174938 A1 EP 4174938A1
Authority
EP
European Patent Office
Prior art keywords
metal interposer
semiconductor package
die pad
package according
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22199565.7A
Other languages
German (de)
French (fr)
Inventor
Chu-Chia Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of EP4174938A1 publication Critical patent/EP4174938A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H01L2224/49052—Different loop heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/4909—Loop shape arrangement
    • H01L2224/49095—Loop shape arrangement parallel in plane
    • H01L2224/49096—Loop shape arrangement parallel in plane horizontal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/4909—Loop shape arrangement
    • H01L2224/49095—Loop shape arrangement parallel in plane
    • H01L2224/49097—Loop shape arrangement parallel in plane vertical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present disclosure relates generally to the field of semiconductor packaging. More particularly, the present disclosure relates to a leadframe package with a metal interposer.
  • FIG. 1 is a schematic diagram showing a typical layout of a leadframe package.
  • FIG. 2 is a schematic, cross-sectional view taken along line I-I' in FIG. 1 .
  • the leadframe package 1 has a rectangular shape when viewed from the above and has four sides S1-S4.
  • a semiconductor die D is mounted on a die pad P of a leadframe LF and is encapsulated by using a molding compound M.
  • 48 pins may be provided along the four sides S1-S4.
  • On each side, at least one pin is designated to provide the same function or signal such as digital power to avoid issues such as IR drop.
  • the pins with same function are denoted as pin No. 6, pin No. 15, pin No.
  • Bond wires W6, W15, W22, W31, W41, and W45 are respectively connected to the pin No. 6, pin No. 15, pin No. 22, pin No. 31, pin No. 41, and pin No. 45.
  • Other bond wires are omitted for the sake of simplicity.
  • the leadframe package 1 requires multiple bond wires for bonding with multiple pins with same function, which inevitably increase the package cost and customer PCB area. It is desirable to provide a leadframe with reduced pin count along the four sides of the leadframe package without affecting the functionality of the device.
  • One object of the present invention is to provide an improved leadframe package having a metal interposer in order to solve the above-mentioned problems or shortcomings.
  • a semiconductor package according to the invention is defined in independent claim 1.
  • the dependent claims define preferred embodiments thereof.
  • One aspect of the invention provides a semiconductor package including a leadframe comprising a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer.
  • a plurality of bond wires with same function is bonded to the metal interposer.
  • the metal interposer is attached to the top surface of the die pad with a first nonconductive adhesive film, and wherein the semiconductor die is attached to the top surface of the metal interposer with a second nonconductive adhesive film.
  • the first nonconductive adhesive film and the second nonconductive adhesive film comprise epoxy or polyimide.
  • the metal interposer is a monolithic and continuous metal sheet.
  • connection bond wire is disposed to electrically connect the metal interposed with a signal pin that provides the plurality of bond wires with same functional signal.
  • the same functional signal provided by the signal pin comprises digital power.
  • the metal interposer, the semiconductor die and the plurality of bond wires with same function are encapsulated by a molding compound.
  • the die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.
  • the metal interposer has a surface area that is smaller than that of the die pad such that a peripheral region of the die pad is spared for ground bond wires.
  • At least one opening penetrates through the metal interposer and the first nonconductive adhesive film, and at least one shorter ground bond wire is bonded to the die pad through the opening.
  • the metal interposer is a multi-piece metal interposer comprising physically separated sub-interposers that provides different function signals.
  • FIG. 3 is a schematic diagram showing an exemplary layout of a leadframe package 2 with a metal interposer IP according to an embodiment of the invention.
  • FIG. 4 is a schematic, cross-sectional view taken along line II-II' in FIG. 3 .
  • the leadframe package 2 may have a rectangular shape when viewed from the above and may have four sides S1-S4.
  • a semiconductor die D may be mounted on a die pad P of a leadframe LF and is encapsulated by using a molding compound M.
  • the space between the leads OL and the die pad P may be filled with the molding compound M.
  • a metal interposed IP that may be consisted of a monolithic and continuous metal sheet such as a monolithic copper or aluminum sheet or film is interposed between the die pad P and the semiconductor die D.
  • the metal interposed IP may be adhered to the top surface of the die pad P by using a nonconductive adhesive film AF1 such as epoxy, polyimide, or any suitable die attach films.
  • the semiconductor die D may be adhered to the top surface of the metal interposed IP by using a nonconductive adhesive film AF2 such as epoxy, polyimide, or any suitable die attach films.
  • the plurality of pins or leads OL such as a total of 48 pins may be provided along the four sides S1-S4.
  • the four rows of pins or leads OL may be separated by four tie bars TB disposed respectively at four corners of the leadframe package 2.
  • the 48 pins may be coplanar with the die pad P with their bottom surfaces exposed from the bottom surface of the molding compound M.
  • a plurality of input/output (I/O) pads such as six pads BP6, BP15, BP22, BP31, BP41, and BP45, which are used to bonded to respective pins such as pin No. 6, pin No. 15, pin No. 22, pin No. 31, pin No. 41, and pin No. 45 having the same function such as digital power on four sides S1-S4, are bonded to the metal interposed IP through shorter bond wires WS6, WS15, WS22, WS31, WS41, and WS45.
  • a connection bond wire WSC is provided to electrically connect the metal interposer IP with the exemplary pin No. 31 that provides the six pads BP6, BP15, BP22, BP31, BP41, and BP45 with same functional signal such as digital power.
  • the die pad P, the metal interposer IP and the semiconductor die D are stacked in layers so as to form a pyramidal stack structure. It is noteworthy that the metal interposer IP has a surface area that is smaller than that of the die pad P such that a peripheral region of the die pad P can be spared and used to bond the ground bond wires WSG.
  • the exemplary five pins including pin No. 6, pin No. 15, pin No. 22, pin No. 41, and pin No. 45 may be spared or canceled to reduce total pin count and the dimension of the leadframe package.
  • the spared five pins including pin No. 6, pin No. 15, pin No. 22, pin No. 41, and pin No. 45 may be designated for extra function signals.
  • FIG. 5 is a schematic, cross-sectional diagram showing another embodiment of the present invention.
  • the differences between the structure of the leadframe package 2a in FIG. 5 and the structure of the leadframe package 2 in FIG. 4 includes that the leadframe package 2a in FIG. 5 comprises at least one opening OG that penetrates through the metal interposer IP and the nonconductive adhesive film AF1. At least one shorter ground bond wire WSG is bonded to the die pad P through the opening OG.
  • the opening OG may be an elongated trench or slit disposed along at least one side of the metal interposer IP or may comprise individual holes.
  • FIG. 6 is a schematic, cross-sectional diagram showing still another embodiment of the present invention.
  • the differences between the structure of the leadframe package 2b in FIG. 6 and the structure of the leadframe package 2 in FIG. 4 includes that the leadframe package 2b in FIG. 6 comprises a multi-piece metal interposer such as two-piece metal interposer.
  • the metal interposer IP in FIG. 4 may be split into at least two physically separated sub-interposers IP1 and IP2, which provides different function signals such as different digital power signals.
  • a connection bond wire WSC1 and a connection bond wire WSC2 are provided to electrically connect the sub-interposers IP1 and IP2 to the respective pins or leads OL.
  • the bond wire WS6 may be electrically connected to the sub-interposer IP1 and the bond wire WS31 may be electrically connected to the other sub-interposer IP2.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor package includes a leadframe (LF) having a die pad (P) and a plurality of pins disposed around the die pad (P), a metal interposer (IP) attached to a top surface of the die pad (P), and a semiconductor die (D) attached to a top surface of the metal interposer (IP). A plurality of bond wires (WS6, WS31) with same function is bonded to the metal interposer (IP). The die pad (P), the metal interposer (IP) and the semiconductor die (D) are stacked in layers so as to form a pyramidal stack structure.

Description

    Cross Reference to Related Applications
  • This application claims the benefit of U.S. Provisional Application No. 63/273,169, filed on October 29th, 2021 . The content of the application is incorporated herein by reference.
    • Background
  • The present disclosure relates generally to the field of semiconductor packaging. More particularly, the present disclosure relates to a leadframe package with a metal interposer.
  • The handheld consumer market is aggressive in the miniaturization of electronic products. Driven primarily by the cellular phone and digital assistant markets, manufacturers of these devices are challenged by ever shrinking formats and the demand for more PC-like functionality. Additional functionality can only be achieved with higher performing logic IC's accompanied by increased memory capability. This challenge, combined together in a smaller PC board format, asserts pressure on surface mount component manufactures to design their products to command the smallest area possible.
  • Many of the components used extensively in today's handheld market are beginning to migrate from traditional leaded frame designs to non-leaded formats. The primary driver for handheld manufacturers is the saved PC board space created by these components' smaller mounting areas. In addition, most components also have reductions in weight and height, as well as an improved electrical performance. As critical chip scale packages are converted to non-leaded designs, the additional space saved can be allocated to new components for added device functionality. Since non-leaded designs can use many existing leadframe processes, costs to convert a production line can be minimized.
  • FIG. 1 is a schematic diagram showing a typical layout of a leadframe package. FIG. 2 is a schematic, cross-sectional view taken along line I-I' in FIG. 1. As shown in FIG. 1 and FIG. 2, the leadframe package 1 has a rectangular shape when viewed from the above and has four sides S1-S4. A semiconductor die D is mounted on a die pad P of a leadframe LF and is encapsulated by using a molding compound M. For example, 48 pins may be provided along the four sides S1-S4. On each side, at least one pin is designated to provide the same function or signal such as digital power to avoid issues such as IR drop. By way of example, the pins with same function are denoted as pin No. 6, pin No. 15, pin No. 22, pin No. 31, pin No. 41, and pin No. 45 in FIG. 1. Bond wires W6, W15, W22, W31, W41, and W45 are respectively connected to the pin No. 6, pin No. 15, pin No. 22, pin No. 31, pin No. 41, and pin No. 45. Other bond wires are omitted for the sake of simplicity.
  • The leadframe package 1 requires multiple bond wires for bonding with multiple pins with same function, which inevitably increase the package cost and customer PCB area. It is desirable to provide a leadframe with reduced pin count along the four sides of the leadframe package without affecting the functionality of the device.
    • Summary
  • One object of the present invention is to provide an improved leadframe package having a metal interposer in order to solve the above-mentioned problems or shortcomings. A semiconductor package according to the invention is defined in independent claim 1. The dependent claims define preferred embodiments thereof.
  • One aspect of the invention provides a semiconductor package including a leadframe comprising a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer.
  • Preferably, the metal interposer is attached to the top surface of the die pad with a first nonconductive adhesive film, and wherein the semiconductor die is attached to the top surface of the metal interposer with a second nonconductive adhesive film.
  • Preferably, the first nonconductive adhesive film and the second nonconductive adhesive film comprise epoxy or polyimide.
  • Preferably, the metal interposer is a monolithic and continuous metal sheet.
  • Preferably, a connection bond wire is disposed to electrically connect the metal interposed with a signal pin that provides the plurality of bond wires with same functional signal.
  • Preferably, the same functional signal provided by the signal pin comprises digital power.
  • Preferably, the metal interposer, the semiconductor die and the plurality of bond wires with same function are encapsulated by a molding compound.
  • Preferably, the die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.
  • Preferably, the metal interposer has a surface area that is smaller than that of the die pad such that a peripheral region of the die pad is spared for ground bond wires.
  • Preferably, at least one opening penetrates through the metal interposer and the first nonconductive adhesive film, and at least one shorter ground bond wire is bonded to the die pad through the opening.
  • Preferably, the metal interposer is a multi-piece metal interposer comprising physically separated sub-interposers that provides different function signals.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • Brief Description of the Drawings
  • The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
    • FIG. 1 is a schematic diagram showing a typical layout of a leadframe package;
    • FIG. 2 is a schematic, cross-sectional view taken along line I-I' in FIG. 1;
    • FIG. 3 is a schematic diagram showing an exemplary layout of a leadframe package with a metal interposer according to an embodiment of the invention;
    • FIG. 4 is a schematic, cross-sectional view taken along line II-II' in FIG. 3;
    • FIG. 5 is a schematic, cross-sectional diagram showing another embodiment of the present invention; and
    • FIG. 6 is a schematic, cross-sectional diagram showing still another embodiment of the present invention.
    Detailed Description
  • In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.
  • These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.
  • It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
  • Please refer to FIG. 3 and FIG. 4. FIG. 3 is a schematic diagram showing an exemplary layout of a leadframe package 2 with a metal interposer IP according to an embodiment of the invention. FIG. 4 is a schematic, cross-sectional view taken along line II-II' in FIG. 3. Like regions, layers or elements are designated with like numeral numbers or labels. As shown in FIG. 3 and FIG. 4, the leadframe package 2 may have a rectangular shape when viewed from the above and may have four sides S1-S4. A semiconductor die D may be mounted on a die pad P of a leadframe LF and is encapsulated by using a molding compound M. Preferably, the space between the leads OL and the die pad P may be filled with the molding compound M.
  • Preferably, a metal interposed IP that may be consisted of a monolithic and continuous metal sheet such as a monolithic copper or aluminum sheet or film is interposed between the die pad P and the semiconductor die D. Preferably, the metal interposed IP may be adhered to the top surface of the die pad P by using a nonconductive adhesive film AF1 such as epoxy, polyimide, or any suitable die attach films. Preferably, the semiconductor die D may be adhered to the top surface of the metal interposed IP by using a nonconductive adhesive film AF2 such as epoxy, polyimide, or any suitable die attach films.
  • Preferably, for example, the plurality of pins or leads OL such as a total of 48 pins may be provided along the four sides S1-S4. The four rows of pins or leads OL may be separated by four tie bars TB disposed respectively at four corners of the leadframe package 2. Preferably, the 48 pins may be coplanar with the die pad P with their bottom surfaces exposed from the bottom surface of the molding compound M. On the active surface of the semiconductor die D, a plurality of input/output (I/O) pads such as six pads BP6, BP15, BP22, BP31, BP41, and BP45, which are used to bonded to respective pins such as pin No. 6, pin No. 15, pin No. 22, pin No. 31, pin No. 41, and pin No. 45 having the same function such as digital power on four sides S1-S4, are bonded to the metal interposed IP through shorter bond wires WS6, WS15, WS22, WS31, WS41, and WS45.
  • A connection bond wire WSC is provided to electrically connect the metal interposer IP with the exemplary pin No. 31 that provides the six pads BP6, BP15, BP22, BP31, BP41, and BP45 with same functional signal such as digital power. The die pad P, the metal interposer IP and the semiconductor die D are stacked in layers so as to form a pyramidal stack structure. It is noteworthy that the metal interposer IP has a surface area that is smaller than that of the die pad P such that a peripheral region of the die pad P can be spared and used to bond the ground bond wires WSG.
  • Preferably, the exemplary five pins including pin No. 6, pin No. 15, pin No. 22, pin No. 41, and pin No. 45 may be spared or canceled to reduce total pin count and the dimension of the leadframe package. Alternatively preferably, the spared five pins including pin No. 6, pin No. 15, pin No. 22, pin No. 41, and pin No. 45 may be designated for extra function signals.
  • FIG. 5 is a schematic, cross-sectional diagram showing another embodiment of the present invention. As shown in FIG. 5, the differences between the structure of the leadframe package 2a in FIG. 5 and the structure of the leadframe package 2 in FIG. 4 includes that the leadframe package 2a in FIG. 5 comprises at least one opening OG that penetrates through the metal interposer IP and the nonconductive adhesive film AF1. At least one shorter ground bond wire WSG is bonded to the die pad P through the opening OG. By providing such configuration, a shorter ground signal path can be obtained and the performance of the leadframe package is improved. It is understood that the opening OG may be an elongated trench or slit disposed along at least one side of the metal interposer IP or may comprise individual holes.
  • FIG. 6 is a schematic, cross-sectional diagram showing still another embodiment of the present invention. As shown in FIG. 6, the differences between the structure of the leadframe package 2b in FIG. 6 and the structure of the leadframe package 2 in FIG. 4 includes that the leadframe package 2b in FIG. 6 comprises a multi-piece metal interposer such as two-piece metal interposer. Preferably, for example, the metal interposer IP in FIG. 4 may be split into at least two physically separated sub-interposers IP1 and IP2, which provides different function signals such as different digital power signals. A connection bond wire WSC1 and a connection bond wire WSC2 are provided to electrically connect the sub-interposers IP1 and IP2 to the respective pins or leads OL. For example, the bond wire WS6 may be electrically connected to the sub-interposer IP1 and the bond wire WS31 may be electrically connected to the other sub-interposer IP2.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (11)

  1. A semiconductor package, comprising:
    a leadframe (LF) comprising a die pad (P) and a plurality of pins (1 - 48) disposed around the die pad (P);
    a metal interposer (IP) attached to a top surface of the die pad (P); and
    a semiconductor die (D) attached to a top surface of the metal interposer (IP), wherein a plurality of bond wires (WS6, WS15, WS22, WS31, WS41, WS45) with same function is bonded to the metal interposer (IP).
  2. The semiconductor package according to claim 1, wherein the metal interposer (IP) is attached to the top surface of the die pad (P) with a first nonconductive adhesive film (AF1), and wherein the semiconductor die (D) is attached to the top surface of the metal interposer (IP) with a second nonconductive adhesive film (AF2).
  3. The semiconductor package according to claim 2, wherein the first nonconductive adhesive film (AF1) and the second nonconductive adhesive film (AF2) comprise epoxy or polyimide.
  4. The semiconductor package according to any one of claims 1 to 3, wherein the metal interposer (IP) is a monolithic and continuous metal sheet.
  5. The semiconductor package according to any one of claims 1 to 4, wherein a connection bond wire (WSC) is disposed to electrically connect the metal interposer (IP) with a signal pin (31) that provides the plurality of bond wires (WS6, WS15, WS22, WS31, WS41, WS45) with same functional signal.
  6. The semiconductor package according to claim 5, wherein the same functional signal provided by the signal pin (31) comprises digital power.
  7. The semiconductor package according to any one of claims 1 to 6, wherein the metal interposer (IP), the semiconductor die (D) and the plurality of bond wires (WS6, WS15, WS22, WS31, WS41, WS45) with same function are encapsulated by a molding compound (M).
  8. The semiconductor package according to any one of claims 1 to 7, wherein the die pad (P), the metal interposer (IP) and the semiconductor die (D) are stacked in layers so as to form a pyramidal stack structure.
  9. The semiconductor package according to any one of claims 1 to 8, wherein the metal interposer (IP) has a surface area that is smaller than that of the die pad (P) such that a peripheral region of the die pad (P) is spared for ground bond wires (WSG).
  10. The semiconductor package according to claim 2 or 3 or any one of claims 4 to 9 in combination with claim 2 or 3, wherein at least one opening (OG) penetrates through the metal interposer (IP) and the first nonconductive adhesive film (AF1), and at least one shorter ground bond wire (WSG) is bonded to the die pad (P) through the opening (OG).
  11. The semiconductor package according to any one of claims 1 to 10, wherein the metal interposer (IP) is a multi-piece metal interposer comprising physically separated sub-interposers (IP1, IP2) that provide different function signals.
EP22199565.7A 2021-10-29 2022-10-04 Leadframe package with metal interposer Pending EP4174938A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163273169P 2021-10-29 2021-10-29
US17/948,195 US20230134332A1 (en) 2021-10-29 2022-09-19 Leadframe package with metal interposer

Publications (1)

Publication Number Publication Date
EP4174938A1 true EP4174938A1 (en) 2023-05-03

Family

ID=83689711

Family Applications (1)

Application Number Title Priority Date Filing Date
EP22199565.7A Pending EP4174938A1 (en) 2021-10-29 2022-10-04 Leadframe package with metal interposer

Country Status (3)

Country Link
US (1) US20230134332A1 (en)
EP (1) EP4174938A1 (en)
TW (1) TW202318585A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220195A (en) * 1991-12-19 1993-06-15 Motorola, Inc. Semiconductor device having a multilayer leadframe with full power and ground planes
WO1993020586A1 (en) * 1992-03-31 1993-10-14 Vlsi Technology, Inc. Leadframe having one or more power/ground planes without vias
US20170047271A1 (en) * 2015-08-10 2017-02-16 Freescale Semiconductor, Inc. Method for making a semiconductor device having an interposer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220195A (en) * 1991-12-19 1993-06-15 Motorola, Inc. Semiconductor device having a multilayer leadframe with full power and ground planes
WO1993020586A1 (en) * 1992-03-31 1993-10-14 Vlsi Technology, Inc. Leadframe having one or more power/ground planes without vias
US20170047271A1 (en) * 2015-08-10 2017-02-16 Freescale Semiconductor, Inc. Method for making a semiconductor device having an interposer

Also Published As

Publication number Publication date
US20230134332A1 (en) 2023-05-04
TW202318585A (en) 2023-05-01

Similar Documents

Publication Publication Date Title
KR101070913B1 (en) Stacked die package
US6861288B2 (en) Stacked semiconductor packages and method for the fabrication thereof
US7700404B2 (en) Large die package structures and fabrication method therefor
US7205651B2 (en) Thermally enhanced stacked die package and fabrication method
US7582960B2 (en) Multiple chip package module including die stacked over encapsulated package
US5646831A (en) Electrically enhanced power quad flat pack arrangement
US7719094B2 (en) Semiconductor package and manufacturing method thereof
US7679177B2 (en) Integrated circuit packaging system with passive components
US7977780B2 (en) Multi-layer package-on-package system
US20080036051A1 (en) Quad flat package
US20060027902A1 (en) Method and apparatus for stacked die packaging
KR20060130125A (en) Semiconductor package and semiconductor device
KR20090065434A (en) Integrated circuit package system with flip chip
US20040183180A1 (en) Multi-chips stacked package
US7564123B1 (en) Semiconductor package with fastened leads
US20080093723A1 (en) Passive placement in wire-bonded microelectronics
KR101737053B1 (en) Semiconductor packages
EP4174938A1 (en) Leadframe package with metal interposer
US7759806B2 (en) Integrated circuit package system with multiple device units
KR20130086687A (en) Multi chip stacked package
KR100393099B1 (en) Semiconductor package
CN117727725A (en) Semiconductor package
KR20080067891A (en) Multi chip package
KR20000040586A (en) Multi chip package having printed circuit substrate
US20040183190A1 (en) Multi-chips stacked package

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20231020

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR