EP1454357A2 - Method for controlling blooming of a photodiode and corresponding integrated circuit - Google Patents
Method for controlling blooming of a photodiode and corresponding integrated circuitInfo
- Publication number
- EP1454357A2 EP1454357A2 EP02799810A EP02799810A EP1454357A2 EP 1454357 A2 EP1454357 A2 EP 1454357A2 EP 02799810 A EP02799810 A EP 02799810A EP 02799810 A EP02799810 A EP 02799810A EP 1454357 A2 EP1454357 A2 EP 1454357A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- photodiode
- junction
- intermediate layer
- integrated circuit
- direct conduction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000969 carrier Substances 0.000 claims abstract description 10
- 238000005215 recombination Methods 0.000 claims abstract description 5
- 230000006798 recombination Effects 0.000 claims abstract description 5
- 238000005286 illumination Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 abstract 2
- 230000004913 activation Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 37
- 239000006185 dispersion Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14654—Blooming suppression
Definitions
- the invention relates to microelectronics, in particular integrated circuits comprising photodiodes, and more particularly the control of over-illumination (“blooming” in English) of such a photodiode.
- Image sensors based on semiconductor components take advantage of the principle of converting photons into electron / hole pairs in silicon. More precisely, the charges created in the photosensitive zones are stored in the photodiode and are then read using an electronic system.
- This electronic system which controls the photodiode, comprises, in particular when the photodiode is a fully depleted photodiode (“fully depleted” in English), a transfer transistor authorizing the transfer of the charges stored in the photodiode.
- the electrons which can no longer be stored in the photodiode can then diffuse in the semiconductor substrate to disturb all the photodiodes of the image sensor, this which visually leads to the generation of an increasingly important white halo on the image.
- one solution consists in defining the saturation level of the photodiode by the voltage applied to the gate of the transfer transistor. More precisely, this voltage is chosen so that the charges will be evacuated towards the supply (via a conduction controlled by a reset transistor) before they diffuse in the substrate and come to degrade the signal received by neighboring photodiodes.
- this voltage must be adjusted by a specific power supply and must take into account the dispersions linked to the technology. In addition, these dispersions lead to a reduction in the storage dynamics on the photodiode.
- the invention aims to remedy this drawback and proposes a radically different solution for controlling the over-illumination of a photodiode.
- the invention therefore provides an integrated circuit comprising at least one cell comprising a photodiode, this photodiode comprising a lower PN junction formed between a part of a semiconductor substrate and an intermediate layer situated on said substrate part, and an upper PN junction formed between the intermediate layer and an upper layer more heavily doped than the intermediate layer.
- the direct conduction voltage of the upper junction is lower than the direct conduction voltage of the lower junction.
- the photodiode will store charges until the surface diode (upper junction) goes into conduction and the carriers (electrons for example) “not storable” in the photodiode will then be recombined with the carriers (holes for example) of the surface layer (upper layer) instead of diffusing into the substrate.
- the maximum level of storage is no longer defined by the voltage of the channel of an MOS transistor (the transfer transistor), but by the voltage of direct conduction of a junction.
- the storage dynamic on the photodiode is therefore increased. And we have solved the problems related to the dispersions of technology.
- the over-lighting control means here comprise the upper junction and the upper layer. They therefore form an integral part of the photodiode, which is also a general characteristic of the integrated circuit according to the invention.
- the doping of the upper layer must be greater than the doping of the intermediate layer, so as to contain more carriers (holes, for example) than the carriers (electrons) of the layer intermediate, and this in order to allow recombination during over-illumination.
- a doping of the upper layer is preferably chosen at least five times greater than the doping of the intermediate layer, and for example at least ten times greater.
- the respective voltages of the direct conductions of the two junctions will preferably be chosen so as to obtain a direct conduction current for the upper junction at least ten times greater than the direct conduction current for the lower junction.
- the upper layer is formed of silicon doped with indium, while the intermediate layer is formed of silicon doped with phosphorus and that said portion of substrate is formed of silicon doped with boron.
- the intermediate layer is formed of silicon doped with phosphorus and that said portion of substrate is formed of silicon doped with boron.
- other materials are possible. One can thus replace phosphorus by arsenic or antimony. And, in general, we can choose any material which reduces the difference between the valence band and the silicon conduction band.
- the invention also relates to an image sensor comprising at least one integrated circuit as defined above.
- the invention also proposes a method for controlling the over-lighting of a photodiode produced in a semiconductor substrate.
- the photodiode comprises an upper junction PN formed between an upper layer and an intermediate layer supported by a portion of the substrate and, storage of the charges in the photodiode is authorized until direct conduction of said upper junction so as to promote the recombination of the carriers coming from the intermediate layer with the carriers of the upper layer.
- FIG. 1 schematically illustrates an image sensor according to the invention, formed of several cells equipped with photodiodes, according to the invention
- FIG. 2 schematically illustrates a semiconductor structure of a photodiode, according to the invention
- FIG. 3a schematically illustrates an example of doping of the different layers forming a photodiode, according to the invention
- FIG. 3b schematically illustrates an example of self-polarization of a photodiode, according to the invention, completely depleted
- FIG. 4 is another schematic representation of a photodiode, according to the invention, illustrating an embodiment of the method according to the invention.
- FIG. 5 represents two voltage-current curves concerning the two junctions of a photodiode according to the invention.
- the reference CIM generally designates an image sensor formed from a matrix of PX i5 cells (or pixels) each comprising a photodiode PD as well as means for controlling this photodiode.
- the photodiode is a totally depleted photodiode and the control means are means with four transistors TG, RST, SF and RS. That said, the invention is not limited to a completely depleted diode and applies to all photodiodes, especially those whose associated control means only have three transistors.
- control means with four transistors of a totally depleted photodiode are conventional and well known to those skilled in the art. We recall here, with reference to Figure 1, the main features.
- control means include a transfer transistor
- TG connected on the one hand to the photodiode PD and, on the other hand, to the gate of a follower transistor SF.
- the gate of the follower transistor SF is also connected to the supply voltage Vdd by means of a reset transistor, referenced RST.
- PX connects the follower transistor SF to a capacitive output register.
- the first phase is a phase of integration or storage of the charges in the photodiode during which the transfer transistor TG is blocked.
- the reset transistor is on.
- the selection transistor RS is made conductive, which makes it possible to determine the level of charge in the photodiode before the transfer.
- the transfer transistor TG is made conductive, then, while the reset transistor is still blocked, the transistor TG is again blocked, marking the end of the transfer.
- the selection transistor RS is then again made conductive so as to be able to determine the charge level after transfer.
- the reset transistor RST is again made conductive, while a new integration phase has already started.
- the amount of light received by the photodiode is then determined by the difference between the two charge levels, measured before and after transfer respectively.
- the means for controlling the over-illumination comprise a specific supply for adjusting the low level of the voltage applied to the gate of the transfer transistor TG
- the control means are, according to the invention, part integral of the PD photodiode, as detailed below.
- the CIM image sensor, and more particularly each cell or pixel PX ⁇ is produced in CMOS technology.
- FIG. 2 illustrates in more detail the semiconductor structure of the photodiode PD of a cell PXj.
- the reference SB denotes a silicon semiconductor substrate, doped here P.
- This substrate SB can for example be a P doped well and located within a P + doped semiconductor plate.
- the substrate SB is connected to ground.
- the transfer transistor TG is a MOS transistor whose source 2, N " doped, forms for the photodiode PD an intermediate layer which extends above part 1 of the substrate SB.
- this intermediate layer 2 is produced, for example by implantation, an upper layer 3, P + doped, which extends to an isolation region IS, for example a region of the LOCOS type, according to a name well known to those skilled in the art. Furthermore, part 1 of the substrate SB comes into contact with the upper layer 3, P + doped.
- the photodiode PD is therefore here formed of these three layers, which define two PN junctions (diodes), namely an upper junction formed by layers 2 and 3, and a lower junction formed by layer 2 and the underlying part of substrate 1.
- FIG. 3a An example of the doping profile of this photodiode PD is illustrated in FIG. 3a. More precisely, the upper layer 3, P + doped, is more strongly doped than the intermediate layer 2, itself more strongly doped than the underlying part of the substrate 1.
- a doping of the upper layer 3 will be chosen between 10 18 and 10 19 at./cm 3 .
- the doping of the intermediate layer 2 could be chosen between 10 17 and 10 18 at./cm 3 , while the doping of the underlying part 1 of the substrate could be chosen less than 10 16 at./ cm 3 .
- the photodiode With such doping of the intermediate layer 2, the photodiode is then of the totally depleted type, that is to say that it self-polarizes at a determined voltage when the concentration of electrons in layer 2 is zero at the end of transfer. In the example described, the photodiode self-polarizes at 1.5 volts ( Figure 3b).
- the photodiode PD consists of two junctions (diodes) D1 and D2. These two diodes Dl and D2 are chosen so that the voltage VI for direct conduction of the diode Dl (FIG. 5) is less than the voltage for direct conduction V2 of the diode D2. As a result, the photodiode PD will store charges during its illumination until the upper junction D1 goes into direct conduction.
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The invention concerns a photodiode comprising an upper junction PN (D1) formed on a top layer and an intermediate layer supported by a portion of a semiconductor substrate. A lower junction is formed between the intermediate layer and the substrate portion. The voltage activating direct conduction of the upper junction (D1) is lower than the voltage activating direct conduction of the lower junction (D2). The method consists in allowing storage of loads in the photodiode until activation of direct conduction of the upper junction so as to promote (F1) the recombination of carriers derived from the intermediate layer with carriers of the top layer.
Description
Procédé de contrôle du sur-éclairement d'une photodiode et circuit intégré correspondant. Method for controlling the over-illumination of a photodiode and corresponding integrated circuit.
L'invention concerne la microélectronique, notamment les circuits intégrés comportant des photodiodes, et plus particulièrement le contrôle du sur-éclairement («blooming» en langue anglaise) d'une telle photodiode.The invention relates to microelectronics, in particular integrated circuits comprising photodiodes, and more particularly the control of over-illumination (“blooming” in English) of such a photodiode.
Les capteurs d' image à base de composants semiconducteurs tirent profit du principe de la conversion des photons en paires électrons/trous dans le silicium. Plus précisément, les charges créées dans les zones photosensibles sont stockées dans la photodiode et sont ensuite lues grâce à un système électronique. Ce système électronique, qui commande la photodiode, comporte, notamment lorsque la photodiode est une photodiode totalement appauvrie («fully depleted» en langue anglaise), un transistor de transfert autorisant le transfert des charges stockées dans la photodiode.Image sensors based on semiconductor components take advantage of the principle of converting photons into electron / hole pairs in silicon. More precisely, the charges created in the photosensitive zones are stored in the photodiode and are then read using an electronic system. This electronic system, which controls the photodiode, comprises, in particular when the photodiode is a fully depleted photodiode (“fully depleted” in English), a transfer transistor authorizing the transfer of the charges stored in the photodiode.
Si l' on ne prend pas de précautions, dans des conditions de sur- éclairement, les électrons qui ne peuvent plus être stockés dans la photodiode peuvent alors se diffuser dans le substrat semiconducteur pour venir perturber toutes les photodiodes du capteur d' image, ce qui conduit visuellement à la génération d'un halo blanc de plus en plus important sur l'image.If we do not take precautions, under conditions of over-illumination, the electrons which can no longer be stored in the photodiode can then diffuse in the semiconductor substrate to disturb all the photodiodes of the image sensor, this which visually leads to the generation of an increasingly important white halo on the image.
Pour remédier à ce problème, une solution consiste à définir le niveau de saturation de la photodiode par la tension appliquée sur la grille du transistor de transfert. Plus précisément, cette tension est choisie de telle sorte que les charges seront évacuées vers l' alimentation (par l'intermédiaire d'une conduction commandée d'un transistor de remise à zéro) avant qu'elles ne diffusent dans le substrat et viennent dégrader le signal reçu par les photodiodes voisines. Cependant, cette tension doit être ajustée par une alimentation spécifique et doit prendre en compte les dispersions liées à la technologie. En outre, ces dispersions conduisent à une réduction de la dynamique de stockage sur la photodiode.
L'invention vise à remédier à cet inconvénient et propose une solution radicalement différente pour contrôler le sur-éclairement d'une photodiode.To remedy this problem, one solution consists in defining the saturation level of the photodiode by the voltage applied to the gate of the transfer transistor. More precisely, this voltage is chosen so that the charges will be evacuated towards the supply (via a conduction controlled by a reset transistor) before they diffuse in the substrate and come to degrade the signal received by neighboring photodiodes. However, this voltage must be adjusted by a specific power supply and must take into account the dispersions linked to the technology. In addition, these dispersions lead to a reduction in the storage dynamics on the photodiode. The invention aims to remedy this drawback and proposes a radically different solution for controlling the over-illumination of a photodiode.
L'invention propose donc un circuit intégré comprenant au moins une cellule comportant une photodiode, cette photodiode comportant une jonction PN inférieure formée entre une partie d'un substrat semiconducteur et une couche intermédiaire située sur ladite partie de substrat, et une jonction PN supérieure formée entre la couche intermédiaire et une couche supérieure plus fortement dopée que la couche intermédiaire.The invention therefore provides an integrated circuit comprising at least one cell comprising a photodiode, this photodiode comprising a lower PN junction formed between a part of a semiconductor substrate and an intermediate layer situated on said substrate part, and an upper PN junction formed between the intermediate layer and an upper layer more heavily doped than the intermediate layer.
Par ailleurs, la tension de mise en conduction directe de la jonction supérieure est inférieure à la tension de mise en conduction directe de la jonction inférieure.Furthermore, the direct conduction voltage of the upper junction is lower than the direct conduction voltage of the lower junction.
Ainsi, la photodiode stockera des charges jusqu' à ce que la diode de surface (jonction supérieure) se mette en conduction et les porteurs (électrons par exemple) « non stockables » dans la photodiode seront alors recombinés avec les porteurs (trous par exemple) de la couche de surface (couche supérieure) au lieu de diffuser dans le substrat. Ainsi, selon l'invention, le niveau maximum de stockage n' est plus défini par la tension du canal d'un transistor MOS (le transistor de transfert), mais par la tension de mise en conduction directe d'une jonction.Thus, the photodiode will store charges until the surface diode (upper junction) goes into conduction and the carriers (electrons for example) “not storable” in the photodiode will then be recombined with the carriers (holes for example) of the surface layer (upper layer) instead of diffusing into the substrate. Thus, according to the invention, the maximum level of storage is no longer defined by the voltage of the channel of an MOS transistor (the transfer transistor), but by the voltage of direct conduction of a junction.
La dynamique de stockage sur la photodiode est par conséquent augmentée. Et l'on a résolu les problèmes liés aux dispersions de la technologie.The storage dynamic on the photodiode is therefore increased. And we have solved the problems related to the dispersions of technology.
Par ailleurs, les moyens de contrôle de sur-éclairement comportent ici la jonction supérieure et la couche supérieure. Ils font donc partie intégrante de la photodiode, ce qui est également une caractéristique générale du circuit intégré selon l'invention.Furthermore, the over-lighting control means here comprise the upper junction and the upper layer. They therefore form an integral part of the photodiode, which is also a general characteristic of the integrated circuit according to the invention.
Le dopage de la couche supérieure doit être supérieur au dopage de la couche intermédiaire, de façon à contenir plus de porteurs (trous, par exemple) que les porteurs (électrons) de la couche
intermédiaire, et ce afin de permettre la recombinaison lors du sur- éclairement.The doping of the upper layer must be greater than the doping of the intermediate layer, so as to contain more carriers (holes, for example) than the carriers (electrons) of the layer intermediate, and this in order to allow recombination during over-illumination.
Par ailleurs, même si la tension de mise en conduction directe de la jonction supérieure est inférieure à la tension de mise en conduction directe de la jonction inférieure de la photodiode, il subsiste généralement néanmoins un courant dans le substrat résultant également de la mise en conduction directe de la jonction inférieure.Furthermore, even if the direct conduction voltage of the upper junction is lower than the direct conduction voltage of the lower junction of the photodiode, there is generally still a current in the substrate also resulting from the conduction direct from the lower junction.
L'homme du métier saura ajuster en fonction des applications et du niveau maximum de stockage souhaité pour la photodiode, d'une part le dopage de la couche supérieure par rapport au dopage de la couche intermédiaire et, d' autre part, le rapport entre le courant de conduction directe pour la jonction supérieure par rapport au courant de conduction directe de la jonction inférieure.Those skilled in the art will be able to adjust, depending on the applications and the maximum level of storage desired for the photodiode, on the one hand the doping of the upper layer compared to the doping of the intermediate layer and, on the other hand, the ratio between the direct conduction current for the upper junction compared to the direct conduction current for the lower junction.
Ceci étant, on choisira de préférence un dopage de la couche supérieure au moins cinq fois supérieur au dopage de la couche intermédiaire, et par exemple au moins dix fois supérieur. Par ailleurs, on choisira de préférence des tensions respectives des mises en conduction directe des deux jonctions de façon à obtenir un courant de conduction directe pour la jonction supérieure au moins dix fois supérieur au courant de conduction directe de la jonction inférieure.This being the case, a doping of the upper layer is preferably chosen at least five times greater than the doping of the intermediate layer, and for example at least ten times greater. Furthermore, the respective voltages of the direct conductions of the two junctions will preferably be chosen so as to obtain a direct conduction current for the upper junction at least ten times greater than the direct conduction current for the lower junction.
Selon un mode de réalisation de l'invention, la couche supérieure est formée de silicium dopé par de l'indium, tandis que la couche intermédiaire est formée de silicium dopé par du phosphore et que ladite partie de substrat est formée de silicium dopé par du bore. Ceci étant, d' autres matériaux sont envisageables. On peut ainsi remplacer le phosphore par de l' arsenic ou de l'antimoine. Et, d'une façon générale, on pourra choisir tout matériau qui diminue l'écart entre la bande de valence et la bande de conduction du silicium.According to one embodiment of the invention, the upper layer is formed of silicon doped with indium, while the intermediate layer is formed of silicon doped with phosphorus and that said portion of substrate is formed of silicon doped with boron. However, other materials are possible. One can thus replace phosphorus by arsenic or antimony. And, in general, we can choose any material which reduces the difference between the valence band and the silicon conduction band.
L'invention a également pour objet un capteur d'image comportant au moins un circuit intégré tel que défini ci-avant.The invention also relates to an image sensor comprising at least one integrated circuit as defined above.
L'invention propose encore un procédé de contrôle du sur- éclairement d'une photodiode réalisé dans un substrat semiconducteur. Selon une caractéristique générale de ce procédé selon l'invention, la photodiode comporte une jonction supérieure PN
formée entre une couche supérieure et une couche intermédiaire supportée par une partie du substrat et, on autorise le stockage des charges dans la photodiode jusqu' à mettre en conduction directe ladite jonction supérieure de façon à favoriser la recombinaison des porteurs issus de la couche intermédiaire avec les porteurs de la couche supérieure.The invention also proposes a method for controlling the over-lighting of a photodiode produced in a semiconductor substrate. According to a general characteristic of this method according to the invention, the photodiode comprises an upper junction PN formed between an upper layer and an intermediate layer supported by a portion of the substrate and, storage of the charges in the photodiode is authorized until direct conduction of said upper junction so as to promote the recombination of the carriers coming from the intermediate layer with the carriers of the upper layer.
D' autres avantages et caractéristiques de l'invention apparaîtront à l'examen de la description détaillée de modes de réalisation et de mises en œuvre, nullement limitatifs, et des dessins annexés, sur lesquels :Other advantages and characteristics of the invention will appear on examination of the detailed description of embodiments and implementations, in no way limiting, and of the appended drawings, in which:
-la figure 1 illustre de façon schématique un capteur d'image selon l'invention, formé de plusieurs cellules équipées de photodiodes, selon l'invention,FIG. 1 schematically illustrates an image sensor according to the invention, formed of several cells equipped with photodiodes, according to the invention,
-la figure 2 illustre de façon schématique une structure semiconductrice d'une photodiode, selon l'invention ;FIG. 2 schematically illustrates a semiconductor structure of a photodiode, according to the invention;
-la figure 3a illustre de façon schématique un exemple de dopage des différentes couches formant une photodiode, selon l'invention ;FIG. 3a schematically illustrates an example of doping of the different layers forming a photodiode, according to the invention;
-la figure 3b illustre de façon schématique un exemple d' auto- polarisation d' une photodiode, selon l'invention, totalement appauvrie ;FIG. 3b schematically illustrates an example of self-polarization of a photodiode, according to the invention, completely depleted;
-la figure 4 est une autre représentation schématique d'une photodiode, selon l'invention, illustrant un mode de mise en œuvre du procédé selon l'invention ; et -la figure 5 représente deux courbes tension-courant concernant les deux jonctions d'une photodiode selon l'invention.FIG. 4 is another schematic representation of a photodiode, according to the invention, illustrating an embodiment of the method according to the invention; and FIG. 5 represents two voltage-current curves concerning the two junctions of a photodiode according to the invention.
Sur la figure 1 , la référence CIM désigne d'une façon générale un capteur d'image formé d'une matrice de cellules (ou pixels) PXi5 comportant chacune une photodiode PD ainsi que des moyens de commande de cette photodiode.In FIG. 1, the reference CIM generally designates an image sensor formed from a matrix of PX i5 cells (or pixels) each comprising a photodiode PD as well as means for controlling this photodiode.
Dans l' exemple qui est décrit ici, la photodiode est une photodiode totalement appauvrie et les moyens de commande sont des moyens à quatre transistors TG, RST, SF et RS . Ceci étant, l'invention n'est pas limitée à une diode totalement appauvrie et s' applique à
toutes photodiodes, notamment celles dont les moyens de commande associés ne comportent que trois transistors.In the example which is described here, the photodiode is a totally depleted photodiode and the control means are means with four transistors TG, RST, SF and RS. That said, the invention is not limited to a completely depleted diode and applies to all photodiodes, especially those whose associated control means only have three transistors.
La structure et le fonctionnement des moyens de commande à quatre transistors d' une photodiode totalement appauvrie, sont classiques et bien connus de l'homme du métier. On en rappelle ici, en se référant à la figure 1, les principales caractéristiques.The structure and operation of the control means with four transistors of a totally depleted photodiode are conventional and well known to those skilled in the art. We recall here, with reference to Figure 1, the main features.
Ces moyens de commande comportent un transistor de transfertThese control means include a transfer transistor
TG, relié d'une part à la photodiode PD et, d' autre part, à la grille d'un transistor suiveur SF. La grille du transistor suiveur SF est également reliée à la tension d'alimentation Vdd par l'intermédiaire d'un transistor de remise à zéro, référencé RST.TG, connected on the one hand to the photodiode PD and, on the other hand, to the gate of a follower transistor SF. The gate of the follower transistor SF is also connected to the supply voltage Vdd by means of a reset transistor, referenced RST.
Enfin, un transistor RS permettant de sélectionner la celluleFinally, an RS transistor for selecting the cell
PX; connecte le transistor suiveur SF à un registre de sortie capacitif.PX ; connects the follower transistor SF to a capacitive output register.
En ce qui concerne le fonctionnement de la cellule, la première phase est une phase d'intégration ou de stockage des charges dans la photodiode au cours de laquelle le transistor de transfert TG est bloqué. Pendant la majeure partie de la phase d'intégration, le transistor de remise à zéro est passant. Puis, juste avant le transfert des charges de la photodiode vers la sortie, le transistor RST est bloqué, puis le transistor de sélection RS est rendu conducteur, ce qui permet de déterminer le niveau de charge dans la photodiode avant le transfert.As regards the operation of the cell, the first phase is a phase of integration or storage of the charges in the photodiode during which the transfer transistor TG is blocked. During most of the integration phase, the reset transistor is on. Then, just before the transfer of the charges from the photodiode to the output, the transistor RST is blocked, then the selection transistor RS is made conductive, which makes it possible to determine the level of charge in the photodiode before the transfer.
Lors du transfert, le transistor de transfert TG est rendu conducteur, puis, alors que le transistor de remise à zéro est toujours bloqué, le transistor TG est à nouveau bloqué, marquant la fin du transfert. Le transistor de sélection RS est alors à nouveau rendu conducteur de façon à pouvoir déterminer le niveau de charge après transfert.During the transfer, the transfer transistor TG is made conductive, then, while the reset transistor is still blocked, the transistor TG is again blocked, marking the end of the transfer. The selection transistor RS is then again made conductive so as to be able to determine the charge level after transfer.
Après cette deuxième mesure, le transistor de remise à zéro RST est à nouveau rendu conducteur, tandis qu'une nouvelle phase d'intégration a déjà commencé.After this second measurement, the reset transistor RST is again made conductive, while a new integration phase has already started.
La quantité de lumière reçue par la photodiode est alors déterminée par la différence entre les deux niveaux de charge, mesurés respectivement avant et après transfert.
Alors que dans l' art antérieur, les moyens de contrôle du sur- éclairement comportent une alimentation spécifique pour régler le niveau bas de la tension appliquée sur la grille du transistor de transfert TG, les moyens de contrôle font, selon l'invention, partie intégrante de la photodiode PD, comme détaillé ci-après.The amount of light received by the photodiode is then determined by the difference between the two charge levels, measured before and after transfer respectively. Whereas in the prior art, the means for controlling the over-illumination comprise a specific supply for adjusting the low level of the voltage applied to the gate of the transfer transistor TG, the control means are, according to the invention, part integral of the PD photodiode, as detailed below.
Le capteur d'image CIM, et plus particulièrement chaque cellule ou pixel PX} est réalisé en technologie CMOS.The CIM image sensor, and more particularly each cell or pixel PX} is produced in CMOS technology.
La figure 2 illustre plus en détail la structure semiconductrice de la photodiode PD d'une cellule PXj. Sur cette figure 2, la référence SB désigne un substrat semiconducteur en silicium, dopé ici P. Ce substrat SB peut être par exemple un caisson dopé P et situé au sein d'une plaque semiconductrice dopée P+. Le substrat SB est relié à la masse.FIG. 2 illustrates in more detail the semiconductor structure of the photodiode PD of a cell PXj. In this FIG. 2, the reference SB denotes a silicon semiconductor substrate, doped here P. This substrate SB can for example be a P doped well and located within a P + doped semiconductor plate. The substrate SB is connected to ground.
Le transistor de transfert TG est un transistor MOS dont la source 2, dopée N", forme pour la photodiode PD une couche intermédiaire qui s'étend au-dessus de la partie 1 du substrat SB.The transfer transistor TG is a MOS transistor whose source 2, N " doped, forms for the photodiode PD an intermediate layer which extends above part 1 of the substrate SB.
Au-dessus de cette couche intermédiaire 2, est réalisée, par exemple par implantation, une couche supérieure 3, dopée P+, qui s'étend jusqu' à une région d'isolement IS, par exemple une région du type LOCOS, selon une dénomination bien connue de l'homme du métier. Par ailleurs, la partie 1 du substrat SB vient au contact de la couche supérieure 3, dopée P+.Above this intermediate layer 2 is produced, for example by implantation, an upper layer 3, P + doped, which extends to an isolation region IS, for example a region of the LOCOS type, according to a name well known to those skilled in the art. Furthermore, part 1 of the substrate SB comes into contact with the upper layer 3, P + doped.
La photodiode PD est donc ici formée de ces trois couches, qui définissent deux jonctions PN (diodes), à savoir une jonction supérieure formée des couches 2 et 3, et une jonction inférieure formée de la couche 2 et de la partie sous-jacente de substrat 1.The photodiode PD is therefore here formed of these three layers, which define two PN junctions (diodes), namely an upper junction formed by layers 2 and 3, and a lower junction formed by layer 2 and the underlying part of substrate 1.
Un exemple de profil de dopage de cette photodiode PD est illustré sur la figure 3a. Plus précisément, la couche supérieure 3, dopée P+, est plus fortement dopée que la couche intermédiaire 2, elle- même plus fortement dopée que la partie sous-j acente de substrat 1.An example of the doping profile of this photodiode PD is illustrated in FIG. 3a. More precisely, the upper layer 3, P + doped, is more strongly doped than the intermediate layer 2, itself more strongly doped than the underlying part of the substrate 1.
A titre indicatif, on choisira un dopage de la couche supérieure 3 compris entre 1018 et 1019 at./cm3.
Le dopage de la couche intermédiaire 2 pourra être, quant à lui, choisi entre 1017 et 1018 at./cm3, tandis que le dopage de la partie sous- jacente 1 de substrat pourra être choisi inférieur à 1016 at./cm3.As an indication, a doping of the upper layer 3 will be chosen between 10 18 and 10 19 at./cm 3 . The doping of the intermediate layer 2 could be chosen between 10 17 and 10 18 at./cm 3 , while the doping of the underlying part 1 of the substrate could be chosen less than 10 16 at./ cm 3 .
Avec un tel dopage de la couche intermédiaire 2, la photodiode est alors du type totalement appauvri, c'est à dire qu'elle s'auto- polarise à une tension déterminée lorsque la concentration des électrons dans la couche 2 est nulle en fin de transfert. Dans l'exemple décrit la photodiode s' auto-polarise à 1,5 volts (figure 3b).With such doping of the intermediate layer 2, the photodiode is then of the totally depleted type, that is to say that it self-polarizes at a determined voltage when the concentration of electrons in layer 2 is zero at the end of transfer. In the example described, the photodiode self-polarizes at 1.5 volts (Figure 3b).
Comme illustré sur la figure 4, et comme indiqué ci-avant, la photodiode PD se compose de deux jonctions (diodes) Dl et D2. Ces deux diodes Dl et D2 sont choisies de sorte que la tension VI de mise en conduction directe de la diode Dl (figure 5) soit inférieure à la tension de mise en conduction directe V2 de la diode D2. De ce fait, la photodiode PD stockera des charges lors de son éclairement jusqu' à ce que la jonction supérieure Dl se mette en conduction directe.As illustrated in FIG. 4, and as indicated above, the photodiode PD consists of two junctions (diodes) D1 and D2. These two diodes Dl and D2 are chosen so that the voltage VI for direct conduction of the diode Dl (FIG. 5) is less than the voltage for direct conduction V2 of the diode D2. As a result, the photodiode PD will store charges during its illumination until the upper junction D1 goes into direct conduction.
Les électrons « non stockables » dans la couche intermédiaire 2 dopée N, seront alors transférés préférentiellement (flèche FI, figureThe “non-storable” electrons in the N-doped intermediate layer 2 will then be preferentially transferred (arrow FI, figure
4) dans la couche supérieure 3 pour se recombiner avec les trous de cette couche supérieure 3, et ne diffuseront pas dans le substrat pour aller perturber les photodiodes voisines.4) in the upper layer 3 to recombine with the holes in this upper layer 3, and will not diffuse into the substrate to disturb the neighboring photodiodes.
Ceci étant, en fonction des caractéristiques CD1 , CD2 (figureHowever, depending on the characteristics CD1, CD2 (figure
5) des jonctions, il peut exister également, simultanément au courant Il de conduction directe de la jonction Dl , un faible courant 12 de conduction directe de la jonction D2. Cependant, dans l'exemple décrit ici, un rapport 10 entre le courant II et 12 permet généralement une bonne recombinaison des électrons avec les trous de la couche supérieure sans que les électrons qui diffusent dans le substrat (flèche F2, figure 4) soient gênants pour les photodiodes voisines. A titre indicatif, si l' on prend une tension de mise en conduction directe V2 pour la diode D2 égale à 0,6 volt, on pourra par exemple choisir une tension de mise en conduction directe VI égale à 0,4 volt pour la jonction Dl .
Matériellement, pour obtenir cette différence de tension de mise en conduction directe, on pourra par exemple choisir une implantation P+ obtenue avec de l'indium, tandis que le dopage P de la partie de substrat sera obtenu par du bore. La région 2 pourra être elle dopée N par du phosphore.
5) of the junctions, there may also exist, simultaneously with the current Il of direct conduction of the junction D1, a weak current 12 of direct conduction of the junction D2. However, in the example described here, a ratio 10 between the current II and 12 generally allows a good recombination of the electrons with the holes of the upper layer without the electrons which diffuse in the substrate (arrow F2, figure 4) being troublesome. for neighboring photodiodes. As an indication, if we take a direct conduction voltage V2 for the diode D2 equal to 0.6 volts, we could for example choose a direct conduction voltage VI equal to 0.4 volt for the junction Dl. Materially, to obtain this difference in direct conduction voltage, it will be possible for example to choose a P + implantation obtained with indium, while the P doping of the substrate part will be obtained with boron. Region 2 can be doped N by phosphorus.
Claims
REVENDICATIONS
1-Circuit intégré, comprenant au moins une cellule comportant une photodiode et des moyens de contrôle de sur-éclairement de la photodiode, caractérisé par le fait que les moyens de contrôle de sur- éclairement ( 2,3) font partie intégrante de la photodiode (PD) .1-Integrated circuit, comprising at least one cell comprising a photodiode and means for controlling over-illumination of the photodiode, characterized in that the means for controlling over-illumination (2,3) are an integral part of the photodiode (PD).
2-Dispositif selon la revendication 1, caractérisé par le fait que la photodiode comporte une jonction PN inférieure (D2) formée entre une partie d'un substrat semiconducteur (1) et une couche intermédiaire (2) située sur ladite partie de substrat, et une jonction PN supérieure (Dl) formée entre la couche intermédiaire (2) et une couche supérieure (3) plus fortement dopée que la couche intermédiaire, et par le fait que la tension de mise en conduction directe de la jonction supérieure est inférieure à la tension de mise en conduction directe de la jonction inférieure, les moyens de contrôle de sur-éclairement comportant la jonction supérieure (Dl) et la couche supérieure (3).2-Device according to claim 1, characterized in that the photodiode comprises a lower PN junction (D2) formed between a part of a semiconductor substrate (1) and an intermediate layer (2) located on said substrate part, and an upper PN junction (Dl) formed between the intermediate layer (2) and an upper layer (3) more heavily doped than the intermediate layer, and by the fact that the direct conduction voltage of the upper junction is lower than the direct conduction voltage of the lower junction, the over-illumination control means comprising the upper junction (Dl) and the upper layer (3).
3-Circuit intégré comprenant au moins une cellule comportant une photodiode, caractérisé par le fait que la photodiode comporte une jonction PN inférieure (D2) formée entre une partie d' un substrat semiconducteur (1) et une couche intermédiaire (2) située sur ladite partie de substrat, et une jonction PN supérieure (Dl) formée entre la couche intermédiaire (2) et une couche supérieure (3) plus fortement dopée que la couche intermédiaire, et par le fait que la tension de mise en conduction directe de la jonction supérieure est inférieure à la tension de mise en conduction directe de la jonction inférieure.3-Integrated circuit comprising at least one cell comprising a photodiode, characterized in that the photodiode comprises a lower PN junction (D2) formed between a part of a semiconductor substrate (1) and an intermediate layer (2) located on said substrate part, and an upper PN junction (Dl) formed between the intermediate layer (2) and an upper layer (3) more heavily doped than the intermediate layer, and by the fact that the direct conduction voltage of the junction upper is lower than the direct conduction voltage of the lower junction.
4-Circuit intégré selon la revendication 2 ou 3, caractérisé par le fait que le dopage de la couche supérieure (3) est au moins 5 fois supérieur au dopage de la couche intermédiaire (2).4-Integrated circuit according to claim 2 or 3, characterized in that the doping of the upper layer (3) is at least 5 times greater than the doping of the intermediate layer (2).
5-Circuit intégré selon l'une des revendications 2 à 4, caractérisé par le fait que les tensions respectives de mise en conduction directe des deux jonctions sont choisies de façon à obtenir un courant de conduction directe pour la jonction supérieure (D l) au
moins dix fois supérieur au courant de conduction directe de la jonction inférieure (D2).5-Integrated circuit according to one of claims 2 to 4, characterized in that the respective direct conduction voltages of the two junctions are chosen so as to obtain a direct conduction current for the upper junction (D l) at least ten times greater than the direct conduction current of the lower junction (D2).
6-Circuit intégré selon l'une des revendications 2 à 5, caractérisé par le fait que la couche supérieure (3) est formée de silicium dopé par de l'indium, par le fait que la couche intermédiaire6-Integrated circuit according to one of claims 2 to 5, characterized in that the upper layer (3) is formed of silicon doped with indium, in that the intermediate layer
(2) est formée de silicium dopé par du phosphore, et par le fait que ladite partie de substrat (1) est formée de silicium dopé par du bore.(2) is formed of silicon doped with phosphorus, and by the fact that said substrate portion (1) is formed of silicon doped with boron.
7-Circuit intégré selon l'une des revendications précédentes, caractérisé par le fait que la photodiode est une photodiode totalement appauvrie, et par le fait que la cellule comprend en outre des moyens de commande de la photodiode à quatre transistors (TG, RST, RS, SF).7-Integrated circuit according to one of the preceding claims, characterized by the fact that the photodiode is a completely depleted photodiode, and by the fact that the cell further comprises means for controlling the photodiode with four transistors (TG, RST, RS, SF).
8-Circuit intégré selon l'une des revendications précédentes, caractérisé par le fait qu' il comprend une matrice de cellules (PXj).8-Integrated circuit according to one of the preceding claims, characterized in that it comprises a matrix of cells (PXj).
9-Capteur d'images, caractérisé par le fait qu'il comporte au moins un circuit intégré selon la revendication 8.9-Image sensor, characterized in that it comprises at least one integrated circuit according to claim 8.
10-Procédé de contrôle du sur-éclairement d'une photodiode réalisé dans un substrat semiconducteur, caractérisé par le fait que la photodiode comporte une jonction supérieure PN (D l) formée entre une couche supérieure et une couche intermédiaire supportée par une partie du substrat, et par le fait qu'on autorise le stockage des charges dans la photodiode jusqu' à mettre en conduction directe ladite jonction supérieure de façon à favoriser (FI) la recombinaison des porteurs issus de la couche intermédiaire avec les porteurs de la couche supérieure.
10-Method for controlling the over-illumination of a photodiode produced in a semiconductor substrate, characterized in that the photodiode comprises an upper PN junction (D l) formed between an upper layer and an intermediate layer supported by a part of the substrate , and by the fact that the storage of charges is authorized in the photodiode until said upper junction is put into direct conduction so as to promote (FI) the recombination of the carriers from the intermediate layer with the carriers of the upper layer.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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FR0116047 | 2001-12-12 | ||
FR0116047A FR2833408B1 (en) | 2001-12-12 | 2001-12-12 | METHOD FOR CONTROLLING THE ILLUMINATION OF A PHOTODIODE AND CORRESPONDING INTEGRATED CIRCUIT |
PCT/FR2002/004302 WO2003050874A2 (en) | 2001-12-12 | 2002-12-12 | Method for controlling blooming of a photodiode and corresponding integrated circuit |
Publications (1)
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EP1454357A2 true EP1454357A2 (en) | 2004-09-08 |
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EP02799810A Withdrawn EP1454357A2 (en) | 2001-12-12 | 2002-12-12 | Method for controlling blooming of a photodiode and corresponding integrated circuit |
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US (1) | US7586172B2 (en) |
EP (1) | EP1454357A2 (en) |
JP (1) | JP2005512341A (en) |
FR (1) | FR2833408B1 (en) |
WO (1) | WO2003050874A2 (en) |
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US7791663B2 (en) * | 2004-10-15 | 2010-09-07 | Omnivision Technologies, Inc. | Image sensor and pixel that has positive transfer gate voltage during integration period |
US7432543B2 (en) * | 2004-12-03 | 2008-10-07 | Omnivision Technologies, Inc. | Image sensor pixel having photodiode with indium pinning layer |
US7378635B2 (en) | 2005-02-11 | 2008-05-27 | Micron Technology, Inc. | Method and apparatus for dark current and hot pixel reduction in active pixel image sensors |
JP5493430B2 (en) * | 2009-03-31 | 2014-05-14 | ソニー株式会社 | SOLID-STATE IMAGING DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
JP5644433B2 (en) * | 2010-12-02 | 2014-12-24 | ソニー株式会社 | Solid-state imaging device and method for manufacturing solid-state imaging device |
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- 2002-12-12 EP EP02799810A patent/EP1454357A2/en not_active Withdrawn
- 2002-12-12 WO PCT/FR2002/004302 patent/WO2003050874A2/en active Application Filing
- 2002-12-12 JP JP2003551836A patent/JP2005512341A/en active Pending
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JP2005512341A (en) | 2005-04-28 |
WO2003050874A3 (en) | 2004-04-15 |
WO2003050874A2 (en) | 2003-06-19 |
FR2833408A1 (en) | 2003-06-13 |
FR2833408B1 (en) | 2004-03-12 |
US7586172B2 (en) | 2009-09-08 |
US20050116270A1 (en) | 2005-06-02 |
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