EP1127376A1 - Integrated circuit chip made secure against the action of electromagnetic radiation - Google Patents

Integrated circuit chip made secure against the action of electromagnetic radiation

Info

Publication number
EP1127376A1
EP1127376A1 EP99947524A EP99947524A EP1127376A1 EP 1127376 A1 EP1127376 A1 EP 1127376A1 EP 99947524 A EP99947524 A EP 99947524A EP 99947524 A EP99947524 A EP 99947524A EP 1127376 A1 EP1127376 A1 EP 1127376A1
Authority
EP
European Patent Office
Prior art keywords
chip
layer
silicon
action
electromagnetic radiation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99947524A
Other languages
German (de)
French (fr)
Inventor
Robert Leydier
Béatrice BONVALOT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales DIS France SA
Original Assignee
Schlumberger Systemes SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schlumberger Systemes SA filed Critical Schlumberger Systemes SA
Publication of EP1127376A1 publication Critical patent/EP1127376A1/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions

  • the present invention relates to integrated circuit chips intended to be incorporated into portable objects in particular in card format.
  • Chip cards are generally used in applications in which the security of the storage and processing of confidential information is essential. These are, for example, applications from the health sector, telephony, pay television or the banking sector such as electronic wallet applications. These cards consist of a plastic card body in which an integrated circuit device or chip is incorporated.
  • the integrated circuit forms a complex assembly structure of logic cells in which a central processing unit CPU distributes and manages, via a bus. data and an address bus, information stored in RAM, ROM or EEPROM memories.
  • logic cells are of the CMOS type. They consist of a first P-type MOS transistor and a second N-type MOS transistor connected in series and controlled by a common control logic signal resulting from the concomitant action of the electrical signals present on the circuit inputs and electrical signals generated by the programs on board the ROM or EEPROM memories or by associated electronic circuits. As a function of this logic control signal, the distribution of the charges in the valence and conduction bands is modified, which induces a controlled switching of said transistors.
  • a technical problem which the invention proposes to solve is to produce a chip for a portable object with a chip, in particular in card format, comprising, on the one hand, a layer of silicon substrate with the active face of which are integrated circuits defining a central processing unit as well as memories and, on the other hand, a complementary layer of silicon covering, at least in part, said active face, which is not sensitive to the action of electromagnetic radiation from the ultraviolet, visible and infrared domains.
  • a solution to this technical problem posed consists, according to the invention, in that the chip further comprises physical protection means against the action of electromagnetic radiation from the infrared domain whose wavelength is greater than 1 ⁇ m.
  • these physical means of protection against the action of electromagnetic radiation are silicon dopants, or formed by surface irregularities or at least one metallic layer.
  • FIG. 1 shows, in perspective, a smart card according to the invention
  • Figure 2 shows, in perspective, a module comprising a chip according to the invention
  • FIGS. 3A and 3B show, in perspective, two types of chip according to the invention
  • FIGS. 4A, 4B and 4C show, in cross section, three variants of a first embodiment of a chip according to the invention
  • FIGS. 5A and 5B are curves representative of the measurement of the effect of the means according to the invention on the protection of the chip against the action of light;
  • FIGS. 6A, 6B, 6C and 6D show, in cross section, four variants of a second embodiment of a chip according to the invention;
  • Figures 7A, 7B, 7C and 7D show, in cross section, four variants of a third embodiment of a chip according to the invention.
  • the present description of the invention relates to the example of smart cards. It is nevertheless understood that the invention applies generally to any integrated circuit device intended to be incorporated in a portable object such as a subscriber identification module SIM in mini-card format or an electronic label.
  • a subscriber identification module SIM in mini-card format or an electronic label.
  • a smart card is a standard portable object operating with and / or without contact, which is defined in particular in ISO standards 7810 and 7816, the content of which is incorporated into the present description, by reference.
  • a smart card 1 comprises, on the one hand, a body 2 of plastic card and, on the other hand, an electronic module 3 of which contact pads 4 are placed flush with the surface of card body 2.
  • the card body 2 is plastic, thermoplastic or thermosetting. It is in the form of a flat rectangular parallelepiped whose dimensions are of the order of 85 mm in length, 54 mm in width and 0.76 mm in thickness.
  • the electronic module 3 shown in FIG. 2 comprises an integrated circuit device or chip 5 fixed by its rear face 6 to a thickness 7 of epoxy carrying the contact pads 4.
  • Contact pads 8 of this chip 5 are electrically connected to said pads 4 by means of metallic wires 9 via through holes 10 made through the thickness 7 of epoxy.
  • the assembly, chip 5 and wires 9, is coated in a protective resin 11.
  • the chips 5 according to the invention are in the form of rectangular parallelepipeds of small dimensions, in practice of the order 2 mm side and a few hundred microns thick, for example 200 ⁇ m. They are of two main types.
  • the chip 5 comprises a layer of silicon substrate 12.
  • This layer 12 shows an active face 13 in which the circuits are integrated and a face opposite to this active face 13, that is to say say the rear face 6.
  • the contact pads 8, generally five in number, are integrated into the active face 13.
  • the chip 5 likewise comprises a layer of silicon substrate 12 thinned by its rear face 6.
  • This layer of silicon substrate 12 likewise shows an active face 13, which includes integrated circuits, and a face opposite this active face or rear face 6.
  • the active face 13 is however covered with a complementary layer 14 of silicon sealed to said face 13 by a sealing layer 15.
  • the complementary layer 14 has a top face 18 and a bottom face 19 in contact with the sealing layer.
  • the sealing layers 15 and complementary 14 advantageously cover all or a large part of the active face 13 of the chip 5 with the exception of the contact pads 8 which remain accessible through openings 16 or vias formed in said layers 14 and 15.
  • the thicknesses of the different layers are as follows. Thinened substrate layer: of the order of 50 ⁇ m; additional layer: of the order of 150 ⁇ m; and sealing layer: of the order of 10 ⁇ m.
  • the chip 3 comprises physical means of protection against the action of light, that is to say against the action of electromagnetic radiation from the ultraviolet, visible and infrared domains, said domains being defined as follows by their wavelength.
  • Ultraviolet 10 nm ⁇ ⁇ 400 nm; visible: 400 nm ⁇ ⁇ 700 nm and infrared: 0.7 ⁇ m ⁇ ⁇ 0.1 mm.
  • these means are dopants 17 of silicon.
  • an intrinsic silicon crystal the atoms are wholly or almost all of the silicon atoms. As shown in FIG. 5A, such an intrinsic silicon crystal is, at 300 degrees Kelvin, opaque to electromagnetic radiation from most of the visible and ultraviolet spectrum whose wavelength is greater than 0.7 ⁇ m with an absorption coefficient greater than
  • the light absorption coefficient remains greater than 100 cm -1 , not only for the lengths wavelengths below 1 ⁇ m, but also for wavelengths above this value. We even note that the absorption coefficient increases for wavelengths increasing from 1 to 10 ⁇ m.
  • dopants conventionally used to modify the semiconductor properties of silicon, are capable of modifying the absorption properties of an intrinsic silicon crystal so that its absorption coefficient increases appreciably for wavelengths. greater than 1 ⁇ m, that is to say in particular for wavelengths in the infrared range.
  • the dopants 17 are atoms of a chemical nature different from that of silicon, the presence of which is the cause of defects in its crystal lattice. It is for example Phosphorus or Boron.
  • the number of doping atoms present in silicon is between 10 17 and 10 20 atoms per cm 3 preferably of the order of 10 19 atoms per cm 3 .
  • the absorption of light for a given wavelength and thickness is all the more effective the higher the doping level.
  • These dopants 17 can be incorporated into the crystal lattice during the growth of the silicon crystal, or else be subject to diffusion at high temperature under neutral atmosphere or even by ion implantation.
  • These dopants 17 may be present in the silicon substrate layer 12 of a chip 5 of the first type or of a chip 5 of the second type. They can also be incorporated into the complementary layer 14 of a chip 5 of the second type.
  • the dopants 17 are present in the complementary layer 14 of the chip 5. They are distributed in this layer 14 in a homogeneous manner. They can nevertheless be located only in part of the thickness of said layer 14, in particular in the part of this layer close to its top face 18.
  • the dopants 17 are present in the substrate layer 12 of the chip 5. These dopants are located in the rear part of said layer 12. Thus, the effects dopants on the electrical conduction do not disturb the proper functioning of the circuits integrated into the active face 13 of the chip 5.
  • the dopants 17 are present at the same time in the substrate layer 12 of the chip and in its complementary layer 14.
  • the means of physical protection against the action of light are formed by surface irregularities 20 apparent to a face of a layer of silicon. These surface irregularities may be apparent on the rear face of the silicon substrate or on one or both of the top and bottom faces of the complementary layer 14 for chips 5 of the second type.
  • These surface irregularities 20 consist for example of hollows and bumps formed over the entire surface considered of the substrate or complementary layer. The height of these hollows and bumps is of the order of a few microns.
  • these irregularities are formed by etching the silicon, for example using dry techniques, such as mechanical abrasion, or wet techniques, such as KOH machining.
  • the radiation no longer reaches the targets sought by the fraudster without the latter being able to predict which targets are ultimately reached. Attacks are made impossible.
  • the irregularities 20 are formed on the face of the complementary layer 14 in contact with the sealing layer 15.
  • the irregularities 20 are formed on the rear face of the silicon substrate layer.
  • the irregularities 20 are formed on the face 18 of the complementary layer.
  • the irregularities 20 are formed on the top face 18 of the complementary layer 14, on its bottom face 19 and on the rear face 6 of the chip 3
  • the physical protection means are formed by a metal layer 21 assembled on at least one of the faces of the layers of substrate 12 or complementary 14 silicon and whose the thickness is greater than 50 Angstroms, for example of the order of 100 Angstroms.
  • the metallization of a face can be carried out by vacuum deposition.
  • the metal layer reflects or absorbs all of the incident light intended to illuminate the circuits. It is no longer possible to inspect the active surface of the integrated circuit using an optical microscope or even to observe using infrared techniques.
  • FIG. 7A which shows a chip of the second type, the metal layer 21 is placed between the complementary layer 14 and the sealing layer 15.
  • the metal layer 21 is placed on the rear face of the substrate layer 12.
  • the metal layer 21 is placed on the top face 18 of the complementary layer 14.
  • FIG. 7D which shows a chip 3 of the second type
  • a first metallic layer is placed between the layer complementary 14 and the sealing layer 15 and to the rear face of the substrate layer 12.
  • the invention is not limited to the aforementioned variants.
  • the physical means of protection against the action of light are capable of covering all of the integrated circuits, or else, certain parts of said circuits.
  • they will advantageously be key parts, that is to say sensitive to attacks by light and of which a disturbance by said light could prove to be dangerous for the integrity of the chip and the secrets it contains.
  • key parts are constituted by the voltage multiplier used for programming the EEPROM memory cells, the amplifiers for reading the contents of the memories and certain registers of the volatile memory (RAM) or of the central processing unit (CPU). ).

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Credit Cards Or The Like (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention concerns a chip (5) for portable object in particular in card format, comprising a silicon substrate layer (12) at the active surface (13) of which are integrated circuits defining a central processing unit and storage units. The invention is characterised in that the chip (3) further comprises physical means (17, 19, 20) for protection against the action of electromagnetic radiation of the infrared whereof the wavelength is greater than 1 mu m. The invention is particularly applicable to chip cards.

Description

PUCE A CIRCUITS INTEGRES SECURISEE CONTRE L'ACTION DE RAYONNEMENTS ELECTROMAGNETIQUES CHIP WITH INTEGRATED CIRCUITS SECURE AGAINST THE ACTION OF ELECTROMAGNETIC RADIATION
La présente invention concerne des puces à circuits intégrés destinées à être incorporés dans des objets portatifs notamment au format carte.The present invention relates to integrated circuit chips intended to be incorporated into portable objects in particular in card format.
Les cartes à puce sont en général utilisées dans des applications dans lesquelles la sécurité du stockage et du traitement d'informations confidentielles sont essentielles. Il s'agit par exemple d'applications du domaine de la santé, de la téléphonie, de la télévision à péage ou du domaine bancaire comme les applications porte-monnaie électronique. Ces cartes se composent d'un corps de carte plastique dans lequel est incorporé un dispositif à circuit intégré ou puce.Chip cards are generally used in applications in which the security of the storage and processing of confidential information is essential. These are, for example, applications from the health sector, telephony, pay television or the banking sector such as electronic wallet applications. These cards consist of a plastic card body in which an integrated circuit device or chip is incorporated.
Dans la puce, le circuit intégré forme une structure d'assemblage complexe de cellules logiques dans laquelle une unité centrale de traitement CPU distribue et gère, par l'intermédiaire d'un bus de. données et d'un bus d'adresses, des informations stockées dans des mémoires RAM, ROM ou EEPROM.In the chip, the integrated circuit forms a complex assembly structure of logic cells in which a central processing unit CPU distributes and manages, via a bus. data and an address bus, information stored in RAM, ROM or EEPROM memories.
Classiquement, les cellules logiques sont du type CMOS. Elles sont constituées d'un premier transistor MOS de type P et d'un second transistor MOS de type N montés en série et commandés par un signal logique de commande commun issu de l'action concomitante des signaux électriques présents sur les entrées du circuit et des signaux électriques générés par les programmes embarqués dans les mémoires ROM ou EEPROM ou par des circuits électroniques associés. En fonction de ce signal logique de commande, la répartition des charges dans les bandes de valence et de conduction se trouve modifiée, ce qui induit une commutation contrôlée desdits transistors.Conventionally, logic cells are of the CMOS type. They consist of a first P-type MOS transistor and a second N-type MOS transistor connected in series and controlled by a common control logic signal resulting from the concomitant action of the electrical signals present on the circuit inputs and electrical signals generated by the programs on board the ROM or EEPROM memories or by associated electronic circuits. As a function of this logic control signal, the distribution of the charges in the valence and conduction bands is modified, which induces a controlled switching of said transistors.
Toutefois, certaines sources d'énergie peuvent aussi modifier cette répartition. C'est le cas en particulier des rayonnements électromagnétiques notamment des domaines allant des ultraviolets à l'infrarouge. De ce fait, en éclairant une zone de la puce, par exemple un ensemble de cellules logiques, avec un tel rayonnement, on peut faire commuter les transistors de cet ensemble de cellules indépendamment de tout contrôle électrique ordonné par les circuits logiques.However, certain energy sources can also modify this distribution. This is particularly the case with electromagnetic radiation, in particular in the fields ranging from ultraviolet infrared. Therefore, by illuminating an area of the chip, for example a set of logic cells, with such radiation, it is possible to switch the transistors of this set of cells independently of any electrical control ordered by the logic circuits.
C'est la raison pour laquelle des fraudeurs, en éclairant une zone appropriée des circuits d'une puce connectée par ses plots Vdd, Vss, Clock, I/O et Reset avec un rayonnement électromagnétique focalisé du domaine ultraviolet, visible ou infrarouge à un temps t de leur choix, ont pu faire commuter les transistors de cette zone et ainsi modifier le déroulement normal des opérations programmées dans les mémoires de la puce et notamment faire exécuter par celle-ci des opérations normalement non autorisées leur permettant d'accéder à des secrets sans destruction des circuits. Des moyens connus de protection du circuit intégré contre l'action de ces rayonnements électromagnétiques ont cependant été développés. Il s'agit de moyens logiciels se caractérisant par le fait que les programmes embarqués dans les mémoires ROM et EEPROM de la puce sont multiples et complétés par des moyens de vérification. Toutefois, ces moyens connus ne pallient pas efficacement aux attaques dites en lumière et présentent les inconvénients d'exiger un espace mémoire important dans la puce et de ralentir sensiblement le déroulement des opérations demandées à celle-ci.This is the reason why fraudsters, by illuminating an appropriate area of the circuits of a chip connected by its Vdd, Vss, Clock, I / O and Reset pads with electromagnetic radiation focused from the ultraviolet, visible or infrared domain to a time t of their choice, were able to switch the transistors of this zone and thus modify the normal course of the operations programmed in the memories of the chip and in particular make execute by this one operations normally not authorized allowing them to reach secrets without destroying circuits. Known means for protecting the integrated circuit against the action of this electromagnetic radiation have however been developed. These are software means characterized by the fact that the programs embedded in the ROM and EEPROM memories of the chip are multiple and supplemented by verification means. However, these known means do not effectively overcome so-called light attacks and have the drawbacks of requiring a large memory space in the chip and of significantly slowing the progress of the operations requested therefrom.
Compte tenu de ce qui précède, un problème technique que se propose de résoudre l'invention est de réaliser une puce pour objet portatif à puce notamment au format carte, comprenant, d'une part, une couche de substrat silicium à la face active de laquelle sont intégrés des circuits définissant une unité centrale de traitement ainsi que des mémoires et, d'autre part, une couche complémentaire de silicium couvrant, au moins en partie, ladite face active, qui ne soit pas sensible à l'action des rayonnements électromagnétiques des domaines ultraviolets, visible et infrarouge.In view of the above, a technical problem which the invention proposes to solve is to produce a chip for a portable object with a chip, in particular in card format, comprising, on the one hand, a layer of silicon substrate with the active face of which are integrated circuits defining a central processing unit as well as memories and, on the other hand, a complementary layer of silicon covering, at least in part, said active face, which is not sensitive to the action of electromagnetic radiation from the ultraviolet, visible and infrared domains.
Une solution à ce problème technique posé consiste, selon l'invention, en ce que la puce comporte en outre des moyens de protection physiques contre l'action de rayonnements électromagnétiques du domaine infrarouge dont la longueur d'onde est supérieure à lμm.A solution to this technical problem posed consists, according to the invention, in that the chip further comprises physical protection means against the action of electromagnetic radiation from the infrared domain whose wavelength is greater than 1 μm.
Notamment, ces moyens physiques de protection contre l'action des rayonnements électromagnétiques sont des dopants du silicium, ou formés par des irrégularités de surface ou d'au moins une couche métallique.In particular, these physical means of protection against the action of electromagnetic radiation are silicon dopants, or formed by surface irregularities or at least one metallic layer.
L'invention sera mieux comprise à la lecture de l'exposé non limitatif qui suit, rédigée au regard des dessins annexés, dans lesquels : la figure 1 montre, en perspective, une carte à puce selon l'invention ; la figure 2 montre, en perpective, un module comportant une puce selon l'invention ; les figures 3A et 3B montrent, en perspective, deux types de puce selon l'invention ; les figures 4A, 4B et 4C montrent, en coupe transversale, trois variantes d'un premier mode de réalisation d'une puce selon l'inventionThe invention will be better understood on reading the following non-limiting description, written with reference to the appended drawings, in which: FIG. 1 shows, in perspective, a smart card according to the invention; Figure 2 shows, in perspective, a module comprising a chip according to the invention; FIGS. 3A and 3B show, in perspective, two types of chip according to the invention; FIGS. 4A, 4B and 4C show, in cross section, three variants of a first embodiment of a chip according to the invention
les figures 5A et 5B sont des courbes représentatives de la mesure de l'effet des moyens selon l'invention sur la protection de la puce contre l'action de la lumière ; les figures 6A, 6B, 6C et 6D montrent, en coupe transversale, quatre variantes d'un second mode de réalisation d'une puce selon l'invention ; et les figures 7A, 7B, 7C et 7D montrent, en coupe transversale, quatre variantes d'un troisième mode de réalisation d'une puce selon l'invention.FIGS. 5A and 5B are curves representative of the measurement of the effect of the means according to the invention on the protection of the chip against the action of light; FIGS. 6A, 6B, 6C and 6D show, in cross section, four variants of a second embodiment of a chip according to the invention; and Figures 7A, 7B, 7C and 7D show, in cross section, four variants of a third embodiment of a chip according to the invention.
Le présent exposé de l'invention a trait à l'exemple des cartes à puce. Il est néanmoins bien entendu que l'invention s'applique de manière générale à tout dispositif à circuit intégré destiné à être incorporé dans un objet portatif tel qu'un module d'identification abonné SIM au format mini-carte ou une étiquette électronique.The present description of the invention relates to the example of smart cards. It is nevertheless understood that the invention applies generally to any integrated circuit device intended to be incorporated in a portable object such as a subscriber identification module SIM in mini-card format or an electronic label.
Une carte à puce est un objet portable standard fonctionnant avec et/ ou sans contact qui est défini notamment dans les normes ISO 7810 et 7816 dont le contenu est incorporé au présent exposé, par citation de référence.A smart card is a standard portable object operating with and / or without contact, which is defined in particular in ISO standards 7810 and 7816, the content of which is incorporated into the present description, by reference.
Ainsi que cela est montré à la figure 1, une carte 1 à puce comprend, d'une part, un corps 2 de carte plastique et, d'autre part, un module 3 électronique dont des plages 4 de contact sont placées affleurantes à la surface du corps 2 de carte.As shown in FIG. 1, a smart card 1 comprises, on the one hand, a body 2 of plastic card and, on the other hand, an electronic module 3 of which contact pads 4 are placed flush with the surface of card body 2.
Le corps 2 de carte est plastique, thermoplastique ou thermodurcissable. Il se présente sous la forme d'un parallélépipède rectangle plat dont les dimensions sont de l'ordre de 85 mm de longueur, 54 mm de largeur et 0,76 mm d'épaisseur.The card body 2 is plastic, thermoplastic or thermosetting. It is in the form of a flat rectangular parallelepiped whose dimensions are of the order of 85 mm in length, 54 mm in width and 0.76 mm in thickness.
Le module 3 électronique montré à la figure 2 comprend un dispositif à circuits intégrés ou puce 5 fixée par sa face 6 arrière à une épaisseur 7 d'époxy portant les plages 4 de contact. Des plots 8 de contact de cette puce 5 sont connectés électriquement auxdites plages 4 au moyen de fils 9 métalliques via des trous 10 débouchants ménagés au travers de l'épaisseur 7 d'époxy. L'ensemble, puce 5 et fils 9, est enrobé dans une résine 11 protectrice.The electronic module 3 shown in FIG. 2 comprises an integrated circuit device or chip 5 fixed by its rear face 6 to a thickness 7 of epoxy carrying the contact pads 4. Contact pads 8 of this chip 5 are electrically connected to said pads 4 by means of metallic wires 9 via through holes 10 made through the thickness 7 of epoxy. The assembly, chip 5 and wires 9, is coated in a protective resin 11.
Les puces 5 selon l'invention se présentent sous la forme de parallélépipèdes rectangles de petites dimensions, en pratique de l'ordre de 2 mm de côté et de quelques centaines de microns d'épaisseur, par exemple 200 μm. Elles sont de deux types principaux.The chips 5 according to the invention are in the form of rectangular parallelepipeds of small dimensions, in practice of the order 2 mm side and a few hundred microns thick, for example 200 μm. They are of two main types.
Dans un premier type présenté à la figure 3A, la puce 5 comprend une couche de substrat silicium 12. Cette couche 12 montre une face 13 active à laquelle sont intégrés les circuits et une face opposée à cette face 13 active, c'est-à-dire la face arrière 6. Les plots 8 de contact, en général au nombre de cinq, sont intégrés à la face active 13.In a first type presented in FIG. 3A, the chip 5 comprises a layer of silicon substrate 12. This layer 12 shows an active face 13 in which the circuits are integrated and a face opposite to this active face 13, that is to say say the rear face 6. The contact pads 8, generally five in number, are integrated into the active face 13.
Dans un second type présenté à la figure 3B, la puce 5 comprend de même une couche de substrat silicium 12 amincie par sa face arrière 6. Cette couche de substrat silicium 12 montre de même une face active 13, qui comporte des circuits intégrés, et une face opposée à cette face active ou face arrière 6. La face active 13 est cependant couverte d'une couche complémentaire 14 de silicium scellée à ladite face 13 par une couche de scellement 15. Le couche complémentaire 14 comporte une face de dessus 18 et une face de dessous 19 en contact avec la couche de scellement. Les couches de scellement 15 et complémentaire 14 recouvrent avantageusement la totalité ou alors une grande partie de la face active 13 de la puce 5 à l'exception des plots 8 de contact qui restent accessibles au travers d'ouvertures 16 ou vias ménagées dans lesdites couches 14 et 15. En pratique, les épaisseurs des différentes couches sont les suivantes. Couche de substrat amincie : de l'ordre de 50 μm ; couche complémentaire : de l'ordre de 150 μm ; et couche de scellement : de l'ordre de 10 μm.In a second type presented in FIG. 3B, the chip 5 likewise comprises a layer of silicon substrate 12 thinned by its rear face 6. This layer of silicon substrate 12 likewise shows an active face 13, which includes integrated circuits, and a face opposite this active face or rear face 6. The active face 13 is however covered with a complementary layer 14 of silicon sealed to said face 13 by a sealing layer 15. The complementary layer 14 has a top face 18 and a bottom face 19 in contact with the sealing layer. The sealing layers 15 and complementary 14 advantageously cover all or a large part of the active face 13 of the chip 5 with the exception of the contact pads 8 which remain accessible through openings 16 or vias formed in said layers 14 and 15. In practice, the thicknesses of the different layers are as follows. Thinened substrate layer: of the order of 50 μm; additional layer: of the order of 150 μm; and sealing layer: of the order of 10 μm.
Quel que soit son type, la puce 3 selon l'invention comporte des moyens physiques de protection contre l'action de la lumière, c'est-à- dire contre l'action de rayonnements électromagnétiques des domaines ultraviolet, visible et infrarouge, lesdits domaines étant définis comme suit par leur longueur d'onde. Ultraviolet : 10 nm <λ<400 nm; visible : 400 nm <λ<700 nm et infrarouge : 0,7 μm <λ<0, lmm. Dans un premier mode de réalisation de l'invention montré aux figures 4A, 4B et 4C ces moyens sont des dopants 17 du silicium.Whatever its type, the chip 3 according to the invention comprises physical means of protection against the action of light, that is to say against the action of electromagnetic radiation from the ultraviolet, visible and infrared domains, said domains being defined as follows by their wavelength. Ultraviolet: 10 nm <λ <400 nm; visible: 400 nm <λ <700 nm and infrared: 0.7 μm <λ <0.1 mm. In a first embodiment of the invention shown in FIGS. 4A, 4B and 4C, these means are dopants 17 of silicon.
Dans un cristal de silicium intrinsèque, les atomes sont en totalité ou en quasi-totalité des atomes de silicium. Ainsi que cela est montré à la figure 5A, un tel cristal de silicium intrinsèque est, à 300 degrés Kelvin, opaque aux rayonnements électromagnétiques de la majeure partie du spectre visible et ultraviolet dont la longueur d'onde est supérieure à 0,7 μm avec un coefficient d'absorption supérieur àIn an intrinsic silicon crystal, the atoms are wholly or almost all of the silicon atoms. As shown in FIG. 5A, such an intrinsic silicon crystal is, at 300 degrees Kelvin, opaque to electromagnetic radiation from most of the visible and ultraviolet spectrum whose wavelength is greater than 0.7 μm with an absorption coefficient greater than
100 cm"1. Toutefois, ce coefficient d'absorption décroît largement pour des valeurs de longueur d'onde supérieures à 1 μm, c'est-à-dire pour la partie du spectre électromagnétique correspondant sensiblement au domaine des infrarouges. Les rayonnements infrarouges pénètrent donc le silicium intrinsèque.100 cm " 1. However, this absorption coefficient decreases widely for values of wavelength greater than 1 μm, that is to say for the part of the electromagnetic spectrum corresponding substantially to the infrared domain. Infrared radiation therefore penetrate intrinsic silicon.
Or, ainsi que cela est montré à la figure 5B, en présence de dopants 17 à raison de Nd = 1019 atomes par cm3, le coefficient d'absorption de la lumière reste supérieur à 100 cm-1, non seulement pour les longueurs d'onde inférieures à 1 μm, mais aussi, pour les longueurs d'onde supérieures à cette valeur. On note même que le coefficient d'absorption augmente pour des longueurs d'onde croissantes de 1 à 10 μm.However, as shown in FIG. 5B, in the presence of dopants 17 at the rate of Nd = 10 19 atoms per cm 3 , the light absorption coefficient remains greater than 100 cm -1 , not only for the lengths wavelengths below 1 μm, but also for wavelengths above this value. We even note that the absorption coefficient increases for wavelengths increasing from 1 to 10 μm.
Aussi, les dopants, utilisés classiquement pour modifier les propriétés semi-conductrices du silicium, sont à même de modifier les propriétés d'absorption d'un cristal intrinsèque de silicium de manière que son coefficient d'absorption augmente sensiblement pour des longueurs d'onde supérieures à 1 μm, c'est-à-dire en particulier pour des longueurs d'onde du domaine infrarouge.Also, dopants, conventionally used to modify the semiconductor properties of silicon, are capable of modifying the absorption properties of an intrinsic silicon crystal so that its absorption coefficient increases appreciably for wavelengths. greater than 1 μm, that is to say in particular for wavelengths in the infrared range.
Selon l'invention, les dopants 17 sont des atomes de nature chimique différente de celle du silicium dont la présence est à l'origine de défauts dans sa maille cristalline. Il s'agit par exemple du Phosphore ou du Bore. Le nombre d'atomes dopants présents dans le silicium est compris entre 1017 et 1020 atomes par cm3 préférentiellement de l'ordre de 1019 atomes par cm3. L'absorption de la lumière pour une longueur d'onde et une épaisseur données est d'autant plus efficace que le niveau de dopage est élevé. Ces dopants 17 peuvent être incorporés dans la maille cristalline lors de la croissance du cristal de silicium, ou alors, faire l'objet d'une diffusion à haute température sous atmosphère neutre ou encore par implantation ionique.According to the invention, the dopants 17 are atoms of a chemical nature different from that of silicon, the presence of which is the cause of defects in its crystal lattice. It is for example Phosphorus or Boron. The number of doping atoms present in silicon is between 10 17 and 10 20 atoms per cm 3 preferably of the order of 10 19 atoms per cm 3 . The absorption of light for a given wavelength and thickness is all the more effective the higher the doping level. These dopants 17 can be incorporated into the crystal lattice during the growth of the silicon crystal, or else be subject to diffusion at high temperature under neutral atmosphere or even by ion implantation.
Ces dopants 17 peuvent être présents dans la couche de substrat silicium 12 d'une puce 5 du premier type ou d'une puce 5 du second type. Ils peuvent aussi être incorporés dans la couche complémentaire 14 d'une puce 5 du second type.These dopants 17 may be present in the silicon substrate layer 12 of a chip 5 of the first type or of a chip 5 of the second type. They can also be incorporated into the complementary layer 14 of a chip 5 of the second type.
A la variante de la figure 4A, qui montre une puce 5 du second type, les dopants 17 sont présents dans la couche complémentaire 14 de la puce 5. Ils sont répartis dans cette couche 14 de manière homogène. Ils peuvent néanmoins être localisés uniquement dans une partie de l'épaisseur de ladite couche 14, en particulier dans la partie de cette couche proche de sa face de dessus 18.In the variant of FIG. 4A, which shows a chip 5 of the second type, the dopants 17 are present in the complementary layer 14 of the chip 5. They are distributed in this layer 14 in a homogeneous manner. They can nevertheless be located only in part of the thickness of said layer 14, in particular in the part of this layer close to its top face 18.
A la variante de la figure 4B, qui montre une puce 5 du premier type, les dopants 17 sont présents dans la couche de substrat 12 de la puce 5. Ces dopants sont localisés dans la partie arrière de ladite couche 12. Ainsi, les effets des dopants sur la conduction électrique ne perturbent pas le bon fonctionnement des circuits intégrés à la face active 13 de la puce 5. A la variante de la figure 4C, qui montre une puce 5 du second type, les dopants 17 sont présents à la fois dans la couche de substrat 12 de la puce et dans sa couche complémentaire 14.In the variant of FIG. 4B, which shows a chip 5 of the first type, the dopants 17 are present in the substrate layer 12 of the chip 5. These dopants are located in the rear part of said layer 12. Thus, the effects dopants on the electrical conduction do not disturb the proper functioning of the circuits integrated into the active face 13 of the chip 5. In the variant of FIG. 4C, which shows a chip 5 of the second type, the dopants 17 are present at the same time in the substrate layer 12 of the chip and in its complementary layer 14.
Dans un second mode de réalisation de l'invention montré aux figures 6A, 6B et 6C les moyens de protection physique contre l'action de la lumière sont formés d'irrégularités de surface 20 apparentes à une face d'une couche de silicium. Ces irrégularités de surface peuvent être apparentes à la face arrière du substrat silicium ou à l'une ou aux deux faces de dessus et de dessous de la couche complémentaire 14 pour les puces 5 du second type. Ces irrégularités de surface 20 sont constituées par exemple par des creux et bosses ménagées sur toute la surface considérée de la couche de substrat ou complémentaire. La hauteur de ces creux et bosses est de l'ordre de quelques microns.In a second embodiment of the invention shown in FIGS. 6A, 6B and 6C, the means of physical protection against the action of light are formed by surface irregularities 20 apparent to a face of a layer of silicon. These surface irregularities may be apparent on the rear face of the silicon substrate or on one or both of the top and bottom faces of the complementary layer 14 for chips 5 of the second type. These surface irregularities 20 consist for example of hollows and bumps formed over the entire surface considered of the substrate or complementary layer. The height of these hollows and bumps is of the order of a few microns.
En pratique, ces irrégularités 20 sont formées par gravure du silicium par exemple au moyen de techniques sèches, comme l'abrasion mécanique, ou humides, comme l'usinage KOH.In practice, these irregularities are formed by etching the silicon, for example using dry techniques, such as mechanical abrasion, or wet techniques, such as KOH machining.
Les rayonnements électromagnétiques focalisés incidents et notamment lesdits rayonnements électromagnétiques dont la longueur d'onde est supérieure à 1 μm, en particulier les rayonnements infrarouges, se réfléchissent en partie sur les parois irrégulières du silicium et font l'objet, en partie, d'une réfraction. Ainsi réfléchis, atténués et diffusés, les rayonnements n'atteignent plus les cibles recherchées par le fraudeur sans que ce dernier puisse prévoir quelles sont les cibles finalement atteintes. Les attaques sont rendues impossibles.Incident focused electromagnetic radiation and in particular said electromagnetic radiation whose wavelength is greater than 1 μm, in particular infrared radiation, is partly reflected on the irregular walls of silicon and is subject, in part, to a refraction. Thus reflected, attenuated and diffused, the radiation no longer reaches the targets sought by the fraudster without the latter being able to predict which targets are ultimately reached. Attacks are made impossible.
A la variante de la figure 6A, qui montre une puce 5 du second type, les irrégularités 20 sont ménagées à la face de la couche complémentaire 14 en contact avec la couche de scellement 15.In the variant of FIG. 6A, which shows a chip 5 of the second type, the irregularities 20 are formed on the face of the complementary layer 14 in contact with the sealing layer 15.
A la variante de la figure 6B, qui montre une puce 5 du premier type, les irrégularités 20 sont ménagées à la face arrière de la couche substrat silicium.In the variant of FIG. 6B, which shows a chip 5 of the first type, the irregularities 20 are formed on the rear face of the silicon substrate layer.
A la variante de la figure 6C, qui montre une puce 5 du second type, les irrégularités 20 sont ménagées à la face 18 de la couche complémentaire . A la variante de la figure 6D, qui montre une puce 5 du second type, les irrégularités 20 sont ménagées à la face de dessus 18 de la couche complémentaire 14, à sa face de dessous 19 et à la face arrière 6 de la puce 3. Dans un troisième mode de réalisation de l'invention montré aux figures 7A, 7B et 7C, les moyens de protection physiques sont formés par une couche métallique 21 assemblée sur au moins une des faces des couches de substrat 12 ou complémentaire 14 silicium et dont l'épaisseur est supérieure à 50 Angstrôm, par exemple de l'ordre de 100 Angstrôms.In the variant of FIG. 6C, which shows a chip 5 of the second type, the irregularities 20 are formed on the face 18 of the complementary layer. In the variant of FIG. 6D, which shows a chip 5 of the second type, the irregularities 20 are formed on the top face 18 of the complementary layer 14, on its bottom face 19 and on the rear face 6 of the chip 3 In a third embodiment of the invention shown in FIGS. 7A, 7B and 7C, the physical protection means are formed by a metal layer 21 assembled on at least one of the faces of the layers of substrate 12 or complementary 14 silicon and whose the thickness is greater than 50 Angstroms, for example of the order of 100 Angstroms.
Il s'agit par exemple d'une couche d'aluminium, de palladium ou d'une couche formée d'une superposition de sous-couches métalliques par exemple de Nickel, de chrome et d'or.It is for example a layer of aluminum, palladium or a layer formed by a superposition of metallic sublayers, for example of nickel, chromium and gold.
La métallisation d'une face peut être effectuée par dépôt sous vide.The metallization of a face can be carried out by vacuum deposition.
La couche de métal réfléchit ou absorbe l'ensemble de la lumière incidente destinée à éclairer le circuits. Il n'est plus possible d'inspecter à l'aide d'un microscope optique la surface active du circuit intégré ni même d'observer à l'aide de techniques infrarouges. A la variante de la figure 7A, qui montre une puce du second type, la couche métallique 21 est placée entre la couche complémentaire 14 et la couche de scellement 15.The metal layer reflects or absorbs all of the incident light intended to illuminate the circuits. It is no longer possible to inspect the active surface of the integrated circuit using an optical microscope or even to observe using infrared techniques. In the variant of FIG. 7A, which shows a chip of the second type, the metal layer 21 is placed between the complementary layer 14 and the sealing layer 15.
A la variante de la figure 7B, qui montre une puce du premier type, la couche métallique 21 est placée a la face arrière de la couche substrat 12.In the variant of FIG. 7B, which shows a chip of the first type, the metal layer 21 is placed on the rear face of the substrate layer 12.
A la variante de la figure 7C, qui montre une puce 3 du second type, la couche métallique 21 est placée à la face de dessus 18 de la couche complémentaire 14.In the variant of FIG. 7C, which shows a chip 3 of the second type, the metal layer 21 is placed on the top face 18 of the complementary layer 14.
A la variante de la figure 7D, qui montre une puce 3 du second type, une première couche métallique est placée entre le couche complémentaire 14 et la couche scellement 15 et à la face arrière de la couche de substrat 12.In the variant of FIG. 7D, which shows a chip 3 of the second type, a first metallic layer is placed between the layer complementary 14 and the sealing layer 15 and to the rear face of the substrate layer 12.
Bien entendu, l'invention ne se limite pas aux variantes précitées. En outre, il est possible d'utiliser différents moyens de protection dans une même puce 5.Of course, the invention is not limited to the aforementioned variants. In addition, it is possible to use different protection means in the same chip 5.
On notera que la mise en place d'une couche complémentaire sur la face active d'une puce de type 1 et/ ou la mise en place des moyens physiques précités de protection des circuits contre l'action de la lumière peuvent intervenir dans des étapes ultérieures à celles classique de production des circuits intégrés. De ce fait, les filières de productions classiques des puces sont conservées. Par ailleurs, une puce de l'invention, qu'elle soit du premier type ou du second, a sensiblement les mêmes dimensions que les puces classiques de l'état de la technique. Aussi, les filières de fabrication de modules avec des puces de l'invention sont de même conservées.It will be noted that the establishment of an additional layer on the active face of a type 1 chip and / or the establishment of the aforementioned physical means of protecting the circuits against the action of light can occur in stages. subsequent to the conventional production of integrated circuits. As a result, the traditional chip production chains are preserved. Furthermore, a chip of the invention, whether of the first type or of the second, has substantially the same dimensions as the conventional chips of the prior art. Also, the modules manufacturing channels with chips of the invention are similarly preserved.
On notera par ailleurs que les moyens physiques de protection contre l'action de la lumière sont susceptibles de recouvrir l'ensemble des circuits intégrés, ou alors, certaines parties desdits circuits. Dans le cas où seulement certaines parties desdits circuits sont recouvertes, il s'agira avantageusement de parties clés, c'est-à-dire sensibles aux attaques par la lumière et dont une perturbation par ladite lumière pourrait s'avérer dangereuse pour l'intégrité de la puce et des secrets qu'elle comporte. Notamment, de telles parties clés sont constituées par le multiplieur de tension utilisé pour la programmation des cellules mémoires EEPROM, les amplificateurs de lecture du contenu des mémoires et certains registres de la mémoire volatile (RAM) ou de l'unité centrale de traitement (CPU). It will also be noted that the physical means of protection against the action of light are capable of covering all of the integrated circuits, or else, certain parts of said circuits. In the case where only certain parts of said circuits are covered, they will advantageously be key parts, that is to say sensitive to attacks by light and of which a disturbance by said light could prove to be dangerous for the integrity of the chip and the secrets it contains. In particular, such key parts are constituted by the voltage multiplier used for programming the EEPROM memory cells, the amplifiers for reading the contents of the memories and certain registers of the volatile memory (RAM) or of the central processing unit (CPU). ).

Claims

REVENDICATIONS
1. Puce (5) pour objet portatif à puce notamment au format carte, comprenant, d'une part, une couche de substrat silicium (12) à la face active (13) de laquelle sont intégrés des circuits définissant une unité centrale de traitement ainsi que des mémoires, et d'autre part, une couche complémentaire (14) de silicium couvrant au moins en partie ladite face active (13) caractérisée en ce qu'elle comporte en outre des moyens physiques (17, 20, 21) de protection contre l'action de rayonnements électromagnétiques du domaine infrarouge dont la longueur d'onde est supérieure à 1 μm.1. Chip (5) for portable smart object, in particular in card format, comprising, on the one hand, a layer of silicon substrate (12) on the active face (13) of which are integrated circuits defining a central processing unit as well as memories, and on the other hand, a complementary layer (14) of silicon covering at least partially said active face (13) characterized in that it also comprises physical means (17, 20, 21) of protection against the action of electromagnetic radiation from the infrared range whose wavelength is greater than 1 μm.
2. Puce (5) selon la revendication 1, caractérisée en ce que les moyens physiques (17, 20, 21) sont des moyens physiques de protection contre l'action de rayonnements électromagnétiques du domaine infrarouge.2. Chip (5) according to claim 1, characterized in that the physical means (17, 20, 21) are physical means of protection against the action of electromagnetic radiation from the infrared domain.
3. Puce (5) selon la revendication 2, caractérisée en ce que les moyens physiques (17, 20, 21) sont des moyens physiques de protection contre l'action de rayonnements électromagnétiques des domaines ultraviolet, visible et infrarouge. 3. Chip (5) according to claim 2, characterized in that the physical means (17, 20, 21) are physical means of protection against the action of electromagnetic radiation from the ultraviolet, visible and infrared domains.
4. Puce (5) selon l'une des revendications 1, 2 ou 3, caractérisée en ce que la couche complémentaire (14) de silicium est scellée à la face active (13) de la couche de substrat silicium (12) par une couche de scellement (15).4. Chip (5) according to one of claims 1, 2 or 3, characterized in that the complementary layer (14) of silicon is sealed to the active face (13) of the layer of silicon substrate (12) by a sealing layer (15).
5. Puce (5) selon l'une des revendications précédentes, caractérisée en ce que les moyens physiques de protection contre l'action de rayonnements électromagnétiques sont des dopants (17) du silicium.5. Chip (5) according to one of the preceding claims, characterized in that the physical means of protection against the action of electromagnetic radiation are dopants (17) of silicon.
6. Puce (5) selon la revendication 5, caractérisée en ce que le nombre de dopants (17) du silicium présents est compris entre 1017 et 1020 atomes par cm3, préférentiellement de l'ordre de 1019 atomes par cm3.6. Chip (5) according to claim 5, characterized in that the number of dopants (17) of silicon present is between 10 17 and 10 20 atoms per cm 3 , preferably around 10 19 atoms per cm 3 .
7. Puce (5) selon l'une des revendications 5 ou 6, caractérisée en ce que les dopants (17) du silicium sont le Phosphore ou le Bore. 7. Chip (5) according to one of claims 5 or 6, characterized in that the dopants (17) of silicon are Phosphorus or Boron.
8. Puce (5) selon l'une des revendications 5, 6 ou 7, caractérisée en ce que les dopants (17) du silicium sont présents dans la couche de substrat silicium (12), dans sa partie opposée à sa face active (13).8. Chip (5) according to one of claims 5, 6 or 7, characterized in that the dopants (17) of silicon are present in the layer of silicon substrate (12), in its part opposite to its active face ( 13).
9. Puce (5) selon l'une des revendications 5 à 8, caractérisée en ce que les dopants (17) du silicium sont présents dans la couche complémentaire (14) de silicium.9. Chip (5) according to one of claims 5 to 8, characterized in that the dopants (17) of silicon are present in the complementary layer (14) of silicon.
10. Puce (5) selon l'une des revendications précédentes, caractérisée en ce que les moyens physiques de protection contre l'action des rayonnements électromagnétiques sont formés d'irrégularités de surface (20). 10. Chip (5) according to one of the preceding claims, characterized in that the physical means of protection against the action of electromagnetic radiation are formed of surface irregularities (20).
11. Puce (5) selon la revendication 10, caractérisée en ce que les irrégularités de surface (20) sont ménagées à la face arrière (6) de la couche de substrat silicium (12) opposée à sa face active (13).11. Chip (5) according to claim 10, characterized in that the surface irregularities (20) are formed on the rear face (6) of the layer of silicon substrate (12) opposite its active face (13).
12. Puce (5) selon l'une des revendications 10 ou 11 , caractérisée en ce que les irrégularités de surface (20) sont ménagées à la face de dessous (19) de la couche complémentaire (14).12. Chip (5) according to one of claims 10 or 11, characterized in that the surface irregularities (20) are formed on the underside (19) of the complementary layer (14).
13. Puce (5) selon l'une des revendications 10, 11 ou 12, caractérisée en ce que les irrégularités de surface (20) sont ménagées à la face de dessus (18) de la couche complémentaire (14).13. Chip (5) according to one of claims 10, 11 or 12, characterized in that the surface irregularities (20) are formed on the top face (18) of the complementary layer (14).
14. Puce (5) selon l'une des revendications précédentes, caractérisée en ce que moyens physiques de protection contre l'action des rayonnements électromagnétiques sont formés d'au moins une couche métallique (21).14. Chip (5) according to one of the preceding claims, characterized in that physical means of protection against the action of electromagnetic radiation are formed of at least one metal layer (21).
15. Puce (5) selon la revendication 14, caractérisée en ce que la couche métallique (21) a une épaisseur supérieure à 50 Angstrôm, préférentiellement de l'ordre de 100 Angstrôms. 15. Chip (5) according to claim 14, characterized in that the metal layer (21) has a thickness greater than 50 Angstroms, preferably of the order of 100 Angstroms.
16. Puce (5) selon l'une des revendications 14 ou 15, caractérisée en ce que la couche métallique (21) est placée à la face de dessous (19) de la couche complémentaire (14).16. Chip (5) according to one of claims 14 or 15, characterized in that the metal layer (21) is placed on the underside (19) of the complementary layer (14).
17. Puce (5) selon l'une des revendications 14, 15 ou 16, caractérisée en ce que la couche métallique (21) est placée à la face de dessus (18) de la couche complémentaire (14).17. Chip (5) according to one of claims 14, 15 or 16, characterized in that the metal layer (21) is placed on the top face (18) of the complementary layer (14).
18. Puce (5) selon l'une des revendications 14 à 17, caractérisée en ce que la couche métallique (21) est placée à la face arrière (6) de la couche de substrat silicium (12). 18. Chip (5) according to one of claims 14 to 17, characterized in that the metal layer (21) is placed on the rear face (6) of the silicon substrate layer (12).
EP99947524A 1998-10-16 1999-10-08 Integrated circuit chip made secure against the action of electromagnetic radiation Withdrawn EP1127376A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9813029 1998-10-16
FR9813029A FR2784768A1 (en) 1998-10-16 1998-10-16 Protecting integrated circuits on cards from the effects of electromagnetic radiation by using silica doped with Phosphorus or Boron or an irregular surface or metallic screening
PCT/FR1999/002428 WO2000024058A1 (en) 1998-10-16 1999-10-08 Integrated circuit chip made secure against the action of electromagnetic radiation

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EP1127376A1 true EP1127376A1 (en) 2001-08-29

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10147140A1 (en) 2001-09-25 2003-04-17 Giesecke & Devrient Gmbh Chip card with display
JP2004341895A (en) * 2003-05-16 2004-12-02 Sony Corp Ic card
JP4680763B2 (en) * 2005-12-16 2011-05-11 住友電工デバイス・イノベーション株式会社 Electronic device and semiconductor device
CN104376357A (en) * 2014-08-27 2015-02-25 北京中电华大电子设计有限责任公司 Light attack resisting method for intelligent card
FR3027705B1 (en) * 2014-10-27 2017-12-22 Oberthur Technologies MICROCIRCUIT MODULE, METHOD FOR MANUFACTURING MICROCIRCUIT MODULE, ELECTRONIC DEVICE COMPRISING SUCH A MODULE
CN105715032B (en) * 2016-04-15 2017-09-29 中国五冶集团有限公司 It is a kind of that there is the construction hanging basket for crossing over locomotive function and moving method is crossed over
WO2021022566A1 (en) * 2019-08-08 2021-02-11 深圳市汇顶科技股份有限公司 Security chip, preparation method for security chip, and electronic device
US20210125959A1 (en) * 2019-10-24 2021-04-29 Texas Instruments Incorporated Metal-covered chip scale packages

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4821363B1 (en) * 1967-12-31 1973-06-28
US4712129A (en) * 1983-12-12 1987-12-08 Texas Instruments Incorporated Integrated circuit device with textured bar cover
US4970565A (en) * 1988-09-01 1990-11-13 Atmel Corporation Sealed charge storage structure
JPH0521655A (en) * 1990-11-28 1993-01-29 Mitsubishi Electric Corp Semiconductor device and package therefor
US5714802A (en) * 1991-06-18 1998-02-03 Micron Technology, Inc. High-density electronic module
JP3048429B2 (en) * 1991-08-14 2000-06-05 株式会社東芝 Semiconductor integrated circuit device
US5213989A (en) * 1992-06-24 1993-05-25 Motorola, Inc. Method for forming a grown bipolar electrode contact using a sidewall seed
KR100294026B1 (en) * 1993-06-24 2001-09-17 야마자끼 순페이 Electro-optical device
US5534056A (en) * 1993-10-28 1996-07-09 Manfred R. Kuehnle Composite media with selectable radiation-transmission properties
FR2727227B1 (en) * 1994-11-17 1996-12-20 Schlumberger Ind Sa ACTIVE SECURITY DEVICE WITH ELECTRONIC MEMORY
JPH09148620A (en) * 1995-09-20 1997-06-06 Sharp Corp Light reflecting type detector and manufacture thereof
US5804827A (en) * 1995-10-27 1998-09-08 Nikon Corporation Infrared ray detection device and solid-state imaging apparatus
JPH10270605A (en) * 1997-03-25 1998-10-09 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPH10270562A (en) * 1997-03-27 1998-10-09 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit
US6229165B1 (en) * 1997-08-29 2001-05-08 Ntt Electronics Corporation Semiconductor device
US6245663B1 (en) * 1998-09-30 2001-06-12 Conexant Systems, Inc. IC interconnect structures and methods for making same
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0024058A1 *

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WO2000024058A1 (en) 2000-04-27
US8138566B1 (en) 2012-03-20
JP4694693B2 (en) 2011-06-08
FR2784768A1 (en) 2000-04-21
CN1323448A (en) 2001-11-21
CN1217411C (en) 2005-08-31

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