EP0851480B1 - Stress-adjusted insulating film forming method, semiconductor device and method of manufacturing the same - Google Patents

Stress-adjusted insulating film forming method, semiconductor device and method of manufacturing the same Download PDF

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Publication number
EP0851480B1
EP0851480B1 EP97112763A EP97112763A EP0851480B1 EP 0851480 B1 EP0851480 B1 EP 0851480B1 EP 97112763 A EP97112763 A EP 97112763A EP 97112763 A EP97112763 A EP 97112763A EP 0851480 B1 EP0851480 B1 EP 0851480B1
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EP
European Patent Office
Prior art keywords
stress
insulating film
film
adjusted
film forming
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EP97112763A
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German (de)
French (fr)
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EP0851480A2 (en
EP0851480A3 (en
Inventor
Yuhko Nishimoto
Kazuo Maeda
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Semiconductor Process Laboratory Co Ltd
Canon Marketing Japan Inc
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Semiconductor Process Laboratory Co Ltd
Canon Marketing Japan Inc
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
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Definitions

  • the present invention relates to a stress-adjusted insulating film forming method, according to claim 1. More particularly, it relates to a method of forming stress-adjusted insulating films which are interposed between respective metal interconnection layers upon laminating three or more metal interconnection layers.
  • a combination of plural insulating films consisting of an insulating film with good film quality and an insulating film with good step coverage may be employed.
  • a combination of the plasma CVD film and the TEOS/O 3 thermal CVD film or SOG film is often recommended.
  • the plasma CVD method and the thermal CVD method or the coating method may be employed in combination.
  • the plasma CVD film since in general the plasma CVD film has good film quality, it can be used by itself as the interlayer insulating film under the assumption that it is followed by the planarization such as CMP method, etching-back method, etc.
  • the high density plasma CVD film is suited for such interlayer insulating film application since it has excellent step coverage.
  • the interlayer insulating film is formed by virtue of ECR, ICP, high density plasma CVD method such as helicon plasma, etc., and then a surface of the interlayer insulating film is planarized by virtue of CMP (Chemical Mechanical Polishing) method or etching-back method.
  • CMP Chemical Mechanical Polishing
  • FIGS.1A to 1D Combinations of the above various insulating films which can be used as the interlayer insulating film may be briefed as follows. Illustrative examples which have been used as the interlayer insulating films between four-layered interconnections are shown in FIGS.1A to 1D.
  • EP-A- 0 307 099 and US-A-5500312 disclose multilayer structures with low stress.
  • EP-A-0 470 632 describes plasma irradiation techniques.
  • an insulating film having a tensile stress and an insulating film having compressive stress are alternately deposited on a substrate to form the stress-adjusted insulating film consisting of the laminated insulating films, as defined in the appending claims.
  • a stress value of the insulating film can be adjusted by adjusting a thickness of the insulating film to be formed, or by adjusting type of film forming gas or film forming conditions (e.g., frequency of plasma generating power, bias power applied to the substrate, heating temperature of the substrate, type of gas, flow rate of gas, etc.).
  • stress of the overall interlayer insulating films can be calculated with good precision by making use of a calculation equation whose good precision has been confirmed experimentally.
  • the stress-adjusted insulating film (interlayer insulating film) can be formed to cover the interconnection, based on the above stress-adjusted insulating film forming method.
  • the interconnections can be laminated as the multi-layered structure via the interlayer insulating film whose stress is adjusted, whereby resulting in the higher integration density of the semiconductor device.
  • step (b) a method of forming a sample used in the experiment will be explained. Seven type of samples (S1 to S7) shown in FIGS.3A to 3F have been used. Though locking a step of irradiating the insulating film having tensile stress with a plasma to shift stress in said film do more tensile (step (b)), these examples are in generale suitable to illustrate the lamination of multiple insulating layers having tensile and compressive stress, respectively.
  • FIG.3A A laminated structure of the sample S1 is shown in FIG.3A. Characteristics of respective layers in the sample S1 such as type of insulating film, film thickness, total stress, and generation of crack are indicated in Table III.
  • the insulating film formed by the plasma CVD method will be called a PECVD film (plasma CVD film) hereinafter, and the insulating film formed by the thermal CVD method will be called a THCVD film (thermal CVD film) hereinafter.
  • total stress indicated in Table III means stress generated in the overall insulating films after respective insulating films have been laminated, which is calculated according to an amount of bowing generated after respective insulating films have been laminated on a silicon wafer.
  • film forming conditions for the plasma CVD film except for a film forming time are common throughout all laminated layers, and they are set forth hereunder.
  • Film forming gas (Flow rate sccm) TMS(15 sccm)+N 2 O(450 sccm) Pressure 0.7 Torr Plasma generating power 150 W Frequency 13.56 MHz Bias power 150 W Frequency 380 kHz Substrate temperature (Film forming temperature) 330 °C Film forming rate 150 nm/min
  • a silicon oxide film having compressive stress of -3.3 ⁇ 10 9 dyne/cm 2 can be formed.
  • film forming conditions of the thermal CVD film except for a film forming time are common in respective layers, which are set forth hereunder.
  • Film forming gas Flow rate sccm
  • Substrate temperature (Film forming temperature) 400 °C Film forming rate 87 nm/min
  • a silicon oxide film having tensile stress of +2.2 ⁇ 10 9 dyne/cm 2 can be formed.
  • TMS trimethoxysilane: HSi(OCH 3 ) 3
  • TEOS tetraethylorthosilicate: Si(OC 2 H 5 ) 4
  • oxygen containing gas has been employed as the oxygen containing gas.
  • the oxygen containing gas may be formed of any of N 2 O, NO 2 , CO, CO 2 , and H 2 O.
  • FIG.3B A laminated structure of the sample S2 is shown in FIG.3B.
  • Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S2 are indicated in Table IV.
  • film forming conditions of the plasma CVD film other than a film forming time are common throughout all laminated layers, and they are set identically to the case where the sample S1 is formed.
  • film forming conditions of the thermal CVD film other than a film forming time are common in respective layers, and they are set identically to the case where the sample S1 is formed.
  • a laminated structure of the sample S3 is also shown in FIG.3B.
  • Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S3 are indicated in Table V.
  • film forming conditions of the plasma CVD film except for a film forming time are common throughout all laminated layers, and they are identical to the case where the sample S1 is formed.
  • film forming conditions of the thermal CVD film except for a film forming time are common in respective layers, and they are identical to the case where the sample S1 is formed.
  • FIG.3C A laminated structure of the sample S4 is shown in FIG.3C.
  • Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S4 are indicated in Table VI.
  • film forming conditions of the thermal CVD film other than a film forming time are common in respective layers, which are identical to the case where the sample S1 is formed.
  • FIG.3D A laminated structure of the sample S5 is shown in FIG.3D.
  • Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S5 are indicated in Table VII.
  • film forming conditions of the plasma CVD film other than a film forming time are common throughout all laminated layers, which are set to be identical to the case where the sample S1 is formed.
  • film forming conditions of the thermal CVD film other than a film forming time are common in respective layers, which are set to be identical to the case where the sample S1 is formed.
  • FIG.3E A laminated structure of the sample S6 is shown in FIG.3E.
  • Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S6 are indicated in Table VIII.
  • film forming conditions of the plasma CVD film other than a film forming time are common in respective layers, and they are set identically to the case where the sample S1 is formed.
  • film forming conditions of the thermal CVD film other than a film forming time are common in respective layers and they are set identically to the case where the sample S1 is formed.
  • FIG.3F A laminated structure of the sample S7 is shown in FIG.3F.
  • Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S7 are indicated in Table IX.
  • film forming conditions of the thermal CVD film other than a film forming time are common in respective layers, which are identical to the case where the sample S1 is formed.
  • FIGS.4A and 4B when change in stress is summarized in the samples S1 to S3 respectively based on stress values indicated in above Tables III to V after respective insulating layers have been laminated.
  • FIG. 4 is a characteristic view showing change in stress before and after humidity absorption, wherein an ordinate shows the average stress value ( ⁇ 10 9 dyne/cm 2 ) caused in the laminated films on a linear scale and an abscissa shows the time interval before and after humidity absorption.
  • an ordinate shows the average stress value ( ⁇ 10 9 dyne/cm 2 ) caused in the laminated films on a linear scale
  • an abscissa shows the time interval before and after humidity absorption.
  • n is the total laminated number
  • t i is a thickness of i-th insulating film (cm)
  • ⁇ i stress in i-th insulating film (dyne/cm 2 ).
  • type of stress of the insulating film it is assumed that the tensile stress is positive and the compressive stress is negative.
  • a stress range not to generate the cracks is less than about +3 ⁇ 10 5 dyne/cm. If stress of the silicon oxide film formed by the thermal CVD method is assumed as 2 ⁇ 10 9 dyne/cm 2 , this corresponds to about 1.5 ⁇ m in terms of the thickness of the silicon oxide film formed by the thermal CVD method.
  • stress of the overall laminated films calculated by the equation is set to a stress limit (+3 ⁇ 10 5 dyne/cm on an Si film, or +2 ⁇ 10 5 dyne/cm on an aluminum film) and then thickness and stress of individual insulating films are determined not to exceed this stress limit, cracks in the interlayer insulating films can be prevented.
  • stress in the insulating film formed by the plasma CVD method and stress in the insulating film formed by the thermal CVD method can be adjusted as explained hereunder and known to a skilled worker.
  • stress in the insulating film formed by the plasma CVD method can as is known to a skilled worker be adjusted according to type of gas, flow rate of gas, frequency of plasma generating power, bias power applied to the substrate, film forming temperature, etc.
  • Experimental examples are shown in FIGS. 5A to 5E. Although TEOS+O 2 system reaction gas has been employed in the experimental examples, stress may be adjusted in a similar manner when TMS+N 2 O system reaction gas is employed.
  • stress in the insulating film formed by the thermal CVD method can be adjusted by known methods according to type of gas, flow rate of gas (including ozone concentration in oxygen), film forming temperature, film forming rate, etc. Experimental examples are shown in FIGS. 6A o 6C.
  • the TEDS+O 3 reaction gas has been employed as the film forming gas.
  • stress in the insulating film formed by the thermal CVD method is often shifted to the compressive stress side because of humidity absorption after formation. Therefore, if moisture is removed from the insulating film by virtue of plasma irradiation according to the invention stress in the insulating film can be shifted to the tensile stress side. As a result, it is possible to stabilize stress in the insulating film.
  • FIG. 7 shows an example of a semiconductor device in which a four-layered interconnections are formed for illustration purposes.
  • the interlayer insulating films formed according to the method of manufacturing the interlayer insulating film of the present invention are interposed respectively between neighboring two interconnections of the four layered interconnections.
  • Film forming gas and film forming conditions used in the plasma CVD method and the thermal CVD method are selected identically to those explained in forming the sample S1 in the first embodiment.
  • interconnections 33a, 33b made of an aluminum film having a thickness of 0.7 ⁇ m are formed on a substrate 31.
  • a silicon oxide film 34a of 0.2 ⁇ m thickness is formed by virtue of the plasma CVD method to cover the interconnections 33a, 33b.
  • a silicon oxide film 35a of 0.5 ⁇ m thickness is formed on the silicon oxide film 34a by virtue of the thermal CVD method.
  • a silicon oxide film 34b of 0.9 ⁇ m thickness is formed on the silicon oxide film 35a by virtue of the plasma CVD method.
  • a surface of the silicon oxide film 34b is planarized by polishing the silicon oxide film 34b by virtue of CMP method (Chemical Mechanical Polishing Method).
  • CMP method Chemical Mechanical Polishing Method
  • second-layered interconnections 33c, 33d made of an aluminum film having a thickness of 0.95 ⁇ m are formed on the planarized silicon oxide film 34b.
  • a second-layered interlayer insulating film 2L having a thickness of 1.85 ⁇ m is formed by repeating the above steps.
  • the second-layered interlayer insulating film 2L consists of a silicon oxide film 34c of 0.1 ⁇ m thickness formed by the plasma CVD method, a silicon oxide film 35b of 0.45 ⁇ m thickness formed by the thermal CVD method, and a silicon oxide film 34d of 1.3 ⁇ m thickness formed by the plasma CVD method.
  • third-layered interconnections 33e, 33f made of an aluminum film having a thickness of 0.95 ⁇ m and a third-layered interlayer insulating film 3L having a thickness of 1.85 ⁇ m are formed in this order on the second-layered interlayer insulating film 2L.
  • the third-layered interlayer insulating film 3L consists of a silicon oxide film 34e of 0.1 ⁇ m thickness formed by the plasma CVD method, a silicon oxide film 35c of 0.45 ⁇ m thickness formed by the thermal CVD method, and a silicon oxide film 34f of 1.3 ⁇ m thickness formed by the plasma CVD method.
  • fourth-layered interconnections 33g, 33h made of an aluminum film having a thickness of 0.95 ⁇ m and a fourth-layered covering insulating film 4L having a thickness of 1.85 ⁇ m are formed in this order on the third-layered interlayer insulating film 3L.
  • the covering insulating film 4L consists of a silicon oxide film 34g of 0.1 ⁇ m thickness formed by the plasma CVD method, a silicon oxide film 35d of 0.45 ⁇ m thickness formed by the thermal CVD method, and a silicon oxide film 34h of 1.3 ⁇ m thickness formed by the plasma CVD method.
  • interconnections With the above, four layered interconnections, three interlayer insulating films 1L to 3L which are interposed respectively between neighboring two interconnections of the four interconnections, and the covering insulating film 4L for covering the fourth layer interconnection have been formed.
  • the preselected interconnections of the interconnections are connected through via holes (not shown) formed in the interlayer insulating films 1L to 3L, into which conductive layers are buried.
  • stress of the overall laminated interlayer insulating films, etc. 1L to 4L is set not to exceed the stress limit (3 ⁇ 10 5 dyne/cm on the insulating film, 2 ⁇ 10 5 dyne/cm on the aluminum film), the arbitrary number of interconnections can be laminated without generating the crack in respective interlayer insulating films.
  • the semiconductor device having the high integration density can be accomplished.
  • interlayer insulating film forming method of the present invention multiple insulating layers whose total stress is adjusted can be formed by laminating insulating films having different stress mixedly on the substrate.

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Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to a stress-adjusted insulating film forming method, according to claim 1. More particularly, it relates to a method of forming stress-adjusted insulating films which are interposed between respective metal interconnection layers upon laminating three or more metal interconnection layers.
    • 2. Description of the Prior Art
  • In recent years, a multilayered interconnection structure in excess of three-layer has been needed with the progress of high integration density of the semiconductor device. Upper and lower interconnections and adjacent interconnections are insulated with the interlayer insulating films interposed therebetween. However, in such multilayered interconnection structure in excess of three-layer, it is extremely important to bury narrow interconnection regions with leaving no void therein and also to planarize surfaces of such buried interconnection regions.
  • In the meanwhile, as for various kinds of insulating films, their characteristics have been known for one skilled in the art, as indicated in Table I below.
    Type of insulating film Step coverage Flatness Film quality
    SOG film ○ ○ X
    TEOS/O3thermal CVD film o ○ ○ ○
    Plasma CVD film X X ○
    High density plasma CVD film o ○ X o ○
  • As one of the interlayer insulating films to be formed between multilayered interconnections in excess of three-layer, a combination of plural insulating films consisting of an insulating film with good film quality and an insulating film with good step coverage may be employed. For instance, a combination of the plasma CVD film and the TEOS/O3thermal CVD film or SOG film is often recommended. In other words, as film forming methods, the plasma CVD method and the thermal CVD method or the coating method may be employed in combination.
  • In addition, since in general the plasma CVD film has good film quality, it can be used by itself as the interlayer insulating film under the assumption that it is followed by the planarization such as CMP method, etching-back method, etc. Especially, the high density plasma CVD film is suited for such interlayer insulating film application since it has excellent step coverage. In other words, the interlayer insulating film is formed by virtue of ECR, ICP, high density plasma CVD method such as helicon plasma, etc., and then a surface of the interlayer insulating film is planarized by virtue of CMP (Chemical Mechanical Polishing) method or etching-back method.
  • Combinations of the above various insulating films which can be used as the interlayer insulating film may be briefed as follows. Illustrative examples which have been used as the interlayer insulating films between four-layered interconnections are shown in FIGS.1A to 1D.
  • 1) Plasma CVD film+SOG film (FIG.1A)
  • 2) Plasma CVD film+TEOS/O3 thermal CVD film (FIG.1B)
  • 3) Plasma CVD film alone (+CMP) (FIG.1C)
  • 4) High density plasma CVD film (+CMP) (FIG.1D)
    • In the case of 3), because the ordinary plasma CVD film is inferior in step coverage, a single plasma CVD film is scarcely used as the interlayer insulating film.
  • Meanwhile, the above various insulating films which can be used as the interlayer insulating film undergo stress, as indicated in Table II below.
    Type of insulating film Stress
    SOG film tensile stress
    TEOS/O3thermal CVD film tensile stress
    Plasma CVD film compressive stress
    High density plasma CVD film compressive stress
  • However, no account of stress caused in the overall interlayer insulating film structure has been taken up to this time. As a result, following problems have arisen. That is, in the case of 1) and 2), tensile stress is in general caused in the interlayer insulating film with good step coverage and flatness, i.e., the SOG film or the thermal CVD film (TEOS/O3thermal CVD film, etc.). In particular, in the case of thermal CVD film, cracks are generated in the film, as shown in FIG.2A, if the film thickness is made thick rather than 1.5 µm. For contrast, if the thickness of the insulating film is made excessively thin, interconnection regions cannot be buried completely by the insulating film to thus generate sharp recesses thereon, as shown in FIG.2B, so that the interconnection conductive film remains in the sharp recesses and flatness of the insulating film is spoiled. Accordingly, there are limitations to employ these insulating films as the single interlayer insulating film. Moreover, it is impossible to employ these insulating films as the interlayer insulating film for the multi-layered interconnections in excess of three layers.
  • In the case of 3) and 4), extremely large compressive stress is applied as a whole to the insulating films. In order to suppress generation of hillock of the interconnections, etc. and generation of electromigration, it is desired to cover the interconnections with the interlayer insulating film with compressive stress. However, too large compressive stress renders the wafer per se to bend physically, whereby causing problems in manufacturing or problems in device characteristics.
  • Still further, such a problem has arisen that, if a width of the interconnection is made narrow and a chip size is reduced, stress migration is caused due to stress applied to the interconnection during operation of the device. In other words, if excessively large compressive stress is caused in the insulating film which covers the interconnections such as Al film, etc., the interconnections undergo tensile stress along their grain boundaries to thus lead to breaking of interconnection. The more the layer number of the multi-layered interconnections, the higher the possibility of breaking of interconnection.
  • EP-A- 0 307 099 and US-A-5500312 disclose multilayer structures with low stress. EP-A-0 470 632 describes plasma irradiation techniques.
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide a stress-adjusted insulating film forming method capable of suppressing electromigration and stress migration in Al interconnections, bowing of wafer, or crack in interlayer insulating film while maintaining step coverage and flatness of the overall interlayer insulating film.
  • According to the stress-adjusted insulating film forming method of the present invention, an insulating film having a tensile stress and an insulating film having compressive stress are alternately deposited on a substrate to form the stress-adjusted insulating film consisting of the laminated insulating films, as defined in the appending claims.
  • Therefore, it is possible to adjust the stress of the overall multi-layered insulating films less than a limit stress value (+3×105 dyne/cm which is determined from the experiment) not to generate the cracks in the insulating films, otherwise it is possible to adjust the stress of the overall multi-layered insulating films within the stress range not to cause the curvature of the wafer, degradation in semiconductor device characteristics, etc.
  • Further, a stress value of the insulating film can be adjusted by adjusting a thickness of the insulating film to be formed, or by adjusting type of film forming gas or film forming conditions (e.g., frequency of plasma generating power, bias power applied to the substrate, heating temperature of the substrate, type of gas, flow rate of gas, etc.). In this case, stress of the overall interlayer insulating films can be calculated with good precision by making use of a calculation equation whose good precision has been confirmed experimentally.
  • In a semiconductor device the stress-adjusted insulating film (interlayer insulating film) can be formed to cover the interconnection, based on the above stress-adjusted insulating film forming method.
  • Thereby, generation of crack in the interlayer insulating film, curvature of the wafer caused by stress, degradation in semiconductor device characteristics, etc. can be prevented by adjusting stress of the interlayer insulating film appropriately. In addition to the above, stress migration and electromigration of the interconnection, e.g., the aluminum interconnection, can also be prevented by adjusting stress of the interlayer insulating film appropriately.
  • Moreover, while preventing generation of cracks in the interlayer insulating film, migration of the interconnections, etc., the interconnections can be laminated as the multi-layered structure via the interlayer insulating film whose stress is adjusted, whereby resulting in the higher integration density of the semiconductor device.
  • Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS.1A to 1D are sectional views each showing an interlayer insulating film laminated structure in the prior art;
  • FIGS.2A and 2B are sectional views showing problems caused in the laminated structure according to the prior art;
  • FIGS.3A to 3F are sectional views each showing an interlayer insulating film forming method to illustrate an embodiment of the present invention;
  • FIG. 4 is a characteristic view showing change in stress due to multilayer stacking of overall interlayer insulating films by virtue of the interlayer insulating film forming method according to the first embodiment of the present invention before and after humidity absorption;
  • FIGS. 5A to 5E are characteristic views each showing stress adjustment depending upon various film forming conditions in a plasma CVD method according to the first embodiment of the present invention;
  • FIGS. 6A to 6C are characteristic views each showing stress adjustment depending upon various film forming conditions in a thermal CVD method according to the first embodiment of the present invention;
  • FIG. 7 is a sectional view showing a semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention; and
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Various embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
    • (1) First Embodiment
  • An experiment made to check a stress compensation effect of the present invention will be explained hereunder.
  • First, a method of forming a sample used in the experiment will be explained. Seven type of samples (S1 to S7) shown in FIGS.3A to 3F have been used. Though locking a step of irradiating the insulating film having tensile stress with a plasma to shift stress in said film do more tensile (step (b)), these examples are in generale suitable to illustrate the lamination of multiple insulating layers having tensile and compressive stress, respectively.
    • (Formation of sample S1)
  • A laminated structure of the sample S1 is shown in FIG.3A. Characteristics of respective layers in the sample S1 such as type of insulating film, film thickness, total stress, and generation of crack are indicated in Table III. The insulating film formed by the plasma CVD method will be called a PECVD film (plasma CVD film) hereinafter, and the insulating film formed by the thermal CVD method will be called a THCVD film (thermal CVD film) hereinafter. Further, "total stress" indicated in Table III means stress generated in the overall insulating films after respective insulating films have been laminated, which is calculated according to an amount of bowing generated after respective insulating films have been laminated on a silicon wafer. A calculation method is effected based on a literature, i.e., J. Vac. Scl. Technol. A, Vol.14, No.3, May/Jun 1986, pp.645-649. Similarly, in Tables IV to IX, total stresses have also been calculated according to the same calculation method.
    Layer (numeral) Type of insulating film Film thickness (µm) Total stress (×105dyne/cm) Crack generation
    1st layer(22a) PECVD film 0.2 -0.38 none
    2nd layer(23a) THCVD film 0.5 +0.53 none
    3rd layer(22b) PECVD film 1.0 -2.0 none
    4th layer(23b) THCVD film 1.45 -1.4 none
    5th layer(22c) PECVD film 0.4 -5.4 none
    6th layer(23c) THCVD film 1.45 -4.5 none
    7th layer(22d) PECVD film 0.4 -9.0 none
    8th layer(23d) THCVD film 1.45 -8.3 none
    9th layer(22e) PECVD film 0.4 ≦-10.7 none
  • In the above Table III, film forming conditions for the plasma CVD film except for a film forming time are common throughout all laminated layers, and they are set forth hereunder.
    Film forming gas (Flow rate sccm) TMS(15 sccm)+N2O(450 sccm)
    Pressure 0.7 Torr
    Plasma generating power 150 W
    Frequency 13.56 MHz
    Bias power 150 W
    Frequency 380 kHz
    Substrate temperature (Film forming temperature) 330 °C
    Film forming rate 150 nm/min
  • Under the film forming conditions defined as above, a silicon oxide film having compressive stress of -3.3×109 dyne/cm2 can be formed.
  • Moreover, film forming conditions of the thermal CVD film except for a film forming time are common in respective layers, which are set forth hereunder.
    Film forming gas (Flow rate sccm) TEOS(1500 sccm) +O 3 5 % in O 2 7.5 l)
    Substrate temperature (Film forming temperature) 400 °C
    Film forming rate 87 nm/min
  • Under the film forming conditions defined as above, a silicon oxide film having tensile stress of +2.2×109 dyne/cm2 can be formed.
  • As the organic silane to be included in the film forming gas, TMS (trimethoxysilane: HSi(OCH3)3) or TEOS(tetraethylorthosilicate: Si(OC2H5)4) has been employed in the plasma CVD method and the thermal CVD method. However, such organic silane may be formed of any of alkylsilane or allylsilane (general formula: RnSiH4-n (n=1 to 4)), alkoxysilane (general formula: (RO)nSiH4-n (n=1 to 4)), chain siloxane (general formula: RnH3-nSiO(RkH2-kSiO)mSiH3-nRn (n=1 to 3; k=0 to 2; m≧0)), derivative of chain siloxane (general formula: (RO)nH3- nSiOSiH3-n(OR)n (n=1 to 3)), and ring siloxane (general formula: (RkH2-kSiO)m (k=1, 2; m≧2)) (where R is alkyl group, allyl group, or their derivative).
  • Still further, ozone (O3 or oxygen (O2) has been employed as the oxygen containing gas. However, the oxygen containing gas may be formed of any of N2O, NO2, CO, CO2, and H2O.
    • (Formation of sample S2)
  • A laminated structure of the sample S2 is shown in FIG.3B. Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S2 are indicated in Table IV.
    Layer (numeral) Type of insulating film Film thickness (µm) Total stress (×105dyne/cm) Crack generation
    1st layer(22f) PECVD film 0.2 -0.58 none
    2nd layer(23e) THCVD film 1.2 +2.0 none
    3rd layer(22g) PECVD film 0.3 +0.92 none
    4th layer(23f) THCVD film 1.5 +4.0 none
    5th layer(22h) PECVD film 0.35 +2.4 none
    6th layer(23g) THCVD film 1.5 +5.8 none
    7th layer(22i) PECVD film 0.35 +4.0 generated
    8th layer(23h) THCVD film 1.5 +6.7 remaining
    9th layer(22j) PECVD film 0.25 +4.7 remaining
  • In the above Table IV, film forming conditions of the plasma CVD film other than a film forming time are common throughout all laminated layers, and they are set identically to the case where the sample S1 is formed.
  • Also, film forming conditions of the thermal CVD film other than a film forming time are common in respective layers, and they are set identically to the case where the sample S1 is formed.
    • (Formation of sample S3)
  • A laminated structure of the sample S3 is also shown in FIG.3B. Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S3 are indicated in Table V.
    Layer (numeral) Type of insulating film Film thickness (µm) Total stress (×105dyne/cm) Crack generation
    1st layer(22f) PECVD film 0.2 -0.69 none
    2nd layer(23e) THCVD film 1.2 +2.3 none
    3rd layer(22g) PECVD film 0.4 +0.6 none
    4th layer(23f) THCVD film 1.45 +3.7 none
    5th layer(22h) PECVD film 0.4 +1.5 none
    6th layer(23g) THCVD film 1.45 +5.1 none
    7th layer(22i) PECVD film 0.4 +2.6 none
    8th layer(23h) THCVD film 1.45 +5.3 none
    9th layer(22j) PECVD film 0.2 +3.4 none
  • In the above Table V, film forming conditions of the plasma CVD film except for a film forming time are common throughout all laminated layers, and they are identical to the case where the sample S1 is formed.
  • Further, film forming conditions of the thermal CVD film except for a film forming time are common in respective layers, and they are identical to the case where the sample S1 is formed.
    • (Formation of sample S4)
  • A laminated structure of the sample S4 is shown in FIG.3C. Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S4 are indicated in Table VI.
    Layer (numeral) Type of insulating film Film thickness (µm) Total stress (×105dyne/cm) Crack generation
    1st layer(22k) PECVD film 0.1 -0.34 none
    2nd layer(23i) THCVD film 1.5 +3.4 none
    3rd layer(22l) PECVD film 0.1 - none
    4th layer(23j) THCVD film 1.6 +6.8 generated
  • In the above Table VI, film forming conditions of the plasma CVD film other than a film forming time are common throughout all laminated layers, which are identical to the case where the sample S1 is formed.
  • In addition, film forming conditions of the thermal CVD film other than a film forming time are common in respective layers, which are identical to the case where the sample S1 is formed.
    • (Formation of sample S5)
  • A laminated structure of the sample S5 is shown in FIG.3D. Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S5 are indicated in Table VII.
    Layer (numeral) Type of insulating film Film thickness (µm) Total stress (×105dyne/cm) Crack generation
    1st layer(22m) PECVD film 0.1 -0.34 none
    2nd layer(23k) THCVD film 1.5 +3.4 none
    3rd layer(22n) PECVD film 0.1 - none
    4th layer(23l) THCVD film 1.6 +6.8 none
  • In the above Table VII, film forming conditions of the plasma CVD film other than a film forming time are common throughout all laminated layers, which are set to be identical to the case where the sample S1 is formed.
  • In addition, film forming conditions of the thermal CVD film other than a film forming time are common in respective layers, which are set to be identical to the case where the sample S1 is formed.
    • (Formation of sample S6)
  • A laminated structure of the sample S6 is shown in FIG.3E. Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S6 are indicated in Table VIII.
    Layer (numeral) Type of insulating film Film thickness (µm) Total stress (×105dyne/cm) Crack generation
    1st layer(22p) PECVD film 1.1 -3.2 none
    2nd layer(23m) THCVD film 1.2 -0.65 none
    3rd layer(22q) PECVD film 0.1 - none
    4th layer(23n) THCVD film 1.7 +2.7 none
  • In the above Table VIII, film forming conditions of the plasma CVD film other than a film forming time are common in respective layers, and they are set identically to the case where the sample S1 is formed.
  • In addition, film forming conditions of the thermal CVD film other than a film forming time are common in respective layers and they are set identically to the case where the sample S1 is formed.
    • (Formation of sample S7)
  • A laminated structure of the sample S7 is shown in FIG.3F. Type of insulating film, film thickness, total stress, and generation of crack in respective layers of the sample S7 are indicated in Table IX.
    Layer (numeral) Type of insulating film Film thickness (µm) Total stress (×105dyne/cm) Crack generation
    1st layer(22r) PECVD film 1.3 -3.9 none
    2nd layer(23p) THCVD film 0.5 -0.17 none
  • In the above Table IX, film forming conditions of the plasma CVD film other than a film forming time are common throughout all laminated layers, which are identical to the case where the sample S1 is formed.
  • In addition, film forming conditions of the thermal CVD film other than a film forming time are common in respective layers, which are identical to the case where the sample S1 is formed.
  • Subsequently, the results are shown in FIGS.4A and 4B when change in stress is summarized in the samples S1 to S3 respectively based on stress values indicated in above Tables III to V after respective insulating layers have been laminated.
  • From experiments it has been deduced that a stress range not to generate cracks is less than +2 x 105 dyne/cm if the insulating film is formed on the Al film.
  • In addition, the results are shown in FIG. 4 when change in stress is investigated in the samples S2 to S7 respectively before and after humidity absorption after the multiple insulating layers are laminated.
  • FIG. 4 is a characteristic view showing change in stress before and after humidity absorption, wherein an ordinate shows the average stress value (×109 dyne/cm2) caused in the laminated films on a linear scale and an abscissa shows the time interval before and after humidity absorption. In the above experiment, it seems that ambient humidity of the sample has been about 40 % and that humidity absorption has occurred mainly in the thermal CVD films of all the laminated films.
  • As shown in FIG. 4, it would be evident that variation in stress due to humidity absorption has been large in the samples S4 to S7, in which the uppermost layer is formed of the THCVD film, compared to the samples S2, S3, in which the uppermost layer is formed of the PECVD film. The stress has been shifted towards the compressive stress side due to humidity absorption in the samples S4 to S7. It is desired that the.uppermost layer should be formed of the PECVD film if suppression of variation in stress is needed. Otherwise, from another experiment, it has been confirmed that plasma irradiation after film formation is effective to suppress variation in stress.
  • It has been found from the above experimental results that stress caused in the overall laminated films can be calculated according to the following equation. That is,
    Figure 00160001
    Where n is the total laminated number, ti is a thickness of i-th insulating film (cm), and σi is stress in i-th insulating film (dyne/cm2). As for type of stress of the insulating film, it is assumed that the tensile stress is positive and the compressive stress is negative.
  • It has been confirmed that, under the assumption that a stress value σ of the plasma CVD film is -3×109 dyne/cm2 and a stress value σ of the thermal CVD film is +2×109 dyne/cm2, stress values calculated according to the above equation exactly coincide with measured stress values, as indicated in Tables III to IX.
  • From the samples S2, S4, S5, it is understood that a stress range not to generate the cracks is less than about +3×105 dyne/cm. If stress of the silicon oxide film formed by the thermal CVD method is assumed as 2×109 dyne/cm2, this corresponds to about 1.5 µm in terms of the thickness of the silicon oxide film formed by the thermal CVD method.
  • Therefore, if stress of the overall laminated films calculated by the equation is set to a stress limit (+3×105 dyne/cm on an Si film, or +2×105 dyne/cm on an aluminum film) and then thickness and stress of individual insulating films are determined not to exceed this stress limit, cracks in the interlayer insulating films can be prevented.
  • Depending upon the film forming method and the film forming conditions, stress in the insulating film formed by the plasma CVD method and stress in the insulating film formed by the thermal CVD method can be adjusted as explained hereunder and known to a skilled worker.
  • For instance, stress in the insulating film formed by the plasma CVD method can as is known to a skilled worker be adjusted according to type of gas, flow rate of gas, frequency of plasma generating power, bias power applied to the substrate, film forming temperature, etc. Experimental examples are shown in FIGS. 5A to 5E. Although TEOS+O2 system reaction gas has been employed in the experimental examples, stress may be adjusted in a similar manner when TMS+N2O system reaction gas is employed.
  • Also stress in the insulating film formed by the thermal CVD method can be adjusted by known methods according to type of gas, flow rate of gas (including ozone concentration in oxygen), film forming temperature, film forming rate, etc. Experimental examples are shown in FIGS. 6A o 6C. The TEDS+O3reaction gas has been employed as the film forming gas.
  • However, usually, stress in the insulating film formed by the thermal CVD method is often shifted to the compressive stress side because of humidity absorption after formation. Therefore, if moisture is removed from the insulating film by virtue of plasma irradiation according to the invention stress in the insulating film can be shifted to the tensile stress side. As a result, it is possible to stabilize stress in the insulating film.
  • FIG. 7 shows an example of a semiconductor device in which a four-layered interconnections are formed for illustration purposes. The interlayer insulating films formed according to the method of manufacturing the interlayer insulating film of the present invention are interposed respectively between neighboring two interconnections of the four layered interconnections. Film forming gas and film forming conditions used in the plasma CVD method and the thermal CVD method are selected identically to those explained in forming the sample S1 in the first embodiment.
  • As shown in FIG. 7, interconnections 33a, 33b made of an aluminum film having a thickness of 0.7 µm are formed on a substrate 31.
  • First, a silicon oxide film 34a of 0.2 µm thickness is formed by virtue of the plasma CVD method to cover the interconnections 33a, 33b.
  • Then, a silicon oxide film 35a of 0.5 µm thickness is formed on the silicon oxide film 34a by virtue of the thermal CVD method.
  • In turn, a silicon oxide film 34b of 0.9 µm thickness is formed on the silicon oxide film 35a by virtue of the plasma CVD method.
  • Subsequently, a surface of the silicon oxide film 34b is planarized by polishing the silicon oxide film 34b by virtue of CMP method (Chemical Mechanical Polishing Method). Thereby, formation of the first-layered interlayer insulating film 1L having a thickness of 1.6 µm to cover the first-layered interconnections 33a, 33b is completed.
  • Next, second-layered interconnections 33c, 33d made of an aluminum film having a thickness of 0.95 µm are formed on the planarized silicon oxide film 34b.
  • Then, a second-layered interlayer insulating film 2L having a thickness of 1.85 µm is formed by repeating the above steps. The second-layered interlayer insulating film 2L consists of a silicon oxide film 34c of 0.1 µm thickness formed by the plasma CVD method, a silicon oxide film 35b of 0.45 µm thickness formed by the thermal CVD method, and a silicon oxide film 34d of 1.3 µm thickness formed by the plasma CVD method.
  • Then, third-layered interconnections 33e, 33f made of an aluminum film having a thickness of 0.95 µm and a third-layered interlayer insulating film 3L having a thickness of 1.85 µm are formed in this order on the second-layered interlayer insulating film 2L. The third-layered interlayer insulating film 3L consists of a silicon oxide film 34e of 0.1 µm thickness formed by the plasma CVD method, a silicon oxide film 35c of 0.45 µm thickness formed by the thermal CVD method, and a silicon oxide film 34f of 1.3 µm thickness formed by the plasma CVD method.
  • Then, fourth-layered interconnections 33g, 33h made of an aluminum film having a thickness of 0.95 µm and a fourth-layered covering insulating film 4L having a thickness of 1.85 µm are formed in this order on the third-layered interlayer insulating film 3L. The covering insulating film 4L consists of a silicon oxide film 34g of 0.1 µm thickness formed by the plasma CVD method, a silicon oxide film 35d of 0.45 µm thickness formed by the thermal CVD method, and a silicon oxide film 34h of 1.3 µm thickness formed by the plasma CVD method.
  • With the above, four layered interconnections, three interlayer insulating films 1L to 3L which are interposed respectively between neighboring two interconnections of the four interconnections, and the covering insulating film 4L for covering the fourth layer interconnection have been formed. The preselected interconnections of the interconnections are connected through via holes (not shown) formed in the interlayer insulating films 1L to 3L, into which conductive layers are buried.
  • If stress of the overall laminated interlayer insulating films, etc. 1L to 4L is set not to exceed the stress limit (3×105 dyne/cm on the insulating film, 2×105 dyne/cm on the aluminum film), the arbitrary number of interconnections can be laminated without generating the crack in respective interlayer insulating films.
  • If the above stress limits are restricted narrower, generation of the crack can be suppressed much more, and the curvature of the wafer, degradation in the semiconductor device characteristics, etc. due to stress can also be prevented, and further stress migration or electromigration of the interconnection, e.g., aluminum interconnection, can be prevented.
  • In addition, if multilayered interconnections are laminated via the stress-adjusted interlayer insulating films while preventing generation of the crack in the interlayer insulating film, etc. and electromigration of the interconnection, etc., the semiconductor device having the high integration density can be accomplished.
  • As described earlier, according to the interlayer insulating film forming method of the present invention, multiple insulating layers whose total stress is adjusted can be formed by laminating insulating films having different stress mixedly on the substrate.
  • Accordingly, it is possible to adjust the stress of the overall multilayered insulating films less than the limit stress value not to generate the cracks in the insulating film, otherwise it is possible to adjust the stress of the overall multilayered insulating films within the stress range not to cause the curvature of the wafer, degradation in the semiconductor device characteristics, etc. due to stress.

Claims (12)

  1. A stress-adjusted insulating film forming method, wherein:
       an insulating film (23a to 23d) having a tensile stress and an insulating film (22a to 22e) having compressive stress are alternately deposited on a substrate (21) to form said stress-adjusted insulating film consisting of said laminated insulating films (22a, 23a, .., 23d, 22e); said method comprising:
    (a) forming an insulating film (23a to 23d) having a tensile stress by reacting a gas mixture including organic silane and oxygen containing gas by virtue of heating;
    (b) then irradiating said insulating film (23a to 23d) having a tensile stress with a plasma to shift stress in said insulating film to more tensile;
    (c) then forming an insulating film (22a to 22e) having compressive stress on said insulating film (23a to 23d); and
    (d) alternating a combination of steps (a) and (b) with step (c) to form a stress-adjusted insulating film consisting of said multiple first and second insulating films (22a, 23a,...,23d, 22e).
  2. A stress-adjusted insulating film forming method according to claim 1, wherein stress in said overall stress-adjusted insulating film is adjusted according to the equation:
    Figure 00250001
       wherein δT is the stress in the overall stress-adjusted insulating film, ti is a thickness of the i-th insulating film of said stress-adjusted insulating film, and δi is the stress in the i-th insulating film of said stress-adjusted insulating film, wherein tensile stress is positive and compressive stress is negative.
  3. A stress-adjusted insulating film forming method according to claim 2, wherein said stress (δT) in the overall stress-adjusted insulating film is tensile stress or compressive stress of less than +3x105 dyne/cm.
  4. A stress-adjusted insulating film forming method according to one of the preceding claims, wherein said insulating film is a silicon oxide film or a silicon containing insulating film including at least any of phosphorus and boron.
  5. A stress-adjusted insulating film forming method according to one of the preceding claims, wherein said gas mixture further includes impurity containing gas.
  6. A stress adjusted insulating film forming method according to one of the preceding claims, wherein said insulating film (22a to 22e) having compressive stress is deposited by reacting a gas mixture including organic silane and oxygen containing gas by virtue of a plasma reaction.
  7. A stress-adjusted insulating film forming method according to one of the preceding claims, wherein said organic silane is one selected from the group consisting of alkylsilane or allylsilane having the formula: RnSiH4-n (n=1 to 4), alkoxysilane having the formula: (RO)nSiH4-n (n=1 to 4), chain siloxane having the formula: RnH3-nSiO(RkH2-kSiO)mSiH3-nRn (n=1 to 3; k=0 to 2; m≧0), derivative of chain siloxane having the formula: (RO)n H3-n SiOSiH3-n (OR)n (n = 1 to 3), and ring siloxane having the formula: (Rk H2-k SiO)m (k=1, 2; m ≧ 2) wherein R is alkyl group, allyl group, or their derivative.
  8. A stress-adjusted insulating film forming method according to one of the preceding claims, wherein said oxygen containing gas is one selected from the group consisting of ozone (O3), oxygen (O2), N2O, NO2, CO, CO2, and H2O.
  9. A stress-adjusted insulating film forming method according to one of the preceding claims, wherein said film forming condition of respective insulating films to adjust stress characteristics of respective insulating films is at least one selected from the group consisting of a frequency of plasma generating power, a bias power applied to said substrate, a film forming temperature, type of gas, and a flow rate of gas.
  10. A semiconductor device manufacturing method according to claim 1, wherein:
       an insulating film (35a) having a tensile stress and an insulating film (34a, 34b) having compressive stress are alternately deposited covering an interconnection layer (33a, 33b) on a substrate (31) to form a stress-adjusted insulating film.
  11. A semiconductor device manufacturing method according to claim 1 comprising the steps of:
    (a) forming an interconnection layer (33a, 33b) on a substrate (31);
    (b) forming a stress-adjusted insulating film (1L) in which an insulating film (35a) having a tensile stress and an insulating film (34a, 34b) having compressive stress are alternately laminated covering said interconnection layer (33a, 33b) on said substrate (31) to form said stress-adjusted insulating film (1L) by:
    (i) forming an insulating film (34a) having compressive stress on said interconnection layer,
    (ii) forming a insulating film (35a) having a tensile stress by reacting a gas mixture including organic silane and oxygen containing gas by virtue of heating,
    (iii) then irradiating said insulating film (35a) having a tensile stress with a plasma to shift stress in said first insulating film (35a) to more tensile,
    (iv) then forming an insulating film (34b) having compressive stress on said insulating film (35a) to form said stress-adjusted insulating film (1L) covering said interconnection layer (33a, 33b), and
    (c) repeating steps (a) and (b) to laminate alternately said interconnection layers (33a to 33h) and said stress-adjusted insulating films (1L to 4L).
  12. A semiconductor device manufacturing method according to one of claims 10 or 11, wherein the material of said interconnection layer (33a, 33b) is aluminum.
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Cited By (5)

* Cited by examiner, † Cited by third party
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EP1174916A2 (en) * 2000-07-21 2002-01-23 Canon Sales Co., Inc. Semiconductor device and semiconductor device manufacturing method
EP1295924A2 (en) * 2001-09-25 2003-03-26 JSR Corporation Stacked film, method for the formation of stacked film, insulating film, and substrate for semiconductor
US6835669B2 (en) 2000-07-21 2004-12-28 Canon Sales Co., Inc. Film forming method, semiconductor device and semiconductor device manufacturing method
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990081277A (en) * 1998-04-28 1999-11-15 윤종용 Stress control method of insulating film
US6184157B1 (en) * 1998-06-01 2001-02-06 Sharp Laboratories Of America, Inc. Stress-loaded film and method for same
KR20000073343A (en) * 1999-05-10 2000-12-05 김영환 Interconnect Structure for Semiconductor Device
US6534870B1 (en) 1999-06-15 2003-03-18 Kabushiki Kaisha Toshiba Apparatus and method for manufacturing a semiconductor device
GB2358285A (en) * 1999-08-30 2001-07-18 Lucent Technologies Inc Interlevel dielectrics
JP3348084B2 (en) 1999-12-28 2002-11-20 キヤノン販売株式会社 Film forming method and semiconductor device
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DE102004031744A1 (en) * 2004-06-30 2006-07-27 Advanced Micro Devices, Inc., Sunnyvale A technique for making a dielectric interlayer over a structure with closely spaced leads
US7638859B2 (en) 2005-06-06 2009-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnects with harmonized stress and methods for fabricating the same
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US7563704B2 (en) * 2005-09-19 2009-07-21 International Business Machines Corporation Method of forming an interconnect including a dielectric cap having a tensile stress
US7858532B2 (en) * 2007-08-06 2010-12-28 United Microelectronics Corp. Dielectric layer structure and manufacturing method thereof
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DE102008054069B4 (en) 2008-10-31 2016-11-10 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Reduced disk deflection in semiconductors due to stressing techniques in the metallization system
US20120015113A1 (en) * 2010-07-13 2012-01-19 Applied Materials, Inc. Methods for forming low stress dielectric films
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JP6919137B2 (en) * 2017-05-11 2021-08-18 新日本無線株式会社 Manufacturing method of semiconductor devices
JP7005367B2 (en) * 2018-02-05 2022-02-04 東京エレクトロン株式会社 Boron-based film film forming method and film forming equipment
CN108376652B (en) * 2018-03-05 2019-08-30 长江存储科技有限责任公司 Wafer bonding method, wafer bonding structure and the method for adjusting wafer distortion amount
KR102271158B1 (en) 2020-12-22 2021-06-29 조아라 Ceramic roller
US11973021B2 (en) * 2021-09-17 2024-04-30 Vanguard International Semiconductor Corporation Semiconductor device and method forming the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0270321A2 (en) * 1986-12-01 1988-06-08 The University Of British Columbia Monoclonal antibodies effective in promoting growth
EP0470632A2 (en) * 1990-08-10 1992-02-12 Semiconductor Process Laboratory Co., Ltd. Method of manufacturing a silicon oxide film and an oxide based glass for semiconductor devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH084109B2 (en) * 1987-08-18 1996-01-17 富士通株式会社 Semiconductor device and manufacturing method thereof
US5098865A (en) * 1989-11-02 1992-03-24 Machado Jose R High step coverage silicon oxide thin films
JPH03151637A (en) * 1989-11-09 1991-06-27 Kowa Kurieitaa:Kk Manufacture of semiconductor device and plasma cvd equipment
CA2006174A1 (en) * 1989-12-20 1991-06-20 Luc Ouellet Method of making crack-free insulating films with sog interlayer
US5250468A (en) * 1990-02-05 1993-10-05 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including interlaying insulating film
JP3332467B2 (en) * 1993-04-06 2002-10-07 三洋電機株式会社 Method for manufacturing polycrystalline semiconductor
US5500312A (en) * 1994-10-11 1996-03-19 At&T Corp. Masks with low stress multilayer films and a process for controlling the stress of multilayer films

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0270321A2 (en) * 1986-12-01 1988-06-08 The University Of British Columbia Monoclonal antibodies effective in promoting growth
EP0470632A2 (en) * 1990-08-10 1992-02-12 Semiconductor Process Laboratory Co., Ltd. Method of manufacturing a silicon oxide film and an oxide based glass for semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Chemical Vapor Deposition for Microelectronics by A. Sherman, Noyes Publication Co., USA, 1987. *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1174914A2 (en) * 2000-07-21 2002-01-23 Canon Sales Co., Inc. Semiconductor device and semiconductor device manufacturing method
EP1174916A2 (en) * 2000-07-21 2002-01-23 Canon Sales Co., Inc. Semiconductor device and semiconductor device manufacturing method
US6835669B2 (en) 2000-07-21 2004-12-28 Canon Sales Co., Inc. Film forming method, semiconductor device and semiconductor device manufacturing method
EP1295924A2 (en) * 2001-09-25 2003-03-26 JSR Corporation Stacked film, method for the formation of stacked film, insulating film, and substrate for semiconductor
US6749944B2 (en) 2001-09-25 2004-06-15 Jsr Corporation Stacked film, method for the formation of stacked film, insulating film, and substrate for semiconductor
TWI843943B (en) * 2021-03-24 2024-06-01 世界先進積體電路股份有限公司 Semiconductor device and method forming the same

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