DE69913366D1 - Lese/schreibe-puffern für ein komplettes verdecken des auffrischen eines halbleiterspeichers und verfahren zum betreiben derselben - Google Patents

Lese/schreibe-puffern für ein komplettes verdecken des auffrischen eines halbleiterspeichers und verfahren zum betreiben derselben

Info

Publication number
DE69913366D1
DE69913366D1 DE69913366T DE69913366T DE69913366D1 DE 69913366 D1 DE69913366 D1 DE 69913366D1 DE 69913366 T DE69913366 T DE 69913366T DE 69913366 T DE69913366 T DE 69913366T DE 69913366 D1 DE69913366 D1 DE 69913366D1
Authority
DE
Germany
Prior art keywords
finishing
semi
read
operating
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69913366T
Other languages
English (en)
Other versions
DE69913366T2 (de
Inventor
Wingyu Leung
Fu-Chieh Hsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peraso Inc
Original Assignee
Monolithic System Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/405,607 external-priority patent/US6415353B1/en
Application filed by Monolithic System Technology Inc filed Critical Monolithic System Technology Inc
Publication of DE69913366D1 publication Critical patent/DE69913366D1/de
Application granted granted Critical
Publication of DE69913366T2 publication Critical patent/DE69913366T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618Refresh operations over multiple banks or interleaving
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30Providing cache or TLB in specific location of a processing system
    • G06F2212/304In main memory subsystem
    • G06F2212/3042In main memory subsystem being part of a memory device, e.g. cache DRAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69913366T 1998-10-01 1999-10-01 Lese/schreibe-puffern für ein komplettes verdecken des auffrischen eines halbleiterspeichers und verfahren zum betreiben derselben Expired - Lifetime DE69913366T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US405607 1989-09-11
US165228 1993-12-10
US09/165,228 US5999474A (en) 1998-10-01 1998-10-01 Method and apparatus for complete hiding of the refresh of a semiconductor memory
US09/405,607 US6415353B1 (en) 1998-10-01 1999-09-24 Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same
PCT/US1999/022894 WO2000019445A1 (en) 1998-10-01 1999-10-01 Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same

Publications (2)

Publication Number Publication Date
DE69913366D1 true DE69913366D1 (de) 2004-01-15
DE69913366T2 DE69913366T2 (de) 2004-05-27

Family

ID=22598011

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69913366T Expired - Lifetime DE69913366T2 (de) 1998-10-01 1999-10-01 Lese/schreibe-puffern für ein komplettes verdecken des auffrischen eines halbleiterspeichers und verfahren zum betreiben derselben

Country Status (6)

Country Link
US (2) US5999474A (de)
EP (1) EP1119862B1 (de)
JP (1) JP4025509B2 (de)
DE (1) DE69913366T2 (de)
TW (1) TW476960B (de)
WO (1) WO2000019445A1 (de)

Families Citing this family (121)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9007790D0 (en) 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
US5796673A (en) * 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
US6468855B2 (en) * 1998-08-14 2002-10-22 Monolithic System Technology, Inc. Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
US6898140B2 (en) 1998-10-01 2005-05-24 Monolithic System Technology, Inc. Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
US6370073B2 (en) * 1998-10-01 2002-04-09 Monlithic System Technology, Inc. Single-port multi-bank memory system having read and write buffers and method of operating same
US6415353B1 (en) * 1998-10-01 2002-07-02 Monolithic System Technology, Inc. Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same
US6707743B2 (en) 1998-10-01 2004-03-16 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
US5999474A (en) 1998-10-01 1999-12-07 Monolithic System Tech Inc Method and apparatus for complete hiding of the refresh of a semiconductor memory
US6504780B2 (en) * 1998-10-01 2003-01-07 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a dram device using clock division
US6222785B1 (en) * 1999-01-20 2001-04-24 Monolithic System Technology, Inc. Method and apparatus for refreshing a semiconductor memory using idle memory cycles
US6496437B2 (en) 1999-01-20 2002-12-17 Monolithic Systems Technology, Inc. Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory
US6356485B1 (en) 1999-02-13 2002-03-12 Integrated Device Technology, Inc. Merging write cycles by comparing at least a portion of the respective write cycle addresses
JP3807582B2 (ja) 1999-02-18 2006-08-09 株式会社ルネサステクノロジ 情報処理装置及び半導体装置
JP2000251467A (ja) * 1999-03-02 2000-09-14 Nec Ibaraki Ltd メモリリフレッシュ制御装置およびその制御方法
EP1052646B1 (de) * 1999-05-11 2004-07-14 Fujitsu Limited Nichtflüchtige Halbleiterspeicheranordnung, die eine Datenleseoperation während einer Datenschreib/lösch-Operation erlaubt
TW522399B (en) 1999-12-08 2003-03-01 Hitachi Ltd Semiconductor device
US6553552B1 (en) * 2000-01-27 2003-04-22 National Semiconductor Corporation Method of designing an integrated circuit memory architecture
US6151236A (en) * 2000-02-29 2000-11-21 Enhanced Memory Systems, Inc. Enhanced bus turnaround integrated circuit dynamic random access memory device
US6430098B1 (en) 2000-05-16 2002-08-06 Broadcom Corporation Transparent continuous refresh RAM cell architecture
JP2001332084A (ja) * 2000-05-22 2001-11-30 Fujitsu Ltd 半導体記憶装置及び半導体記憶装置のリフレッシュ方法
JP3871853B2 (ja) 2000-05-26 2007-01-24 株式会社ルネサステクノロジ 半導体装置及びその動作方法
US6552923B2 (en) * 2000-06-13 2003-04-22 Texas Instruments Incorporated SRAM with write-back on read
JP3531592B2 (ja) 2000-07-21 2004-05-31 セイコーエプソン株式会社 半導体装置及び電子機器
US6862654B1 (en) * 2000-08-17 2005-03-01 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
US6445636B1 (en) * 2000-08-17 2002-09-03 Micron Technology, Inc. Method and system for hiding refreshes in a dynamic random access memory
US6941415B1 (en) * 2000-08-21 2005-09-06 Micron Technology, Inc. DRAM with hidden refresh
US6779076B1 (en) 2000-10-05 2004-08-17 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
JP2002140890A (ja) * 2000-10-31 2002-05-17 Hitachi Ltd 半導体装置
JP3938842B2 (ja) * 2000-12-04 2007-06-27 富士通株式会社 半導体記憶装置
KR100367690B1 (ko) * 2000-12-04 2003-01-14 (주)실리콘세븐 디램 셀을 이용한 비동기식 에스램 호환 메모리 장치 및그 구동 방법
US6366516B1 (en) 2000-12-29 2002-04-02 Intel Corporation Memory subsystem employing pool of refresh candidates
KR100381615B1 (ko) * 2001-01-04 2003-04-26 (주)실리콘세븐 디램 캐쉬 메모리를 이용하여 리프레쉬 동작을 숨기는에스램 호환 메모리
JP2004288226A (ja) * 2001-03-30 2004-10-14 Internatl Business Mach Corp <Ibm> Dram及びdramのリフレッシュ方法
US7085186B2 (en) * 2001-04-05 2006-08-01 Purple Mountain Server Llc Method for hiding a refresh in a pseudo-static memory
US6829682B2 (en) * 2001-04-26 2004-12-07 International Business Machines Corporation Destructive read architecture for dynamic random access memories
KR100394587B1 (ko) * 2001-05-19 2003-08-14 (주)실리콘세븐 디램 셀을 이용한 에스램 호환 메모리 장치의 리프레쉬 회로
KR100394322B1 (ko) * 2001-05-19 2003-08-09 (주)이엠엘에스아이 리프레쉬 동작을 제어할 수 있는 디램 셀을 이용한 에스램호환 메모리 장치
KR100401235B1 (ko) * 2001-05-22 2003-10-17 (주)실리콘세븐 디램 셀을 이용한 에스램 호환 메모리 장치의 로우 제어회로
JP4768163B2 (ja) * 2001-08-03 2011-09-07 富士通セミコンダクター株式会社 半導体メモリ
JP3985889B2 (ja) * 2001-08-08 2007-10-03 株式会社ルネサステクノロジ 半導体装置
US6757784B2 (en) * 2001-09-28 2004-06-29 Intel Corporation Hiding refresh of memory and refresh-hidden memory
US7333388B2 (en) * 2001-10-03 2008-02-19 Infineon Technologies Aktiengesellschaft Multi-port memory cells
TW533413B (en) * 2001-10-11 2003-05-21 Cascade Semiconductor Corp Asynchronous hidden refresh of semiconductor memory
WO2003032170A1 (en) 2001-10-11 2003-04-17 Cascade Semiconductor Corporation Asynchronous hidden refresh of semiconductor memory
US6643205B2 (en) * 2001-10-23 2003-11-04 Coremagic, Inc. Apparatus and method for refresh and data input device in SRAM having storage capacitor cell
US6882562B2 (en) * 2001-11-01 2005-04-19 Agilent Technologies, Inc. Method and apparatus for providing pseudo 2-port RAM functionality using a 1-port memory cell
US6643732B1 (en) 2001-11-14 2003-11-04 Etron Technology, Inc. Delayed read/write scheme for SRAM interface compatible DRAM
US6748497B1 (en) * 2001-11-20 2004-06-08 Cirrus Logic, Inc. Systems and methods for buffering memory transactions
US20030097519A1 (en) * 2001-11-21 2003-05-22 Yoon Ha Ryong Memory subsystem
JP4249412B2 (ja) * 2001-12-27 2009-04-02 Necエレクトロニクス株式会社 半導体記憶装置
US6638813B1 (en) 2002-01-29 2003-10-28 Taiwan Semiconductor Manufacturing Company Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell
EP1345234A1 (de) * 2002-03-11 2003-09-17 STMicroelectronics S.r.l. Halbleiterspeicher mit Selbstauffrisch-Modus
US6906978B2 (en) * 2002-03-19 2005-06-14 Intel Corporation Flexible integrated memory
JP2003282823A (ja) * 2002-03-26 2003-10-03 Toshiba Corp 半導体集積回路
US7146454B1 (en) * 2002-04-16 2006-12-05 Cypress Semiconductor Corporation Hiding refresh in 1T-SRAM architecture
US6741515B2 (en) * 2002-06-18 2004-05-25 Nanoamp Solutions, Inc. DRAM with total self refresh and control circuit
US7043599B1 (en) * 2002-06-20 2006-05-09 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
KR100455393B1 (ko) * 2002-08-12 2004-11-06 삼성전자주식회사 리프레시 플래그를 발생시키는 반도체 메모리 장치 및반도체 메모리 시스템.
KR100481819B1 (ko) * 2002-08-27 2005-04-11 (주)실리콘세븐 디램 셀을 사용하며, 칩 디스에이블 구간 중에 발생하는신호에 의하여 리프레쉬가 수행되도록 제어되는 동기식에스램 호한 메모리
US20040064657A1 (en) * 2002-09-27 2004-04-01 Muraleedhara Navada Memory structure including information storage elements and associated validity storage elements
KR100482380B1 (ko) * 2002-11-11 2005-04-14 (주)실리콘세븐 메모리 뱅크별 기입 동작의 수행이 가능한 에스램 호환 메모리 및 그 구동방법
US7073026B2 (en) * 2002-11-26 2006-07-04 Advanced Micro Devices, Inc. Microprocessor including cache memory supporting multiple accesses per cycle
US6795364B1 (en) * 2003-02-28 2004-09-21 Monolithic System Technology, Inc. Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode
JP2004310879A (ja) * 2003-04-04 2004-11-04 Renesas Technology Corp 半導体記憶装置
JP4241175B2 (ja) 2003-05-09 2009-03-18 株式会社日立製作所 半導体装置
DE10329369B4 (de) * 2003-06-30 2010-01-28 Qimonda Ag Schaltung und Verfahren zum Auffrischen von Speicherzellen eines dynamischen Speichers
US6985398B2 (en) 2003-09-26 2006-01-10 Infineon Technologies Ag Memory device having multiple array structure for increased bandwidth
US20050067934A1 (en) * 2003-09-26 2005-03-31 Ishikawajima-Harima Heavy Industries Co., Ltd. Discharge apparatus, plasma processing method and solar cell
US6859407B1 (en) * 2004-01-14 2005-02-22 Infineon Technologies Ag Memory with auto refresh to designated banks
EP3001321B1 (de) * 2004-02-05 2018-07-11 BlackBerry Limited Speichersteuerungsschnittstelle
US20050226079A1 (en) * 2004-04-08 2005-10-13 Yiming Zhu Methods and apparatus for dual port memory devices having hidden refresh and double bandwidth
US8122187B2 (en) * 2004-07-02 2012-02-21 Qualcomm Incorporated Refreshing dynamic volatile memory
KR100564633B1 (ko) 2004-09-25 2006-03-28 삼성전자주식회사 향상된 동작 성능을 가지는 반도체 메모리 장치 및 이에대한 액세스 제어 방법
KR100652380B1 (ko) * 2004-10-25 2006-12-01 삼성전자주식회사 버퍼를 이용하여 리프레쉬하는 메모리 장치 및 그 방법
US7307912B1 (en) * 2004-10-25 2007-12-11 Lattice Semiconductor Corporation Variable data width memory systems and methods
KR100607334B1 (ko) * 2004-12-30 2006-08-01 주식회사 하이닉스반도체 슈도 에스램의 리프레쉬 제어 회로
US8347034B1 (en) 2005-01-13 2013-01-01 Marvell International Ltd. Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access
US7685372B1 (en) 2005-01-13 2010-03-23 Marvell International Ltd. Transparent level 2 cache controller
US7323379B2 (en) * 2005-02-03 2008-01-29 Mosys, Inc. Fabrication process for increased capacitance in an embedded DRAM memory
US7640392B2 (en) * 2005-06-23 2009-12-29 Qualcomm Incorporated Non-DRAM indicator and method of accessing data not stored in DRAM array
US7620783B2 (en) * 2005-02-14 2009-11-17 Qualcomm Incorporated Method and apparatus for obtaining memory status information cross-reference to related applications
US20060190678A1 (en) * 2005-02-22 2006-08-24 Butler Douglas B Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag
US7506100B2 (en) * 2005-02-23 2009-03-17 United Memories, Inc. Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks
KR100672029B1 (ko) * 2005-05-27 2007-01-19 삼성전자주식회사 Dram히든 리프레쉬 동작 시 발생되는 동작 시간 지연을감소시킬 수 있는 장치와 방법
US7274618B2 (en) * 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
JP4518563B2 (ja) * 2005-09-02 2010-08-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置
DE102005048582A1 (de) * 2005-10-06 2007-04-12 Robert Bosch Gmbh Teilnehmerschnittstelle zwischen einem Mikrocontroller und einem FlexRay-Kommunikationsbaustein, FlexRay-Teilnehmer und Verfahren zur Übertragung von Botschaften über eine solche Schnittstelle
US7349258B2 (en) * 2005-12-06 2008-03-25 Sandisk Corporation Reducing read disturb for non-volatile storage
KR101197624B1 (ko) * 2006-01-18 2012-11-07 에스케이하이닉스 주식회사 반도체 메모리 소자의 뱅크 제어 회로
US20070170489A1 (en) * 2006-01-26 2007-07-26 Fang Gang-Feng Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process
US7382658B2 (en) * 2006-01-26 2008-06-03 Mosys, Inc. Non-volatile memory embedded in a conventional logic process and methods for operating same
US9262326B2 (en) * 2006-08-14 2016-02-16 Qualcomm Incorporated Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem
US20080162869A1 (en) * 2006-12-29 2008-07-03 Intel Corporation Address hashing to help distribute accesses across portions of destructive read cache memory
US7613061B2 (en) * 2007-11-30 2009-11-03 Agere Systems Inc. Method and apparatus for idle cycle refresh request in DRAM
US8112604B2 (en) * 2007-12-17 2012-02-07 International Business Machines Corporation Tracking load store ordering hazards
US8131953B2 (en) * 2007-12-17 2012-03-06 International Business Machines Corporation Tracking store ordering hazards in an out-of-order store queue
US20090182977A1 (en) * 2008-01-16 2009-07-16 S. Aqua Semiconductor Llc Cascaded memory arrangement
JP5189887B2 (ja) 2008-04-28 2013-04-24 ローム株式会社 強誘電体メモリ装置およびその動作方法
JP5237731B2 (ja) * 2008-09-10 2013-07-17 スパンション エルエルシー メモリシステム、メモリ装置、メモリアクセス方法
US8433880B2 (en) 2009-03-17 2013-04-30 Memoir Systems, Inc. System and method for storing data in a virtualized high speed memory system
US9442846B2 (en) 2009-03-17 2016-09-13 Cisco Technology, Inc. High speed memory systems and methods for designing hierarchical memory systems
TWI425508B (zh) * 2009-04-23 2014-02-01 Orise Technology Co Ltd 具隱藏更新及雙埠能力之sram相容嵌入式dram裝置
US8108621B2 (en) * 2009-05-27 2012-01-31 Via Technologies, Inc. Data cache with modified bit array
US8108624B2 (en) * 2009-05-27 2012-01-31 Via Technologies, Inc. Data cache with modified bit array
US8347027B2 (en) * 2009-11-05 2013-01-01 Honeywell International Inc. Reducing power consumption for dynamic memories using distributed refresh control
WO2011075167A1 (en) * 2009-12-15 2011-06-23 Memoir Systems,Inc. System and method for reduced latency caching
US20130329553A1 (en) 2012-06-06 2013-12-12 Mosys, Inc. Traffic metering and shaping for network packets
US9496009B2 (en) 2012-06-06 2016-11-15 Mosys, Inc. Memory with bank-conflict-resolution (BCR) module including cache
US8484418B2 (en) * 2010-10-22 2013-07-09 Intel Corporation Methods and apparatuses for idle-prioritized memory ranks
US8570790B2 (en) * 2011-01-13 2013-10-29 Cypress Semiconductor Corporation Memory devices and methods for high random transaction rate
WO2013106210A1 (en) 2012-01-10 2013-07-18 Intel Corporation Electronic apparatus having parallel memory banks
US8824196B2 (en) 2012-03-30 2014-09-02 International Business Machines Corporation Single cycle data copy for two-port SRAM
US9213640B2 (en) * 2013-04-17 2015-12-15 Advanced Micro Devices, Inc. Promoting transactions hitting critical beat of cache line load requests
US9449032B2 (en) * 2013-04-22 2016-09-20 Sap Se Multi-buffering system supporting read/write access to different data source type
WO2015065426A1 (en) * 2013-10-31 2015-05-07 Hewlett-Packard Development Company, L.P. Memory access for busy memory
US10020045B2 (en) * 2013-11-26 2018-07-10 Micron Technology, Inc. Partial access mode for dynamic random access memory
US9916261B2 (en) * 2014-05-19 2018-03-13 Infineon Technologies Ag Randomized memory access
KR102161311B1 (ko) * 2014-12-03 2020-10-05 에스케이하이닉스 주식회사 메모리 컨트롤러
FR3032814B1 (fr) * 2015-02-18 2018-02-02 Upmem Circuit dram muni d'un processeur integre
US10229047B2 (en) * 2016-08-06 2019-03-12 Wolley Inc. Apparatus and method of wear leveling for storage class memory using cache filtering
US11237758B2 (en) * 2016-08-06 2022-02-01 Wolley Inc. Apparatus and method of wear leveling for storage class memory using address cache

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330852A (en) 1979-11-23 1982-05-18 Texas Instruments Incorporated Semiconductor read/write memory array having serial access
JPS58155596A (ja) 1982-03-10 1983-09-16 Hitachi Ltd ダイナミツク型mosram
US4625301A (en) 1983-11-30 1986-11-25 Tandy Corporation Dynamic memory refresh circuit
US4810643A (en) 1985-08-23 1989-03-07 Kirin- Amgen Inc. Production of pluripotent granulocyte colony-stimulating factor
JPH0612616B2 (ja) 1986-08-13 1994-02-16 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
US5033027A (en) 1990-01-19 1991-07-16 Dallas Semiconductor Corporation Serial DRAM controller with multi generation interface
EP0811979B1 (de) * 1990-12-25 2004-02-11 Mitsubishi Denki Kabushiki Kaisha Halbleiterspeichervorrichtung
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JPH04372790A (ja) * 1991-06-21 1992-12-25 Sharp Corp 半導体記憶装置
DE69324508T2 (de) 1992-01-22 1999-12-23 Enhanced Memory Systems, Inc. DRAM mit integrierten Registern
GB2265035B (en) 1992-03-12 1995-11-22 Apple Computer Method and apparatus for improved dram refresh operations
US5471601A (en) * 1992-06-17 1995-11-28 Intel Corporation Memory device and method for avoiding live lock of a DRAM with cache
US5617551A (en) 1992-09-18 1997-04-01 New Media Corporation Controller for refreshing a PSRAM using individual automatic refresh cycles
JP3026474B2 (ja) 1993-04-07 2000-03-27 株式会社東芝 半導体集積回路
KR950014089B1 (ko) 1993-11-08 1995-11-21 현대전자산업주식회사 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치
US5450364A (en) 1994-01-31 1995-09-12 Texas Instruments Incorporated Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices
JP3165585B2 (ja) 1994-05-13 2001-05-14 シャープ株式会社 情報処理装置
KR0135699B1 (ko) * 1994-07-11 1998-04-24 김주용 셀프-리프레쉬 가능한 듀얼포트 동적 캠셀 및 리프레쉬장치
JPH08129882A (ja) * 1994-10-31 1996-05-21 Mitsubishi Electric Corp 半導体記憶装置
TW358907B (en) 1994-11-22 1999-05-21 Monolithic System Tech Inc A computer system and a method of using a DRAM array as a next level cache memory
US5737748A (en) 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
US5873114A (en) 1995-08-18 1999-02-16 Advanced Micro Devices, Inc. Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles
JP3352577B2 (ja) 1995-12-21 2002-12-03 インターナショナル・ビジネス・マシーンズ・コーポレーション 記憶装置
EP0794497A3 (de) 1996-03-08 2000-10-11 Matsushita Electric Industrial Co., Ltd. Speicherauffrischungssteuerverfahren und -gerät
US5748547A (en) 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US5784705A (en) 1996-07-15 1998-07-21 Mosys, Incorporated Method and structure for performing pipeline burst accesses in a semiconductor memory
JP3706212B2 (ja) * 1996-10-30 2005-10-12 沖電気工業株式会社 メモリ装置
US5940851A (en) 1996-11-27 1999-08-17 Monolithic Systems, Inc. Method and apparatus for DRAM refresh using master, slave and self-refresh modes
KR100243335B1 (ko) * 1996-12-31 2000-02-01 김영환 독립적인 리프레쉬 수단을 가지는 데이지 체인 구조의 반도체 장치
US5822265A (en) 1997-07-29 1998-10-13 Rockwell Semiconductor Systems, Inc. DRAM controller with background refresh
US5999474A (en) 1998-10-01 1999-12-07 Monolithic System Tech Inc Method and apparatus for complete hiding of the refresh of a semiconductor memory

Also Published As

Publication number Publication date
JP4025509B2 (ja) 2007-12-19
EP1119862A1 (de) 2001-08-01
US5999474A (en) 1999-12-07
WO2000019445A1 (en) 2000-04-06
DE69913366T2 (de) 2004-05-27
TW476960B (en) 2002-02-21
EP1119862B1 (de) 2003-12-03
WO2000019445B1 (en) 2000-05-25
US6449685B1 (en) 2002-09-10
JP2002526882A (ja) 2002-08-20
US20020056022A1 (en) 2002-05-09

Similar Documents

Publication Publication Date Title
DE69913366D1 (de) Lese/schreibe-puffern für ein komplettes verdecken des auffrischen eines halbleiterspeichers und verfahren zum betreiben derselben
DE69404674D1 (de) Speicherkarte und verfahren zum betrieb
DE59610918D1 (de) Magnetische lagervorrichtung und verfahren zum betrieb derselben
DE69532126D1 (de) Verfahren zum sammeln und verarbeiten visueller und räumlicher positionsinformation
DE69724862D1 (de) Verfahren und Anordnung für die Zugangs- und Informationsverfälschungskontrolle in Rechnersystemen
DE69720109D1 (de) Anlage und Verfahren zum Lesen von Fingerabdrücken
DE69423662D1 (de) Aufzeichnungsgerät und Aufzeichnungsverfahren für ein Aufzeichnungsmedium
DE69717409D1 (de) Verfahren, anordnung und aufzeichnungsmedium zur befehlseingabe
DE69907250D1 (de) Verfahren und anordnung zur verlängerung der verfügbaren auffrischungszeit eines 1-t sram-kompatibelspeichers
DE19983420T1 (de) Verfahren und Einrichtungen zum Aktualisieren eines nicht-flüchtigen Speichers
DE69527563D1 (de) Automationssystem und -verfahren zum LSI-Entwurf
DE69528851D1 (de) Einchipsteuerungsspeicheranordnung und eine Speicherarchitektur und Verfahren zur Inbetriebnahme derselben
DE69739138D1 (de) Verfahren und system zum ausfallgesicherten programmieren eines nichtflüchtigen speichers
DE69933720D1 (de) Anordnung und Verfahren zum Eingeben von Koordinatenwerten
DE69621165D1 (de) Ferroelektrischer Speicher und Verfahren für seine Betriebswirkung
DE69405740D1 (de) Verfahren und anordnung für bewegungskompensierende interpolation
DE69726103D1 (de) Verfahren zum Schreiben eines Servomusters für magnetische Plattenlaufwerke und dieses Verfahren verwendendes magnetisches Plattenlaufwerk
DE69910785D1 (de) Einrichtung und verfahren für eine antriebseinheit eines fahrzeugs
DE69624155D1 (de) Ferroelektrischer Speicher und Verfahren für seine Betriebswirkung
DE59804197D1 (de) Verfahren zum betrieb eines sensorsystems und sensorsystem
DE69905350D1 (de) Fräswerkzeug und verfahren zum fräsen
DE69935693D1 (de) Bibliotheksvorrichtung für aufzeichnungsträger und verfahren zum betreiben derselben
DE69600963D1 (de) Verfahren und Schaltkreis zum Programmieren und Löschen eines Speichers
DE59912179D1 (de) Turbomaschine und Verfahren zum Betrieb derselben
DE69820594D1 (de) Anordnung und Verfahren zum Lesen von nichtflüchtigen Speicherzellen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition