DE3483576D1 - Tor-schaltungsanordnung. - Google Patents

Tor-schaltungsanordnung.

Info

Publication number
DE3483576D1
DE3483576D1 DE8484308520T DE3483576T DE3483576D1 DE 3483576 D1 DE3483576 D1 DE 3483576D1 DE 8484308520 T DE8484308520 T DE 8484308520T DE 3483576 T DE3483576 T DE 3483576T DE 3483576 D1 DE3483576 D1 DE 3483576D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
gate circuit
gate
arrangement
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484308520T
Other languages
English (en)
Inventor
Hirokazu C O Fujitsu Lt Suzuki
Takehiro C O Fujitsu L Akiyama
Teruo C O Fujitsu Ltd Morita
Hirofumi Takeda
Hikotaro Masunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58232531A external-priority patent/JPS60124122A/ja
Priority claimed from JP14958784A external-priority patent/JPS6130117A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3483576D1 publication Critical patent/DE3483576D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/296—Time-programme switches providing a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Circuits Of Receivers In General (AREA)
DE8484308520T 1983-12-09 1984-12-07 Tor-schaltungsanordnung. Expired - Fee Related DE3483576D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58232531A JPS60124122A (ja) 1983-12-09 1983-12-09 論理ゲ−ト回路
JP14958784A JPS6130117A (ja) 1984-07-20 1984-07-20 ゲート回路装置

Publications (1)

Publication Number Publication Date
DE3483576D1 true DE3483576D1 (de) 1990-12-13

Family

ID=26479423

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484308520T Expired - Fee Related DE3483576D1 (de) 1983-12-09 1984-12-07 Tor-schaltungsanordnung.

Country Status (4)

Country Link
US (1) US4645958A (de)
EP (1) EP0151875B1 (de)
KR (1) KR900002599B1 (de)
DE (1) DE3483576D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU591747B2 (en) * 1986-01-16 1989-12-14 Tandem Computers Incorporated Delay regulation circuit
US4894791A (en) * 1986-02-10 1990-01-16 Dallas Semiconductor Corporation Delay circuit for a monolithic integrated circuit and method for adjusting delay of same
US4862020A (en) * 1988-06-20 1989-08-29 Tektronix, Inc. Electronic delay control circuit having pulse width maintenance
US4973052A (en) * 1989-01-13 1990-11-27 Conti Donald J Interactive motion sensing toy
US5210450A (en) * 1990-04-16 1993-05-11 Tektronix, Inc. Active selectable digital delay circuit
US5231319A (en) * 1991-08-22 1993-07-27 Ncr Corporation Voltage variable delay circuit
JPH0563525A (ja) * 1991-08-29 1993-03-12 Nec Corp パルス幅可変回路
US5600273A (en) * 1994-08-18 1997-02-04 Harris Corporation Constant delay logic circuits and methods
JPH08125509A (ja) * 1994-10-25 1996-05-17 Mitsubishi Electric Corp 可変遅延回路、リング発振器、及びフリップフロップ回路
US5986492A (en) * 1995-06-05 1999-11-16 Honeywell Inc. Delay element for integrated circuits
JP3460913B2 (ja) * 1995-09-29 2003-10-27 旭化成マイクロシステム株式会社 可変遅延時間発生回路とその方法
US20040003194A1 (en) * 2002-06-26 2004-01-01 Amit Bodas Method and apparatus for adjusting DRAM signal timings
AU2003267410A1 (en) * 2002-09-27 2004-04-23 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung Transistor circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180750A (en) * 1977-03-15 1979-12-25 Pioneer Electronic Corporation Transistor switching circuit with shortened response time
JPS58125915A (ja) * 1981-12-29 1983-07-27 Fujitsu Ltd バイアス回路
JPS58184817A (ja) * 1982-02-26 1983-10-28 Yokogawa Hewlett Packard Ltd 遅延回路
US4516041A (en) * 1982-11-22 1985-05-07 Sony Corporation Voltage controlled variable capacitor

Also Published As

Publication number Publication date
EP0151875A3 (en) 1987-07-15
EP0151875A2 (de) 1985-08-21
KR900002599B1 (ko) 1990-04-20
EP0151875B1 (de) 1990-11-07
KR850005057A (ko) 1985-08-19
US4645958A (en) 1987-02-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee