DE2321901A1 - SYSTEM FOR DETECTING FREQUENCY DIFFERENCES OF AN UNKNOWN SIGNAL FROM A RATED FREQUENCY - Google Patents

Description

Patent attorney

Dip mg.

D-8023 /'/..'m.jie'- Pullach
Wiener5lr.2, T.Mchr..7 <i30570,7931782

vI / Mü-Paris file: 4886-A 8023 Pullach, April 30, 1973

THE BENDIX CORPORATION, Executive Offices, Bendix Center, Southfield, Michigan 48 075, USA

System for detecting frequency deviations of an unknown signal from a nominal frequency

There are a number of use cases where it is desirable is to compare an unknown frequency with a known frequency and provide an output that is a Represents the frequency difference between the unknown signal and the signal of the known frequency. One possible application This technique is found in sonar systems to make reflections better to distinguish between moving objects and stationary objects. Typically sends A sonar system in the course of echolocation or distance measurement emits a series of pulses that consist of many cycles of one High frequency signal. A sonar pulse can therefore be in the Of the order of 30 milliseconds in length, which consists of quite a number of cycles of a carrier frequency, which can be of the order of 10 KHz. When this impulse is reflected off an object and towards the sonar transducer returned, there can be fluctuations in the carrier frequency be detected in order to provide an immediate display of a locating object in motion.

In a known system, this result is achieved

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a phase slope network with a delay line is used, which consists of a series of resonance circles. This delay line represents a comparative large, heavy and expensive component. In such a system, the received signal becomes the phase accident network in which it is delayed a fixed period of time and then compared to itself. Obvious is it is desirable to make the line as long as possible for maximum delay and greater sensitivity to achieve as long as the delay is noticeably shorter than the total pulse length or pulse duration, so that the comparison can take place. It can therefore be said that the longer the delay, the better the frequency error signals are however, as the delay line becomes larger, the inconvenient properties such as size, weight and cost also increase.

Another disadvantage is that the longer the delay line is, the more it becomes necessary that the individual components are very stable, and the more difficult it becomes to provide components with sufficient stability during production.

Another attempt or approach that has been taken for this use case is a phase-locked loop. This is a well known technique that can be implemented with relatively few components and thus some of the Make the size and cost of the delay line as outlined above avoided. This attempted solution However, it is also subject to the instability of the components and offers little advantage in terms of noise or noise discrimination, so that both the stability and the noise in the arrangement with the phase-locked loop the Make the whole thing questionable.

The disadvantages inherent in this technique, essentially

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Analog techniques can be largely eliminated by applying digital techniques, thereby reducing the reliance on the extreme stability of the components is degraded. In the system according to the present invention, the input signal , which can consist of both short and long pulses from a carrier having a frequency that is either is obtained directly or by superimposition translation from a higher carrier frequency such as 2 KHz and the frequency fluctuations, such as is subjected, for example, due to the Doppler effect, fed to a circuit which has a single output pulse for each cycle of the input signal and these pulses are used to divide a flip-flop binary to drift. The output of the flip-flop consists of a series of pulses with the length of each cycle used for this purpose will be able to control the timing cycle during which the pulses of a much higher reference frequency, such as 2 MHz can be counted and stored. When the next input cycle is counted, the previous ones will be saved Counting steps are supplied to the output to which a digital output device or a digital / analog converter can be connected.

In some applications it is necessary to use the disturbance variables or Pay attention to noise in the input signal and it is known that there is no usable input information outside of a given frequency range. For such applications, means are provided to cancel all reference cycles that are below a frequency of which is known to represent the lowest frequency of useful information, and these means also serve to erase of the input pulses containing cycles of a number greater than that containing useful information contains, since these impulses largely consist of disturbance variables. A main counter is initiated, only these counting steps to save that are above a minimum with the help of

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the use of facilities such as a minimum counter or a multivibrator that changes state upon occurrence of a mini-space count-it to cause only Counting steps are stored in the main counter that are above the minimum, over-range counting steps are saved by the Use of gating devices that cause the counter to stop counting when the maximum counting step is reached is ignored and which then holds back the stored count or prevents it from being switched to the output until the Counter is reset to zero for a new pulse count.

Further advantages and details of the invention can be found in the following description of exemplary embodiments with reference to the drawing.

It shows:

Fig. 1 is a block diagram of a frequency measurement system

according to the invention in its basic form;

Fig. La a series of graphical representations of white. lenforms that are found at various points in the

Devices of Figures 1 and 2 appear;

FIG. 2 is a block diagram of a further embodiment of the frequency measurement system according to the invention with devices to limit the frequency response behavior within certain limits;

Fig. 3 is a block diagram of yet another embodiment of the frequency measurement system according to the invention, wherein the response limiting device of Figure 2 is used, but in a somewhat simplified embodiment; and

FIG. 4 is a block diagram of a simplified analog evaluation system which can be used with any of the embodiments according to Figures 2, 1 and 3

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2321301

can be det.

In FIG. 1, an electrical alternating current signal with an unknown frequency f, which, however, is determined to be located between certain defined limits, is fed to a zero crossing detector 10, which generates a sharp output pulse at every positive zero crossing of f or at every crossing of the Zero stress axis generated. A typical Bhoortungssonargerät can generate a series of pulses and. Send, each of which is 30 milliseconds long or lasts (see Figure IA, curve 1), which consists of a carrier signal of 2KHz (see Figure IA, curve 2). When these transmitted pulses impinge upon an in motion reflector _s so is 2 kHz carrier is increased or decreased in frequency in proportion to the relative speed and direction of movement between the transmitting transducer and the locating object as been known from the Doppler effect . If there is no speed difference, the reflected frequency is exactly the transmitted frequency and the output of the zero crossing detector 10, as shown in Figure 1A (3), consists of a series of sharp pulses of a given polarity at a frequency of 2KHz. When an increase in frequency occurs due to the movement or speed of the reflective object moving towards the receiving transducer, the pulse train is increased and the interval between the pulses decreases proportionally. Should the reflective object move away from the transducer, the pulse train will decrease and the interval between the pulses will increase. Therefore, the interval between the pulses at the output of the zero passage detector 10 is proportional to the unknown frequency f.

The pulse signal from the zero crossing detector 10 is fed to a flip-flop circuit of "T" or toggle type 12, the output pulses alternately / Q and § generated. An impulse of Q becomes

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fed to an AND gate 10 and goes to a transmission gate 16. The other pulse 5 goes to an AND gate 18 and to a transmission gate 20. A known reference frequency of a value such as ±, by way of example, IMHz, becomes as well the gate 14 as well as the gate l8 and can pass through them get to the counters 22 or 24 only if the in Readiness-setting impulse of Q or δ. is also present. This is shown in FIG. 1A, curves 4 and 5, which reproduce the output signals from the gates 14 and 18, respectively. If therefore a pulse from terminal Q is present, the counter 22 counts a train of pulses at the reference frequency, while the Gate 16 opens to transmit a previously stored count of pulses from counter 24 to the digital output, like this is illustrated. This pulse output variable, the count or counting step of which is directly proportional to the unknown frequency f

can be a digital display device or a digital-to-analog converter 26 supplied Weitfen, which is an analog output variable generated whose voltage is proportional to the number of counting steps stored in the counter and thus to f ". When a Pulse is present at §, the gate transmits 18 pulses with the reference frequency to the counter 24, which counts and stores them, while the transmission gate 20 passes the count present in the counter 22 to the output. Therefore, the counters 22 operate and 24 such that they alternately store pulses at the reference frequency in an amount proportional to f, and that they deliver these impulses to the output.

Figure 2 shows a block diagram of the system similar to that of Figure 1, but with an additional device for limiting the output variable is intended to be within a given range. There is a great deal in a sonar use case Noise or noise is present in the received signals and a large part of it is above or below the frequency range any useful information. A returned signal from a 2KHz carrier would last for a 500 microsecond period.

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and would be subject to Doppler fluctuations, for example between 450 microseconds and 550 microseconds are. This Doppler-variable signal is counted with the help of the much higher frequency reference signal and it can then frequency differences are determined over a range of 100 cycles of the reference frequency. In this way it becomes possible cancel all counted pulses below a minimum amount, such as 450 cycles. If the clock or reference frequency is compared to the received frequency, there is a range of counting steps or a counting difference between Zero and 100. This output can then be used in a digital to analog converter in such a way that 0 is represented by -5 volts and 100 counts by +5 Volts are represented. The output variable passes through or crosses zero volts at 50 counting steps. Because zero volts one Doppler shift of / or a change in speed

of / represent can be a simple threshold responsive Eliminate circuit voltages below a given value that represent speeds that are too slow are to be of interest.

As in the case of FIG. 1, the unknown frequency f is fed to a zero crossing detector 30 which generates a gate control pulse for a flip-flop 32 in the same way as in the device of FIG. The output of the flip-flop 32 again consists of a pulse that appears either at Q or at $, the duration or length of which is determined by the frequency of the unknown signal is determined. Pulses from Q are then applied to a two input AND gate 34, and one as well AND gate 36 with three inputs. Alternatively, a pulse at 5 is sent to a two input AND gate 38 and likewise to an AND gate 40 with three inputs. The Q and C§ Pulses operate in the same manner previously described to produce alternating strings of pulses of the reference frequency for the counters 42 and 44 are to be provided, which alternately store these impulses.

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brazen and spend. Should be oversized or over the area lying count occur which is fed to one of the counters, a signal is one of two R-S flip-flop circuits 54 and 56 and is also on lines 46 or 48 is fed back to an inverter of the inverter pair 50 and 52, which, after inverting the signal, it the gates 36 and 40 supplies, whereby these gates are caused to interrupt the delivery of the reference frequency to the counters.

The counters 42 and 44 also differ from the counters 22 and 24 in that they have input pulses for the number of the minimum count (450 cycles) at the S terminal during their counting cycle provide one of the Plip-Plps 54 and 56, and these circuits respond to this count by providing an output at port Q, thereby enabling a standby Signal to one terminal of the AND gates 34 or 38 to be provided. These At this point in time, gates do not cause the blocking circuits or circuits 58 or 60 to conduct, since this is not the case at the '"second input required signal is available. Therefore, when a signal is provided from the Q terminal of flip-flop 54, it is the gate 38 is not brought into the conductive state, since the §- Signal from flip-flop 32 does not exist and does not exist will be until the counter 42 has finished counting. When the count is within the desired range, save the counters 42 and 44 the counting steps above the minimum value. If an over-range count is detected, a ^ Signal fed back on line 46 and causes the gate 36 prevents the supply of the pulses to the counter 42, as has already been explained. The counter 42 then holds the maximum Count until it is reset for a new cycle. That. Reset signal can come from a number of sources, however, the output of the zero crossing detector 30 is for

very useful for this purpose. This causes the overrange count is ignored by the system.

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- y -

During the time during which the counter 42 has a correct or valid count accumulates, the blocking circuit 60 switches the count or count stored in the previous cycle counter 44. Number for digital output or digital-to-analog converter 62 in essentially the same manner as was described with reference to the embodiment according to FIG. So that the blocking circuit 60 is conductive, it must be switched on by the gate 34, which only responds to both signals at the terminals Q of the flip-flops 32 and 56, which must be supplied at the same time, responds.

The system of FIG. 3 has essentially the same initial properties as the system according to FIG. 2, but manages with a significantly reduced number of components. The unknown signal f is fed to a zero crossing detector 66 which, as already described, generates an output pulse to the S terminal of an RS-type flip-flop 68. Any pulse received at S results in an output variable at terminal Q, which causes a gate 70 to pass the pulses from the reference frequency source to the minimum counter 72. When the counter 72 has reached the minimum counting step, an output variable appears for a gate 74, which is also switched so that it can receive the reference frequency pulses. The initial counting steps above the minimum counting step cause the latch circuit 78 to pass the count existing in the main counter 76 to the output and to reset the main counter 76 and the minimum counter 72 to zero. You also provide an input signal for connection I? of the flip-flop 68, which switches its output variable from Q to Q, whereby a gate 78 * is set to standby, and the main counter 76 is caused to begin counting and storing the reference frequency pulses. This count is accumulated in the counter 76 until the next output variable of the zero crossing detector appears, whereby the flip-flop 68 is reset to Q and 5 is erased or switched off, whereby the counter

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ler 76 is stopped; or, if an overrange count is recorded was, this sets a hold input in readiness and causes the counter 76 at the maximum count value to stop.

In the case of a minimum count or minimum count, after the next pulse from the fcector 66, the output variable of the gate 7 * 1 switches the blocking circuit 78 to transmit the maximum count from the main counter 76 to the output. In this case, the overrange signal is simply kept at the maximum value and it is given the opportunity to pass, so that it is not eliminated as in the system according to FIG. Should it be desired to eliminate this group of impulses, this can easily be done. For example, the gate Th can be replaced by a gate with three inputs, such as the gate designated 36 or 40 in FIG so that the full count in counter 76 is reset to zero before the next inhibit signal occurs. It should be emphasized that the systems described provide a count which is indicative of the length or duration of each individual cycle of the input signal, regardless of whether this input signal is continuous or discontinuous.

As already described above, there is the output variable the locking circuit 78 from a digital signal which a digital-to-analog converter 80 can be fed to a to provide an analog output variable. This can also be fed to a digital display device and / or evaluation device will. A simple analog output arrangement is illustrated in Figure 4, the analog output variable from the digital / Analog converter 80 is fed to a low-pass filter 82 in order to avoid any undesirable high-frequency interference or noise

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see remove, and then a digital display device 84 and an absolute value circuit 86, all of which Output pulses converted to the same effective polarity. This absolute value signal is then fed to a digital comparison stage 88, in which this signal is compared with a reference signal which has a minimal Doppler effect to be displayed or represented. Frequencies that are above this reference frequency then become an output device such as a video motor of a cathode ray tube circuit to illuminate the tube.

It should be emphasized that a number of other evaluation arrangements can be used. Changes can also be made to the systems described in order to adapt them to specific use cases to adjust. It may be desirable to have all minimal counts to include and exclude all counts above a given number, or all counts above to include a minimum. It may also be desirable to keep all counts above the minimum just up to the limit to include a minimum count. The external evaluation device, such as the digital / analog converter, can also be used be calibrated to be responsive to any threshold of minimum or maximum count applied to it. All such modifications and variations, as those skilled in the art will recognize, fall within the scope of the present invention.

All details which can be seen in the description and shown in the drawing are important for the invention.

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Claims (7)

.- 12 - Claims Iy system for detecting frequency deviations of an unknown signal from a nominal frequency, characterized in that it has the following features and devices: means for feeding the unknown signal (f ") to a zero crossing detector (10; 30; 66) in order to provide an output signal, the period of which fluctuates with the frequency of a complete cycle of the unknown signal (f _Y ); Gate means (I4, 18; 36, 40; 70, 74, 78 ') receiving a reference frequency signal; electrical switching means (12; 32; 68) generating signals from the output signal to enable the gate means (14, 18; 36, 40; 70, 78 ') to conduct the reference frequency signal for the period; Counter means (22, 24; 42, 44; 72, 76) responsive to the gated reference signal and counting and storing the reference frequency signal for the periods and means for resetting the counting means (22, 24; 42, 44; 72, 76) on End of each such period; an output device (26; 62; 80); and gate control means (20, 16; 58, 60; 78) responsive to the electrical switch means (12; 32; 68) for at least a portion of those stored in the counting means (22, 24; 42, ¹ ^ J 76) To transmit counting or counting steps to the output device (26; 62; 80) in such a way that the output device (26; 62; 80) receives a count which is indicative of the duration or the length of each complete cycle of the unknown signal (f) is. 2. System according to claim 1, characterized in that the output device (26; 62; 80) describe a digital-to-an & og converter having. 3. System according to claim 1, characterized in that the count of the unknown signal regardless of whether the input signal is continuous or uniform or 409846/05 8 6 is discontinuous. 4. System according to claim 1 ·, characterized in that the gate means comprises a first (36) and a second (40) gates which receive the reference frequency signal, that further the electrical switch means (32) is responsive to the output signal to alternate the first (36) and the second ( ¹ IO) gate in readiness, so that the reference frequency signal for the period of alternating complete cycles of the unknown will. Signal (f) passed or passed ^ that further the counter devices first (42) and second (44) counters responsive to the gated reference signal and count and store this for the period of the alternating complete cycles of the unknown signal (f), and that V X ter the gate control device comprises a third (38) and a fourth (34) gate, which respond to the standby signals respond from the electrical switch device (32) and connect the first (42) and the second (44) counter so that, when the first counter (42) counts cycles of the reference signal, the third gate (38) blocks the output of the first counter (42) and the fourth gate (34) the count accumulated or stored in the second counter (44) to the output device (62) conducts, taking a count indicative of the duration or length of each complete cycle of the unknown signal (f). 5. System according to claim 4, characterized in that first and second flip-flop stages (54, 56) are provided which are connected to each the first and second counters (42, 44) are connected; that a fifth (38) and a sixth (3 * 0 gate is provided and that these gates are connected so that they receive signals from the first and the second flip-flop stage (5 ^, 56) and that they receive ready-setting signals from the electrical switch means (32) so that when both the signals also from the first and second flip-flop stage (54.56) l / 409846/05 8 6 Acknowledgment signals are present, either the fifth (38) or the sixth (34) gate operates to the count of the first (42) 'or the second counter (44) to the output device (62) to submit. 6. System according to claim 5, characterized in that the first and the second flip-plop stage (54,56) on the occurrence of a Address a count that is above a given number /, to stop the first (42) or second (44) from collecting counting steps and to keep the stored count to prevent '. 'before resetting the first (42) or the second counter (44) for the receipt of the count to arrive at the output device (62). 7. System according to claim 1, characterized in that the gate means comprises a first (70) and a second gate (78 ¹ ) which receives a reference frequency signal which the counting means has a minimum counting step counter (72) and a main counter (76 contains) that further electrical switch means (68) responsive to the output signal for one of the first ((setting 70) and the second gate 78 ^T) in readiness to conduct the reference frequency signal for Minimumzählschritt counter, and in that also a third Gate (74) is provided and is connected to the minimum count counter (72) and is responsive to the occurrence of a minimum count to produce an output signal which the switching means (68) from the first gate (70) to the second Gate (78 ·) switches, so that thereby the second gate (78 *) is set in readiness to pass the reference frequency signal to the main counter (76), and which gate the existing count in the main count The counter (76) switches to the output device (80) and resets the main counter (76) to zero. 409846/0583 Blank page