DE19809554A1 - Silicon carbide semiconductor device - Google Patents

Abstract

A semiconductor device has (a) a first conductivity type single crystal silicon carbide semiconductor substrate bearing a first conductivity type silicon carbide epitaxial layer; (b) a second conductivity type silicon carbide first semiconductor region formed on the epitaxial layer; (c) a first conductivity type silicon carbide second semiconductor region formed on the first region; (d) a first conductivity type silicon carbide third semiconductor region formed on the first region, connected to the epitaxial layer and the second region and having a higher resistance than the substrate; and (e) a gate electrode formed on an intermediate insulation layer on the third region. The third region is depleted when no voltage is applied to the gate electrode so that the device has a normally 'off' characteristic. Also claimed are similar devices in which the third region has a lower dopant concentration than the substrate and in which (i) the third region has a thickness (in the sub-micron range) such that complete depletion occurs when no voltage is applied to the gate electrode or (ii) the impurity concentration of a region of the surface channel layer, existing on the epitaxial layer surface region, is greater than that of the rest of the surface channel layer and of the epitaxial layer so that the conduction resistance is reduced.

Description

The present invention relates to a silicon carbide or SiC semiconductor device, such as an Iso lierschicht field effect transistor and in particular one vertical high-performance MOSFET or metal oxide semiconductor Field effect transistor.

Common is a wide variety of vertical ones MOS transistors and other devices known SiC use. Examples include those in the un Examined Japanese Patent Publication No. 4-23977, U.S. Patent 5,323,040 and Shenoy et al., IEEE Electron Device Letters, Vol. 18, No. 3, pages 93 to 95, March 1997, are described. The ones disclosed in these publications vertical MOS transistors are made with high quality mate materials for a high breakdown voltage and a low voltage on resistance compared to silicon formed MOS transistors.

It is an object of the present invention to provide a Silicon carbide MOS transistor to create what full Makes use of the characteristics of SiC to yet a lower on resistance and still a higher one Breakdown voltage as SiC-MOS transistors in the prior art To achieve technology, and which for an easier Ge custom designed.

This object is achieved by means of the in 1 specified measures solved.

Further advantageous refinements of the present Invention are the subject of the dependent claims.  

According to the invention, the above-mentioned object solving semiconductor device created a semi-lead ter substrate, the silicon carbide of a first conductive type and a silicon carbide epitaxial layer of the first Conductivity type, which is on the main page of the Semiconductor substrate is formed, a first half lead the area on the main surface of the silicon carbide is formed epitaxial layer and silicon carbide one has a second conductivity type, a second semi-lead ter area trained on the first semiconductor area det, the silicon carbide of the first conductivity type and through the first semiconductor region from the Si silicon carbide epitaxial layer of the first conductivity type is separated, a third semiconductor region on the is formed first semiconductor region, the silicon carbide epitaxial layer and the second semiconductor region connects, the silicon carbide of the first conductivity type and has a higher resistance than the silicon card bidepitaxy layer or the semiconductor substrate, and has a gate electrode which coincides with one insulation layer on the third half conductor region is formed, the third semiconductor area is depleted if there is no voltage at the gate elec trode is applied so that the semiconductor device Character normally switched off or in idle state logistics.

According to this structure, the third semiconductor region (the thin channel epitaxial layer) becomes impoverished and has one characteristic normally switched off if none Voltage is applied to the gate electrode. To such Times the third semiconductor area must be impoverished Have layer that is across the full width between the first semiconductor region and the gate insulation film stretches to a normally off character stik, but it is not necessary that the depleted layer completely along the entire length of the  extends third semiconductor region. More specifically, it is Depletion of the third semiconductor region is not necessary there dig where the third semiconductor region joins the second Semiconductor area or the area that extends the Sili cium carbide epitaxial layer of the first conductivity type be stirs (drift range).

In the structure described above, when a Voltage is applied to the gate electrode to an elek form trical field on the gate insulation layer, an enrichment type channel on the third half lead region (the thin channel epitaxial layer) and the charge carriers flow between the source electrode and the drain electrode (that is, an on state is achieved).

This structure can alleviate the problem of a low channel Mobility of an SiC power transistor of an inverter Sion type him solve the state of the art since the device works as an enrichment type. It has been established the that in electronic devices made of Si the Anrei Link layer port mobility much higher than the inverter layer mobility is (see for example p. C. Sun et al., IEEE Transactions on Electron Device, Vol. ED-27, page 1497, 1980). The same applies to on MOS ba based SiC power devices. A great wrinkle The forward resistance can also be used for SiC performance devices of an enrichment type are expected.

The characteristic of the third semiconductor region is by mutual Ver bind the impoverished layer, which is between the Extends the gate electrode and the third semiconductor region, and the depleted layer between the second semiconductor area and the third semiconductor area. Therefore according to the silicon carbide semiconductor device present invention the impurity concentration and  Thickness of the third semiconductor region and the second half conductor area and the gate electrode even then a full permanent depletion of the third semiconductor layer if no voltage is applied to the gate electrode, which is why allows a normally off character Stik is achieved so that it is similar to one normally switched off device used in the prior art can be.

Furthermore, according to the semiconductor device present invention, the impurity concentration of the most semiconductor area and the impurity concentration of the third semiconductor region in which the channel is out is independently controlled to form a silicon carbide semiconductor device with a high breakdown voltage, a low power loss and a low threshold to create value tension. That is, the defect groups tration of the first semiconductor region can be increased so that while a high breakdown voltage between the Source and the drain is maintained, the depth of the first semiconductor region can be shortened by the Junction field effect (JFET effect) to reduce. Except this can be because the impurity concentration of the Ka nals can be reduced to the effect of an interference to reduce oil scatter during charge flow, the channel mobility can be increased. As a result, it is possible to use a silicon carbide semiconductor device high breakdown voltage and low power losses achieve.

The silicon carbide semiconductor device of the present the invention is a planar vertical field effect transi stor, but it can also be used on planar transistors or Transistors with a trench can be applied.

A planar type semiconductor device according to The present invention has a semiconductor substrate  of the first conductivity type, the single-crystalline silicon carbide and a silicon carbide epitaxial layer of the first Conductivity type, which is on the main page of the Semiconductor substrate is formed and a lower Do animal substance concentration than the semiconductor substrate, a first semiconductor base region of a second guide ability type based on a predetermined range of sili Zium carbide epitaxial layer to a predetermined depth is formed, a second semiconductor source region of the first conductivity type based on a predetermined Be Richly formed the base area and a flatter Depth than the base region has a third half lead surface channel layer of the first conductivity type, which consists of silicon carbide and is arranged in such a way that they have the source region and the silicon carbide epitaxy layer of the first conductivity type and the second half conductor base region connects, a gate insulation layer, out on the surface of the surface channel layer is formed, with a gate electrode on the surface of the Surface channel layer is formed, a source electrode trode that is in contact with the base area and the source area is formed, and a drain electrode on the is formed on the back of the semiconductor substrate.

Preferred embodiments of the semiconductor device of the planar type are described below.

• (1) The main surface of the silicon carbide semiconductor substrates is a (0001) -Si surface, a (0001) -C surface, a (1120) -a face or a (1100) prism face. The (0001) -Si area or the (1120) -a area is for the low transition surface state of the silicon card bid / insulator transition preferred.
• (2) The dopant concentration of the surface channel layer is not larger than the dopant concentrations the silicon carbide epitaxial layer and the base region.  
• (3) The gate electrode has a first exit area potential, the base area has a second off pedal work potential, the surface channel layer has a third work function potential and he most, second and third work function potentials set such that the charge carriers of the first guide ability type are depleted in the surface channel layer.
• (4) The first, second and third workforce positions potentials are set such that the charge carriers of the first conductivity type in the surface channel layer are depleted if the gate electrode is in relation to the Drain area is at zero potential.
• (5) The surface channel layer is by epitaxial Growth or ion implantation trained.
• (6) The surface channel layer is by epitaxial Growth developed and the crystal system / polymorphic Silicon carbide, which is the semiconductor substrate, the silicon carbide epitaxial layer, the base region and the sourcebe is rich, is the surface of the silicon carbide channel channel layer different. For example, that is Si silicon carbide, which is the semiconductor substrate, the silicon car bidepitaxy layer, the base region and the source region forms a hexagonal system, while the silicon carbide the surface channel layer is a cubic system.
• (7) The surface channel layer is formed by epitaxial growth, and the silicon carbide that forms the semiconductor substrate, the silicon carbide epitaxial layer, the base region and the source region is 6H-SiC, while the silicon carbide of the surface channel layer is 3 C-SiC.

By using a surface channel layer formed by epitaxial growth in which the silicon carbide crystal system / polymorphic as in item (5) and (6) differs from that of the base, it is possible to have a device with good characteristics and high Realize reliability.

• (8) A portion of the first semiconductor base region is made thicker. This allows a breakthrough occurs more easily.
• (9) In the silicon carbide semiconductor device according to the preceding point (8) is the impurity concentration tion of the thickened region of the first semiconductor base manufactured higher than the impurity concentration of the thinner areas. This further facilitates a through fracture.
• (10) In the silicon carbide semiconductor device according to the previous point (8), the thickened area of the Base area to be formed under the source area. This leaves a shared use of the mask for training that of a deep base region and the mask for formation a source area for manufacturing.
• (11) A silicon carbide epitaxial layer of a first one Conductivity type, which has a lower dopant concentration tration than the semiconductor substrate is on the Main surface of the semiconductor substrate of the first guide ability type, which is made of single-crystalline sili cium substrate, and a first base region of an er most conductivity type that has a predetermined depth points, is on a predetermined area of the surface area of the silicon carbide epitaxial layer. Furthermore, a surface channel layer of the first Conductivity type, which consists of silicon carbide, on the Silicon carbide epitaxial layer arranged, a second Base area of the second conductivity type with a large  greater depth than the first base area on a past agreed area in the first base area and then the mask to form a second base reichs used to create a source area of the first guide ability type, which has a shallower depth than the first Ba sis range, on a predetermined range of the Form surface area of the first base area. After that, a gate electrode is placed on the surface of the top surface channel layer with one in between Gate insulation film formed while a source elec trode is formed, the base area and the Source area touched. Therefore it is possible to use the Sourcebe rich using the mask to form a two th base area to use the mask allow for both purposes.
• (12) In the silicon carbide semiconductor device according to the previous point (8) is the thickened area of the Base area formed at a location that the source area does not overlap. This helps ver breakthrough prevent.
• (13) The surface channel layer, can be a section of the second semiconductor source region overlap. This leaves expanding the contact area from the second half lead tersource area to the surface channel layer.
• (14) In the planar type semiconductor device can be the area of the surface channel layer, which is on the surface area of silicon carbide epitaxy layer, with a lower resistance as the silicon carbide epitaxial layer yet another reduction in forward resistance of the Allow an enhancement type MOSFET. The Durchlaßwi the level of the MOSFET is determined by the contact resistance between between the source electrode and the source region, the inside resistance of the source region, the enhancement channel  stood in the channel area on the surface channel layer is formed, the internal resistance of the rich tion drift resistance of the surface channel layer, the JFET resistance of the JFET area, the internal resistance of the Epitaxial layer, the internal resistance of the semiconductor substrate and the contact resistance between the half lead ter substrate and the drain electrode determines their sum forms the forward resistance.

Hence, by making such sturgeon place concentration of the area of the surface channel layer that rests on the surface area of the epitaxy layer is higher than that of the epitaxial layer is, possible, the resistance of the other areas of the upper surface channel layer as the channel area (Enrichment drift resistance of the channel layer) gladly, which therefore reduces the forward resistance of the MOSFET device. This allows an even lower one for the MOSFET Forward resistance is achieved.

For example, if the surface channel layer through Io is formed and also an ion implant plantation in the other areas of the surface channel layer is executed as the channel area, then the Impurity concentration of the area of the surface channel layer that is on the surface area of the epitaxy layer is located simultaneously with the formation of the Surface channel layer over the impurity concentration the epitaxial layer can be increased. This leaves a simplification production process for silicon carbide semiconductor device too.

The present invention will hereinafter be described with reference to Embodiments with reference to the accompanying Drawing explained in more detail.

Show it:  

Fig. 1 is a schematic cross-sectional view of a power MOSFET of a planar type according to a first embodiment of the present invention;

Fig. 2 to 9 are cross sectional views of a manufacturing method of a planar type for a power MOSFET;

FIG. 10 is a graph showing the relationship between a Oberflächenkanalepitaxieschichtdicke, an impurity concentration and a breakdown voltage;

FIG. 11 is a cross-sectional view of another Her approval process of a planar-type extension for a power MOSFET according to the first embodiment of the present OF INVENTION;

Fig. 12 is a schematic cross-sectional view of a power MOSFET of a planar type in accordance with a second embodiment of the front lying invention;

Fig. 13 to 20 are cross sectional views of a fabrication of a planar type method for a power MOSFET;

Fig. 21 is a schematic cross-sectional view of a power MOSFET of a planar type in accordance with a third embodiment of the front lying invention;

Fig. 22 is a schematic cross-sectional view of a power MOSFET of a planar type in accordance with a fourth embodiment of the front lying invention;

Fig. 23 to 27 are cross sectional views of a manufacturing method of a planar type for a power MOSFET;

FIG. 28 is a cross-sectional view of another Her approval process for a power MOSFET of a planar type the four th embodiment of the present invention according to;

FIG. 29 is a cross-sectional view of still wide ren manufacturing method of a ben efit MOSFET of a planar type in accordance with the fourth embodiment of the present the invention;

Fig. 30 is a schematic cross-sectional view of a conventional MOSFET of an inversion type for explaining the prior art;

FIG. 31 is a cross-sectional view of a vertical power MOSFET according to a fifth example of the present imple mentation OF INVENTION dung;

Fig. 32 is a graph showing the on-resistance of the vertical power MOSFET in Fig. 31 of a gate voltage / drain current characteristic;

Figure 33 to 41 views of a manufacturing method of the vertical power MOSFET in Fig. 31.; and

FIGS. 42 and 43 are cross sectional views of a vertical ben efit-MOSFET according to a sixth and seventh embodiment of the present the invention.

The following is a description of exemplary embodiments in FIG present invention.

A first off is described below management example of the present invention.

Fig. 1 shows a cross-sectional view of a planar vertical power MOSFET having an n-channel according to this embodiment of the present invention. This device can be suitably used as an inverter or an AC voltage generator for a vehicle.

The used silicon carbide semiconductor substrate 1 of an n⁺ type is hexagonal silicon carbide. The silicon carbide semiconductor substrate 1 of the n⁺ type can be cubic crystal. Likewise, the silicon carbide semiconductor substrate 1 of the n⁺ type has the upper side as the main side 1 a and the lower side, which is opposite the main side 1 a, as the rear side 1 b. On the main side 1 a of the silicon carbide semiconductor substrate of the n⁺ type, a silicon carbidepi taxi layer of an n⁻ type (hereinafter referred to as “silicon carbide epi layer of the n⁻ type”) 2 is layered, which has a lower dopant concentration than the substrate 1 .

Here, the top of the silicon carbide semiconductor substrate 1 of the n⁺ type and the semiconductor epi layer of the n⁻ type are the (0001) -Si surface or the (0001) -C surface. Alternatively, the top of the silicon carbide semiconductor substrate 1 of the n⁺ type and the semiconductor epi layer of the n⁻ type can be the (1120) -a surface or the (1100) prism surface. More specifically, a low transition state density of silicon carbide / insulator can be achieved if the (0001) -Si and (1200) -a areas are used.

On predetermined areas of the surface region of the silicon carbide ni-type layer, a silicon carbide base region 3 a of a p⁻ type and a silicon carbide base region 3 b of a p⁻ type are separately formed to a predetermined depth. Likewise, the surface area of Siliziumkar bidbasisbereichs 3a of the p⁻-type is on a vorbe voted region is formed a source region 4 a of the n⁺-type which is shallower than the base region 3 a, and is on a predetermined area of the upper surface area of the Siliziumkarbidbasisbereichs 3 b of the p⁻ type, a source region 4 b of the n⁺ type is formed, which is flatter than the base region 3 b. Furthermore, there is an SiC layer 5 of the n auf type on the silicon carbide epoxy layer 2 of the n Typs type between the source region 4 a of the n Typs type and the source region 4 b of the n⁺ type and on surface areas of the silicon carbide base regions 3 a, 3 b of the p⁻ type provided. That is, the SiC layer 5 of the n⁻ type is arranged such that it connects the source regions 4 a, 4 b on the surface regions of the base regions 3 a, 3 b and the silicon carbide layer 2 of the n des type. This SiC layer 5 of the n⁻ type is formed by epitaxial growth and the crystals of the epitaxial film are 4H, 6H or 3C. Regardless of the underlying substrate 1 , the epitaxial layer can form different crystal types if different conditions of epitaxial growth are used. During operation of the device, it serves as a channel formation layer on the device surface. The SiC layer 5 of the n⁻ type is referred to hereinafter as the surface layer.

Here, the dopant concentration of the surface channel channel layer 5 is a low concentration of approximately 1.0E14 cm ^-3 to 1.0E16 cm ^-3 , which is lower than the dopant concentration of the silicon carbide layer 2 of the n⁻ type and the silicon carbide base regions 3 a, 3 b of the is p⁻-type. This allows that a low forward resistance was achieved.

Furthermore, depressions 6 a, 6 b are formed on the surface of the silicon carbide base regions 3 a, 3 b of the p⁻ type and the source regions 4 a, 4 b of the n⁺ type.

A gate insulation film (silicon oxide film) 7 is formed on the top of the surface channel epi layer 5 and the source regions 4 a, 4 b of the n⁺ type. A polysilicon gate electrode 8 is also formed on the gate insulation film 7 . The polysilicon gate electrode 8 is covered by an insulation film 9 . An oxide film is formed as the insulation film 9 . A source electrode 10 is formed above and the source electrode 10 contacts the source regions 4 a, 4 b of the n⁺-type and the silicon carbide base regions 3 a, 3 b of the p⁻-type. Likewise, a silicon carbide drain layer 11 is formed on the rear side 1 b of the silicon carbide semiconductor substrate 1 of the n⁺ type.

A manufacturing method for a power MOSFET of a planar type is shown in FIGS. 2 to 9.

First, as shown in FIG. 2, an n-type 4H, 6H, or 3C-SiC substrate 1 , that is, an n Typs-type silicon carbide semiconductor substrate 1 is prepared. Here, the thickness of the silicon carbide semiconductor substrate 1 of the n⁺ type is 400 micrometers and the main surface 1 a is the (0001) -Si surface, (0001) -C surface, (1120) -a surface or (1100) - prism surface. A silicon carbide epoxy layer 2 of the n⁻ type is epitaxially grown to a thickness of 5 to 10 micrometers on the main surface 1 a of the substrate 1 . In this embodiment of the present invention, the silicon carbide layer 2 of the n⁻ type receives the same crystals as the underlying substrate 1 for a 4H, 6H or 3C-SiC layer of the n⁻ type.

Also, as shown in FIG. 3, an insulation film 20 is placed on a predetermined area of the n⁻-type silicon carbide layer 2 , and this is used as a mask for ion implantation of group IIIA impurities, that is, B + (boron ions ), Al + (aluminum ions) or Ga + (gallium ions) are used to form the silicon carbide base regions 3 a, 3 b of the p⁻ type. The ion implantation conditions are a temperature of 700 ° C and a dose of 1E14 cm ^-2 .

After removing the insulation film 20 , as shown in FIG. 4, a surface channel epi layer 5 of the n⁻ type is epitaxially grown on the silicon carbide epi layer 2 of the n⁻ type. As the growth conditions, who uses SiH ₄ , C ₃ H ₈ and H ₂ as the source gases, and the growth temperature is 1600 ° C.

Next, as shown in Fig. 5, an insulation film 21 is placed on a predetermined area of the surface channel epi layer 5 and this is used as the mask for ion implantation of N + (nitrogen ions) to source regions 4 a, 4 b of the n ⁺-type. The ion implantation conditions are a temperature of 700 ° C and a dose of 1E15 cm ^-2 .

Also, after removing the insulation film 21 as shown in FIG. 6, the photoresist method is used to place an insulation film 22 on a predetermined area of the surface channel layer 5 , and this is used as a mask for etching a portion of the source areas 4 a , 4 b of the n⁺-type and the silicon carbide base regions 3 a, 3 b of the ⁻-type used by RIE or reactive ion etching to form the recesses 6 a, 6 b. The RIE source gases used here are CF ₄ and O ₂ .

After subsequent removal of the insulation film 22 , as shown in FIG. 7, a gate insulation film (gate oxide film) 7 is formed on the substrate 1 by wet oxidation. The atmosphere temperature is 1080 ° C.

Then, as shown in FIG. 8, a polysilicon gate electrode 8 is deposited on the gate insulation film 7 by LPCVD or chemical vapor pressure vapor deposition. The film formation temperature is 600 ° C.

Next, as shown in FIG. 9, after removing the unwanted portions of the gate insulation film 7, an insulation film 9 is formed to cover the gate insulation film 7 . More specifically, the film formation temperature is 425 ° C and annealing is carried out at 1000 ° C after the film formation.

Also, as shown in Fig. 1, the source electrode 10 and the drain electrode 11 are generated by metal sputtering at room temperature. Then an annealing is carried out at 1000 ° C after film formation.

This completes the power MOSFET of a plana ren type.

Now the functionality (operation) of the vertika len planar power MOSFET explained.

This MOSFET works as a normally switched-off enrichment type, so that when no voltage is applied to the polysilicon gate electrode, the charge carriers of the surface channel layer 5 are completely depleted by the potential caused by the difference in the static potentials of the silicon carbide base regions 3 a, 3 b of the p⁻ type and the surface channel layer 5 and the difference of the work functions of the surface channel layer 5 and the polysilicon gate electrode 8 is generated. Applying a voltage to the polysilicon gate electrode 8 changes the potential difference that is generated by the sum of the work function of the surface channel layer 5 and the polysilicon gate electrode 8 and the externally applied voltage. This allows the channel state to be controlled.

In other words, if the work function potential of the polysilicon gate electrode 8 is defined beitspotential than the first Austrittsar, the work function potential of the Siliziumkarbidbasisbereiche 3 a, 3 b of the p⁻-type is defined as the second work potential and the From work function potential of the surface channel epi-layer 5 is defined as the third work function potential is , then the first to third work function potentials can be set such that the n-type charge carriers are contained in the surface channel epi layer 5 . That is, the first to third work function potentials are set such that the n-type charge carriers (electrons) in the surface channel layer 5 are depleted when the polysilicon gate potential 8 is at zero potential with respect to the drain region.

It continues with the explanation of the operation. An impoverished region is formed in the surface channel epi layer 5 by the electric field generated by the silicon carbide base regions 3 a, 3 b of the p⁻ type and the polysilicon gate electrode 8 . If a positive bias voltage is applied to the polysilicon gate electrode 8 in this state, a channel region of the enrichment type is formed in the surface channel epi layer 5 , which extends from the source regions 4 a, 4 b of the n⁺ type in the direction of the drift region 2 of the expands n aus-type, so that a switching to the on state is effected, which causes the charge carriers to flow between the source electrode 10 and the drain electrode 11 .

Here, the electrons flow from the source regions 4 a, 4 b of the n⁺ type through the surface channel epi layer 5 and from the surface channel epi layer 5 to the silicon carbide epi layer 2 of the n⁻ type. Likewise, the electrons flow vertically to the silicon carbide semiconductor substrate 1 of the n⁺ type after reaching the silicon carbide epoxy layer 2 (the drift region) of the n⁻ type.

However, the voltage applied to the gate electrode 8 must be at least as high as the predetermined threshold voltage V _th . This threshold voltage V _th will now be explained.

As a reference, the threshold voltage V _th for an inversion type MOSFET will be explained as the basis for explaining the threshold voltage V _th for the enhancement type power MOSFET according to this embodiment of the present invention.

Threshold voltages V _th for inversion type MOSFETs are generally expressed by the following equation (1).

V _th = V _FB + 2Φ _B (1)

where V _FB = Φ _ms - (Q _s + Q _fc + Q _i + Q _ss ) / C _oxide
and insertion results in the following equation (2).

V _th = Φ _ms - (Q _s + Q _fc + Q _i + Q _ss ) / C _oxide + 2Φ _B (2)

In general, the energy band is based on the effect of the work function difference (electron energy difference) Φ _ms between the metal and the semiconductor, the fixed charge Q _fc at the transition between the gate oxide film (SiO ₂ ) and the layer of the n⁻ type (here in further referred to as the SiO ₂ / SiC junction), the movable ions Q _i in the oxide film and the surface charge Q _ss curved at the SiO ₂ / SiC junction. Hence, the threshold voltage V _{th is} the sum of the voltage that displaces this energy band curvature and the voltage 2 Φ _B that begins; form an inversion state, and is represented by equations (1) and (2). Q _s represents the space charge in the gate insulation film (oxide film) 7 and C _oxide represents the capacitance of the gate insulation film (oxide film) 7 .

This is known as the basis for the vertical ben efit MOSFET of the enhancement type in accordance with this exporting approximately example of the present invention contemplates, as the energy band of the surface channel layer 5 by the degree of difference in work function V _built at the PN junction (built in the PN junction voltage) for the base regions 3 a, 3 b of the p⁻ type and the surface channel layer 5 compared to the MOSFET of the inversion type is curved and no voltage 2 Φ _B is necessary for an inversion state, the threshold value voltage V _{th being} therefore represented by the following equation (3 ) is shown.

V _th = V _buiilt + Φ _ms - (Q _s + Q _fc + Q _i + Q _ss ) / C _oxide (3)

In other words, since the energy band due to the work function difference V _built on the PN junction side of the surface channel layer 5 , the work function difference Φ _ms between the polysilicon (metal) and semiconductor on the gate insulation film side and the degree of curvature of the energy band caused by the Oxide film is caused ((Q _s + Q _fc + Q _i + Q _ss ) / C _oxide ) to bend, applying an offset voltage will flatten the energy band and cause current to flow. Therefore, the threshold voltage V _th of the enhancement type MOSFET of this embodiment of the present invention is represented by equation (3).

Accordingly, according to this embodiment of the present invention, a voltage which is larger than the threshold voltage V _th , which is represented by equation (3) Darge, is used as the gate application voltage.

Otherwise, the principle of operation of this device similar to that of a vertical channel JFET (see B.J. Baliga, "Modem Power Devices", Kreiger Press, Malabar, Florida, 1992).

This normally off device of the enrichment type can also withstand an avalanche breakdown condition. In order to achieve a vertical power MOSFET of a normally off type, it is necessary that it have a sufficient junction height so that the extended depletion layer in the n⁻ layer does not prevent electrical conduction when no gate voltage is applied. The maximum thickness of the epitaxial growth layer 5 used in the construction of a normally-off planar type MOSFET will depend on the impurity concentration, the SiO ₂ film blanket and the polysilicon conductivity type used for the gate electrode.

With this structure, in order to obtain a sufficient barrier height to prevent conduction between the source and the drain, the thickness of the surface channel channel layer 5 can be determined using the equation (4) given below. The conditions are expressed by the following equation:

Here, Tepi is the height of the depleted layer that diffuses into the n⁻-type layer, N _{D is} the donor concentration in the channel region of the n Typs-type, N _{A is} the acceptor concentration of the base region of the p⁻-type, is V _built the built-in voltage of the PN junction, Φ _{ms is} the difference in the work function of the gate polysilicon (metal) and the semiconductor, Q _{s is} the space charge in the gate insulation film, Q _{fc is} the specified surface charge on the SiO ₂ / SiC junction, if Q _{i are} the mobile ions in the oxide with a charge, Q _{ss are} the charged surface states at the SiO ₂ / SiC junction and C _{oxide is} the capacitance of the gate insulation film.

The first expression on the right side of equation (4) is the degree of expansion of the depleted layer due to a built-in voltage V _built at the PN junction between the surface channel layer 5 and the silicon carbide base regions 3 a, 3 b of the p⁻ type, that That is, the degree of expansion of the depletion layer from the silicon carbide base regions 3 a, 3 b of the p⁻ type to the surface channel layer 5 and the second expression is the degree of expansion of the depletion layer due to the charge and Φ _{ms is} the difference in the work function of the gate polysilicon (metal ) and the silicon carbide channel layer 5 , which represents the degree of expansion of the depletion layer from the gate insulation film 7 to the surface channel layer 5 .

Consequently, if the sum of the expansion of the depletion layer of the silicon carbide base regions 3 a, 3 b of the p⁻ type and the expansion of the depletion layer of the gate insulation film 7 is made larger than the thickness of the surface channel layer 5 , the vertical power MOSFET can be made as a normally off type can be made.

Therefore, the surface channel epi layer 5 must have a low thickness (in terms of submicron order) or it must have a low concentration. That is, when considering the simplicity of training, the thickness is preferably larger from the standpoint of uniformity, and the concentration is preferably higher to ensure impurity inclusion in the device.

Because this vertical power MOSFET's normally switched off type can be manufactured such that no current flows even if due to a device voltage failure or the like no voltage to the gate electrode is applied, it is possible to use a larger Si safety than with a normally switched on type ensure.

Likewise, the two-dimensional numerical simulations have been carried out in order to optimize the element structure parameters, that is to say the thickness and impurity concentration of the surface channel layer 5 of the n⁻ type and the impurity concentration of the silicon carbide base regions 3 a, 3 b of the n⁻ type and to achieve the silicon carbide epoxy layer 2 of an n⁻ type for a device breakdown voltage of 1000 V.

FIG. 10 is a graph showing the relationship between the breakdown voltage, the impurity concentration, and the thickness of the surface channel epi layer 5 of the n⁻ type.

Two different types of dopants have been taken into account for the polysilicon gate electrode 8 in the calculations, that is, one in which p-type impurities have been doped and another in which n-type impurities have been doped. When p-type impurities are doped as the polysilicon gate electrode 8 , the impurity concentrations of the surface epitaxial layer 5 are 1E17 cm ^-3 , 1E16 cm ^-3 and 1E15 cm ^-3 , and when the n-type impurities are doped as the polysilicon gate electrode 8 , the impurity concentration of the surface channel epi layer is 5 1E16 cm ^-3 . It can be clearly seen from FIG. 10 that the breakdown voltage depends on the thickness of the surface channel epi layer 5 . The breakdown voltage depends also of the conductivity type of the polysilicon from which is used for the gate electrode 8, and it is understood that when the surface channel epi-layer 5 has the same impurity concentration, the polysilicon gate electrode 8 of the p-type better than the polysilicon gate electrode 8 of n -Typs (for example, the surface channel epi layer 5 can be made thicker with the same breakdown voltage and impurity concentration). In other words, the breakdown voltage is better when it is of the opposite conductivity type with respect to the surface channel epi layer 5 .

Furthermore, according to this invention, using the surface channel epi layer 5 of the n⁻ type, it is possible to separately control the impurity concentration of the channel region and the impurity concentration of the silicon carbide base regions 3 a, 3 b of the p⁻ type. Consequently, by separately controlling the impurity concentrations from different areas, a power MOSFET having a high breakdown voltage, a low forward resistance and a low threshold voltage is obtained. In other words, according to the prior art planar MOSFET as shown in FIG. 30, it is not possible to separately control the impurity concentrations of the channel and base regions of a second conductivity type to have a higher breakdown voltage, a low forward resistance, and to achieve a low threshold voltage, but this is possible with the device according to the present invention.

Fig. 30 shows a cross-sectional view of a planar type silicon carbide MOSFET in the prior art. In Fig. 30 a Siliziumkarbidepitaxieschicht is stacked 71 of the n⁻-type on a Siliziumkarbidhalbleitersubstrat 70 of the n⁺-type and are on the surface area of the Sili ziumkarbidepitaxieschicht 71 of the n⁻-type a Siliziumkar bidbasisbereich 72 of a p⁻-type and a source region 73 of the n⁺ type by double ion implantation. Likewise, on the n 75-type epitaxial layer 71, there is a gate electrode 75 over a gate insulation film 74 and the gate electrode 75 is covered with an insulation film 76 . A source electrode 77 is arranged to contact the p⁻-type silicon carbide base region 72 and the n⁺-type source region 73 , while a drain electrode 78 is on the back of the n⁺-type silicon carbide semiconductor substrate 70 .

The problems in the prior art are considered with respect to the fact that the MOSFET in the prior art uses the base region 72 and the source region 73 , which are formed by double ion implantation, since the diffusion method cannot be used in SiC. Therefore, the SiC / SiO ₂ junction of a channel region formed by oxidation retains crystal damage due to ion implantation, which leads to a high transition state density. Likewise, due to the poor quality of the ion implantation of the base region 72 of the p⁻ type, which forms the channel layer of the inversion type, obviously no improvement in the channel mobility can be expected. In contrast, in the embodiment of the present invention shown in FIG. 1, a pure transition can be achieved by forming the channel layer with a high quality epitaxial layer 5 .

Likewise, an SiC layer by ion implantation can also be used instead of the surface channel epi layer 5 . That is, while the epitaxial layer 5 has been formed on the substrate in FIG. 4, alternatively, as shown in FIG. 11, N + may be planted in an SiC substrate in order to form a channel formation SiC layer 25 of the n ⁻-Type in the substrate surface area.

In addition to the construction for the above-described embodiment of the present invention, which has been explained for use on a vertical MOSFET with an n-channel, the same effect for vertical MOSFETs with a p-channel can be achieved by swapping the p-type and n -Types can be achieved in Fig. 1.

A second off is described below management example of the present invention.

The second embodiment of the present invention is now emphasizing the differences compared to the first embodiment of the present ing invention explained.

Fig. 12 is a cross sectional view of a MOSFET this embodiment shows ei nes planar type with an n-channel (vertical power MOSFET) according to the present invention.

In Fig. 12 a Siliziumkarbidepischicht 2 is layered n-type with a lower dopant concentration than the substrate 1 on the main surface of a silicon semiconductor substrate 1 of n + type. On predetermined areas of the surface area of this silicon carbide epi layer 2 of the n⁻ type, a silicon carbide base area 3 a of the p⁻ type and a silicon carbide base area 3 b of the p⁻ type are formed separately, which have a predetermined thickness. Likewise, on a predetermined area of the surface area of the silicon carbide base region 3 a of the p⁻ type, a source area 4 a of the n aus type is formed, which is flatter than the base area 3 a, and is on a predetermined area of the surface area of the silicon carbide base area 3 b of the p⁻ type, a source region 4 b of the n⁺ type is formed, which is flatter than the base region 3 b.

Here, a portion of each of the base regions 3 a, 3 b made thicker. That is, deep base areas 30 a, 30 b are formed. The impurity concentration of the thickened regions of the base regions 3 a, 3 b (the tie fen base portions 30 a, 30 b) is higher than the impurity concentration at the thinner areas. Likewise, the deep base regions 30 a, 30 b are formed under the source regions 4 a, 4 b.

Furthermore, an SiC layer (surface channel epi layer) 5 of the n⁻ type on the surface area of the silicon carbide epoxy layer 2 of the n⁻ type and the surface regions of the silicon carbide base regions 3 a, 3 b of the p⁻ type between the source region 4 a of the n⁺ -Types and the source region 4 b of the n⁺-type. The SiC layer (surface channel epi layer) 5 of the n⁻ type is formed by epitaxial growth and serves as the channel formation layer on the device surface during the operation of the device.

Here, the silicon carbide, which forms the semiconductor substrate 1 , the silicon carbide epoxy layer 2 of the n⁻ type, the base regions 3 a, 3 b and the source regions 4 a, 4 b, 6H-SiC, while that of the surface channel epoxy layer 5 is 3C-SiC .

Likewise, depressions 6 a, 6 b are formed on the surface areas of the silicon carbide base regions 3 a, 3 b of the p⁻ type and the source regions 4 a, 4 b of the n⁻ type.

A gate insulation film (silicon oxide film) 7 is formed on the top of the surface channel epi layer 5 and the source regions 4 a, 4 b of the n⁺ type. A polysilicon gate electrode 8 is also formed on the gate insulation film 7 , this polysilicon gate electrode 8 being covered with an insulation film 9 . A source electrode 10 is formed over it and the source electrode 10 touches the source regions 4 a, 4 b of the n Typs-type, and the silicon carbide base regions 3 a, 3 b of the p⁻-type. A drain electrode layer 11 is also formed on the rear side 1 b of the silicon carbide semiconductor substrate 1 of the n⁺ type.

A manufacturing method for this planar type power MOSFET will now be explained with reference to FIGS . 13 to 20.

First, as shown in FIG. 13, an n-type 6H-SiC substrate 1 , that is, a n⁺-type silicon carbide semiconductor substrate 1 is prepared, and an n⁻-type silicon carbide epoxy layer 2 becomes epitaxially through grown to a thickness of 5 to 10 microns on the main surface 1 a of the substrate 1 . In this embodiment of the present invention, the silicon carbide layer 2 of the n⁻ type receives the same crystals as the underlying substrate 1 for a 6H-SiC layer of the n type.

Also, as shown in Fig. 14, an insulation film 20 is placed on a predetermined area of the silicon carbide epoxy layer 2 of the n⁻ type, and this is used as the mask for ion implantation of group IIIA impurities, that is, B +, Al + or Ga + used to form the silicon carbide base regions 3 a, 3 b of the p⁻ type.

After removing the insulation film 20 , as shown in FIG. 15, a surface channel epi layer of the n⁻ type is epitaxially grown on the silicon carbide epi layer 2 of the n⁻ type using an LPCVD device. SiH ₄ , C ₃ H ₈ and H _{2 are used} as the source gases as the growth conditions, and the SiH ₄ / C ₃ H ₈ flow ratio is [0.5]. The growth temperature is 1300 ° C. This method results in a 3C-SiC surface channel epi layer 5 . That is, a 3C-SiC surface channel epoxy layer 5 is made by lowering the temperature to 1200 to 1300 ° C compared to the conventional 1600 ° C and by forming the film with a higher Si / C ratio to increase the two-dimensional nucleation improve, instead of a layer achieved by layer growth. In other words, a 3C-SiC {111} surface is formed on the {0001} surface of the 6H-SiC.

Next, as shown in Fig. 16, Group IIIA impurities, i.e., B +, Al +, or Ga +, are ion-implanted with a mask (an insulating film, etc.) 31 ions disposed over the surface channel epi layer 5 , to form deep base areas 30 a, 30 b.

Also, as shown in Fig. 17, the aforementioned mask 31 is used for implanting N + to form source regions 4 a, 4 b of the n⁺ type.

After removing the mask, as shown in Fig. 18, the photoresist method is used to arrange an insulation film 22 on a predetermined area, the surface channel epi layer 5 , and this is used as a mask for etching portions of the source areas 4 a, 4 b of the n⁺ type and the silicon carbide base regions 3 a, 3 b of the p⁻ type used by RIE to form depressions 6 a, 6 b.

After subsequent removal of the insulation film 22 , as shown in FIG. 19, a gate insulation film (gate oxide film) 7 is formed on the substrate by wet oxidation. A polysilicon gate electrode 8 is then deposited on the gate insulation film 7 by LPCVD.

Next, as shown in FIG. 20, after removing the unwanted portions of the gate insulation film 7, an insulation film 9 is formed to cover the poly silicon gate electrode 8 . Also, as shown in Fig. 12, the source electrode 10 and the drain electrode 11 are generated by metal sputtering at room temperature. Annealing is then carried out at 1000 ° C after film formation.

This completes the power MOSFET of a plana ren type.

If the power MOSFET of a planar type is switched off, it is due to a depletion due to the difference in the work functions of the polysilicon gate electrode 8 and the surface channel layer 5 and the PN junction between the silicon carbide base regions 3 a, 3 b of the p⁻ type and the surface channel epi layer 5 in a pinch-off state.

On the other hand, it is switched on by applying a voltage to the polysilicon gate electrode 8 in an enrichment mode in which the charge carriers are enriched on the surface channel epi layer 5 . In the switched-on state, electrons flow from the source regions 4 a, 4 b of the n⁺-type through the surface channel epi layer 5 and from the surface channel epi layer 5 to the silicon carbide epi layer 2 of the n⁻-type and the electrons flow after reaching the silicon carbide epi layer 2 (des Drift region) of the n⁻-type vertically to the silicon carbide semiconductor substrate 1 of the n Typs-type (drain of the n⁺-type).

According to this embodiment of the present invention, since 3C-SiC, which has high mobility, is used as a surface channel epoxy layer 5 separate from the substrate side SiC, it is possible to greatly improve the transistor properties (on-resistance) of the FET, and particularly, due to this reduction in forward resistance, greatly reduce loss when used as a module.

In other words, when a surface channel epi layer 5 is grown with the same crystal system / polymorph on the substrate side SiC (for example, when a 6H-SiC epitaxial layer is formed on the 6H-SiC substrate and a 4H-SiC epitaxial layer on the 4H-SiC substrate), 4H-SiC is generally used, which gives preferred characteristics, but with a poor quality 4H-SiC substrate, the quality of the epitaxial layer is also deteriorated. In contrast, using a surface channel layer 5 with a different crystal system / polymorph to the substrate side, it is possible to achieve an SiC semiconductor substrate with good characteristics and high reliability.

The combination of a different crystal system / polymorph of the SiC substrates ( 1 , 2 , 3 , 3 a, 3 b, 4 a, 4 b) and the surface channel epi layer 5 can be a 6H-SiC substrate and a 3C-SiC epitaxial layer 5 or other different combinations, for example a 6H-SiC substrate and a 4H-SiC epitaxial layer 5 or a 4H-SiC substrate and a 3C-SiC epitaxial layer 5 .

Since deep base regions 30 a, 30 b are formed on the base regions 3 a, 3 b to thicken a portion of the base regions 3 a, 3 b, the thickness on the silicon carbide epoxy layer 2 of the n⁻ type is also below the depths Base regions 30 a, 30 b lower (the distance between the silicon carbide semiconductor substrate 1 of the n⁺ type and the deep base regions 30 a, 30 b is shortened), which therefore promotes a breakthrough. Furthermore, since the impurity concentration at the deep base regions 30 a, 30 b is higher than the impurity concentration at the thinner regions, a breakthrough is still encouraged. Since the deep base regions 30 a, 30 b are formed from the source regions 4 a, 4 b, it is also possible to make common use of the mask 31 , as shown in FIGS. 16 and 17.

Therefore, this embodiment of the present invention has the following features.

• (a) The silicon carbide that forms the semiconductor substrate 1 , the silicon carbide epoxy layer 2 of the n⁻ type, the base regions 3 a, 3 b and the source regions 4 a, 4 b is 6H, while the silicon carbide of the surface channel layer 5 is 3C. That is, the silicon carbide that forms the semiconductor substrate 1 , the silicon carbide epoxy layer 2 of the n⁻-type, the base regions 3 a, 3 b and the source regions 4 a, 4 b is hexagonal, while the silicon carbide of the surface channel layer 5 is cubic . In other words, the silicon carbide that forms the semiconductor substrate 1 , the silicon carbide epoxy layer 2 of the n⁻ type, the base regions 3 a, 3 b and the source regions 4 a, 4 b, and the silicon carbide of the surface channel epoxy layer 5 have a different Crystal system / polymorph. Therefore, by using a surface channel epi layer 5 with a different crystal system / polymorphic to that of the substrate side, it is possible to achieve a SiC semiconductor device with good characteristics and high reliability.
• (b) Since deep base regions 30 a, 30 b are provided as thickened sections of the base regions 3 a, 3 b, a breakthrough is facilitated.
• (c) Since the impurity concentration of the deep base areas 30 a, 30 b is higher than the impurity concentration of the thinner areas, a breakthrough is further facilitated.
• (d) Since the deep base regions 30 a, 30 b (thickened regions of the base regions) are formed under the source regions 4 a, 4 b, the mask 31 can be used both as the mask for forming a deep base region and the mask during manufacture a Sourcebe be Reich used to form, as it can be, without leading to increased manufacturing costs, manufactured in FIGS. 16 and 17 is shown, and therefore, the MOSFET of a planar type in Fig. 12.

That is, as shown in Fig. 13, a silicon carbide layer 2 of the n⁻ type is formed on the main surface 1 a of the semiconductor substrate 1 , and, as shown in Fig. 14, base regions 3 a, 3 b a predetermined depth are formed on predetermined areas of the surface area of the silicon carbide epoxy layer 2 of the n⁻ type. Also, as shown in FIG. 15, a surface channel epi layer 5 is arranged on the silicon carbide layer 2 of the n⁻ type, as shown in FIG. 16, deep base regions 30 a, 30 b, which are deeper than that Base areas 3 a, 3 b are formed on predetermined areas of the base areas 3 a, 3 b, and, as shown in FIG. 17, the mask 31 is used to form a deep base area to source areas 4 a, 4 b to form predetermined areas of the surface areas of the base areas 3 a, 3 b to a shallower depth than the base areas 3 a, 3 b. Then, a gate electrode 8 is formed on the surface of the surface channel epoxy layer 5 over a gate electrode film 7 , and a source electrode 10 is formed in contact with the base regions 3 a, 3 b and source regions 4 a, 4 b.

Therefore, the mask 31 is used to form a deep base region to form the source regions 4 a, 4 b, so that they can be used as both masks.

A third off is described below management example of the present invention.

The third embodiment of the present invention is now emphasizing its differences to the second embodiment of the present invention explained.

Fig. 21 shows a cross-sectional view of a planar vertical power MOSFET having an n-channel according to this embodiment of the present invention.

In Fig. 21, the thickened areas of the base areas 3 a, 3 b, that is, the deep base areas 30 c, 30 d are formed at locations that do not overlap the source areas 4 a, 4 b. This helps prevent the device from being destroyed.

The reason for this is now explained.

A breakdown occurs at the deep base regions 30 c, 30 d and a breakdown current flows between the source electrode 10 and the drain electrode 11 . At such a time, if there is a source region in the path of the breakdown current flow, a voltage drop occurs in the source region, the PN junction with the base regions 3 a, 3 b of the p⁻ type is forward biased and therefore the NPN begins -Transistor, which consists of the silicon carbide epi layer 2 of the n⁻ type, the base region 3 a ( 3 b) and the source region 4 a ( 4 b) to work, which generates a large current and heats the element, which be Reliability may be undesirable. Consequently, this state can be avoided by removing the source regions 4 a, 4 b from the main path of a breakdown current flow, as it is according to this exemplary embodiment of the invention.

Thus, this embodiment has the present Invention the following feature.

Since the thick portions of the base regions 3 a, 3 (the deep base portions 30, 30 d c) are provided at locations b, which do not overlap the source regions 4 a, 4 b, it is possible to prevent destruction.

A fourth off is described below management example of the present invention.

The fourth embodiment of the present invention is now emphasizing its differences to the first embodiment of the present invention explained.

Fig. 22 is a cross-sectional view of a planar MOSFET having an n-channel (vertical power MOSFET) accelerator as this embodiment of the present invention.

In Fig. 22, a SiC layer 40 expands the n⁻-type on the surface of the Siliziumkarbidepischicht 2 of the n⁻-type. That is, the SiC layer 40 of the n⁻-type is arranged such that it connects the source regions 4 a, 4 b on the surface regions of the base regions 3 a, 3 b and the silicon carbide layer 2 of the n⁻-type. This nC-type SiC layer 40 is formed by epitaxial growth and the crystals of the epitaxial film are 3C.

Also, the n⁻-type SiC layer 40 serves as the channel formation layer on the device surface during the operation of the device. The SiC layer 40 of the n⁻ type is referred to hereinafter as the surface channel layer.

Therefore, the surface channel epi layer 40 overlaps with a portion S of each of the source regions 4 a, 4 b. More specifically, the surface channel epi layer 40 does not cover all of the source regions 4 a, 4 b.

The rest of the structure is the same as in Fig. 1 and designated by the same reference numerals, and its explanation is omitted.

A manufacturing method for this planar type power MOSFET will be explained with reference to FIGS. 23 to 27.

First, as shown in FIG. 23, a 6H-SiC substrate 1 of the n⁻-type, that is, a silicon carbide semiconductor substrate 1 of the n⁺-type, is prepared, and a silicon carbide epoxy layer 2 of the n⁻- Type grown up to a thickness of 5 to 10 microns epitaxially on the main surface 1 a of the substrate 1 . In this exemplary embodiment of the present invention, the silicon carbide epoxy layer 2 of the n⁻ type receives the same crystals as the underlying substrate 1 for a 6H-SiC layer of the n⁻ type.

Also, as shown in FIG. 24, an insulation film 20 is placed on a predetermined area of the n⁻-type silicon carbide layer 2 and this is used as a mask for ion implantation of group IIIA impurities, that is, B +, Al + or Ga +, used to form the silicon carbide base regions 3 a, 3 b of the p⁻ type.

After removing the insulation film 20 , as shown in Fig. 25, an insulation film 41 is placed on a predetermined area of the n⁻-type silicon carbide layer 2 , and this is used as a mask for ion implantation of N + around the source regions Form 4 a, 4 b of the n⁺ type.

After removing the insulation film 41 , as shown in FIG. 26, a surface channel epi layer 40 of the n⁻ type is epitaxially grown on the silicon carbide layer 2 of the n⁻ type. As the growth conditions, who uses SiH ₄ , C ₃ H ₈ and H ₂ as the source gases, and the Si / C ratio is [0.5]. The growth temperature is 1200 ° C. This process results in a 3C-SiC surface channel epi layer 40 .

Next, as shown in Fig. 27, the unnecessary surface channel epi layer 40 is removed. That is, a mask material M of a photoresist material, an SiO ₂ film, an Si ₃ N ₄ film or the like is formed, and the unnecessary surface channel epi layer 40 is removed by dry etching (for example, RIE). If the mask material M is a Si ₃ N ₄ film, the surface channel epi layer 40 can be thermally oxidized to convert it to an oxide film for removal. If the surface channel epi layer 40 is removed by dry etching, the surfaces of the source regions 4 a, 4 b of the n⁺-type and the silicon carbide base regions 3 a, 3 b of the p⁻-type, which are exposed by the etching, are applied by dry etching roughened, but the roughened surfaces can be removed by oxidation.

Then, as shown in FIG. 22, a gate insulation film (gate oxide film) 7 is formed. Then, a polysilicon gate electrode 8 is deposited on the gate insulation film 7 by LPCVD. An insulation film 9 is then formed so that it covers the gate insulation film 7 be. Likewise, a source electrode 10 and a drain electrode 11 are generated by metal sputtering at room temperature. Then, annealing is carried out at 1000 ° C after film formation.

This completes the power MOSFET of a plana  ren type.

When the power MOSFET of a planar type is switched off, it is due to a depletion due to the difference in the work functions of the polysilicon gate electrode 8 and the surface channel layer 40 and the PN junction between the silicon carbide base regions 3 a, 3 b of the p⁻ type and the surface channel epi layer 40 in a pinch-off state.

On the other hand, it is switched on by applying a voltage to the polysilicon gate electrode 8 in the enrichment mode in which the charge carriers accumulate on the surface channel epi layer 40 . In the switched-on state, electrons flow from the source regions 4 a, 4 b of the n⁺ type through the surface channel epi layer 40 and from the surface channel epi layer 40 to the silicon carbide epi layer 2 of the n⁻ type and the electrons flow after reaching the silicon carbide layer 2 ( of the drift region) of the n⁻-type vertically to the silicon carbide semiconductor substrate 1 of the n⁺-type.

Here, the contact point S between the source areas 4 a, 4 b and the surface channel epi layer 40 forms the contact area, so that a larger contact area is achieved with the surface channel epi layer 40 compared to the structure in FIG. 1.

Therefore, this embodiment has the present features.

• (a) Since the surface of channel epilayer 40 has a structure that a portion of each of the source regions 4 a, 4 b overlaps, it is possible to Kontaktbe range from the source regions 4 a, 4 b to the Oberflächenka dimensional pisch maybe expand 40th
• (b) As the manufacturing method in this case, as shown in FIG. 23, an n⁻-type silicon carbide layer 2 is formed on the main surface of the semiconductor substrate 1 , as shown in FIG. 24, Base regions 3 a, 3 b of a predetermined depth are formed on predetermined regions of the surface region of the silicon carbide epoxy layer 2 of the n⁻ type and, as shown in FIG. 25, the source regions 4 a, 4 b of a shallower depth than the base regions 3 a, 3 b formed in front of certain areas of the surface areas of the base areas 3 a, 3 b. Likewise, the surface channel epi-layer will be as shown in Fig. 26, epitaxially grown on the Siliziumkarbidepischicht 2 of the n⁻-Tys 40 and is, as shown in Fig. 27, the unnecessary upper surface channel-epi layer 40 from the Oberflächenkanalepi layer 40 is removed, the rich on the sections of the Sourcebe 4 a, 4 b remains. In addition, as shown in FIG. 22, the gate electrode 8 is formed on the surface of the surface channel epi layer 40 with the gate insulation film 7 therebetween, while the source electrode 10 is in contact with the base regions 3 a, 3 b and the source regions 4 a , 4 b is formed. The semiconductor device in point (a) is therefore made in this way.

This embodiment of the present invention can be applied in the following way.

As shown in Fig. 28, a portion of each of the base regions 3 a, 3 b thickened. That is, deep base areas 50 a, 50 b are formed. The impurity concentration at the thickened areas of the base areas 3 a, 3 b (the deep base areas 50 a, 50 b) is higher than the impurity concentration at the thinner areas. Likewise, the deep base regions 50 a, 50 b are formed under the source regions 4 a, 4 b.

The depressions 6 a, 6 b are also formed in the source regions 4 a, 4 b, which touch the source electrode 10 in the same way as in the first and second exemplary embodiments of the present invention. This increases the contact area with the electrode by the degree of the recesses 6 a, 6 b.

Alternatively, as shown in FIG. 29, deep base regions 50 c and 50 d are formed as regions of greater thickness in the base regions 3 a, 3 b and these deep base regions 50 c, 50 d are formed at locations which are not included overlap the source regions 4 a, 4 b. This helps prevent their destruction.

Likewise, the crystal system / polymorph of silicon carbide, which forms the semiconductor substrate 1 , the silicon carbide epi layer 2 of the n⁻ type, the base regions 3 a, 3 b and the source regions 4 a, 4 b, is the same as the crystal system / polymorph of the silicon carbide may be the surface channel epi-layer 40 .

A fifth off is described below management example of the present invention.

Fig. 31 shows a cross-sectional view of a normally-off planar vertical power MOSFET with an n-channel according to this embodiment of the present invention. This device is suitable for use on inverters or AC voltage generators for vehicles.

The structure of the vertical power MOSFET will now be explained with reference to FIG. 31. However, since the vertical power MOSFET of this embodiment of the present invention has generally the same structure as the MOSFET shown in FIG. 1, only the different aspects will be explained. The aspects of the vertical power MOSFET of this embodiment of the present invention, which are the same as those of the MOSFET shown in FIG. 1, are denoted by the same reference numerals.

In the MOSFET shown in FIG. 1, the surface channel layer 5 is made entirely of a layer of an n + type, but in the vertical power MOSFET of this embodiment of the present invention, the channel region portion 5 a of the surface channel layer is made a layer of an n⁻-type, while the other regions 5 b are formed as the channel region from a layer of an n⁺-type.

That is, the surface channel layer 5 is formed such that the source regions 4 a, 4 b and the silicon carbide layer 2 of the n⁻ type on the surface areas of the silicon carbide base regions 3 a, 3 b of the p⁻ type and the surface region of the silicon carbide layer 2 of the n⁻ type connects, but the surface regions of the silicon carbide base regions 3 a, 3 b of the p⁻ type consist of layers of the n⁻ type, while the surface region of the silicon carbide epoxy layer 2 of the n⁻ type consists of a layer of an n⁺ -Type exists.

Regarding the inner enrichment _drift resistance R _{acc-drift of} the surface channel layer 5 , since the other regions 5 b as the channel region section 5 a of the surface channel layer 5 are formed from a layer of the n⁺-type, the internal resistance of these sections 5 b is smaller than if they are formed from a layer of the n⁻ type. Consequently, the sum of the _on resistance R _{on is} smaller, which allows the _on resistance R _{on to be} reduced.

The _on -resistance R _{on of} a planar vertical power MOSFET is due to the contact resistance R _s-cont between the source electrode and the source regions of the n⁺-type, the inner drift resistance R _{source of} the _source regions is the n⁺-type, the enrichment _channel resistance R _channel in the Channel region formed in the surface channel layer, the inner enhancement _drift resistance R _{acc-drift of} the surface channel layer, the JFET resistor R _{JFET of} the JFET region, the inner _drift resistance R _drift of the n⁻-type silicon carbide channel layer, the inner resistance R _{sub of} the silicon carbide semiconductor substrate of the n⁺ type and the contact resistance R _d-cont between the silicon carbide semiconductor substrate of the n⁺ type and the drain electrode are determined. The sum of the previous components is the forward resistance. That is, it is represented by the following equation (5).

R _on = R _s-cont + R _source + R _channel + R _acc-drift + R _JFET + R _drift + R _sub + R _d-cont (5)

FIG. 32 shows a comparison of the drain current / drain voltage characteristics of the vertical power MOSFET of this embodiment of the present invention shown in FIG. 31 and one such as that shown in FIG. 1 in which the others Areas as the channel area of the surface channel layer 5 are also made of a layer of the n⁻ type. This graph shows the change in drain current when the gate application voltage is changed.

As shown in FIG. 32, when the regions 5 b other than the channel region of the surface channel layer 5 are made of an n + type layer, the drain current is larger than when the regions 5 b other than the channel region are made of a layer of the n⁻ type exist. This is due to the reduced _on resistance R _{on of} the vertical power MOSFET. Therefore, it is possible by manufacturing the other regions 5 b than the channel region of the surface channel layer 5 with a layer of the n⁺ type to further reduce the forward resistance R _{on of} the vertical power MOSFET.

Deep base layers 30 a, 30 b are likewise formed, which are thickened regions of the base regions 3 a, 3 b. The deep base layers 30 a, 30 b are formed on areas that do not overlap with the source area of the n⁺ type, and the thickened areas on which the deep base areas 30 a, 30 b in the silicon carbide base areas 3 a, 3 b of the p⁻-type are formed, have a higher impurity concentration than the thinner areas, on which the deep base layers 30 a, 30 b are not formed.

With these deep base layers 30 a, 30 b, the thickness of the silicon carbide epoxy layer 2 of the n⁻ type under the deep base layers 30 a, 30 b is reduced (the distance between the silicon carbide semiconductor substrate 1 of the n⁺ type and the deep base layer 30 a, 30 b is shortened), which allows an increase in the field intensity and facilitates an avalanche breakdown.

Since the deep base layers 30 a, 30 b are formed on areas that do not overlap with the source area of the n⁺ type, the following state results.

An avalanche breakdown occurs at the deep base regions 30 a, 30 b and a breakdown current therefore flows between the source electrode 10 and the drain electrode 11 . At such a time, when the path of a breakthrough current flow (current flow of positive holes) occurs, the base regions 3 a, 3 b of the p⁻ type, that between the source regions 4 a, 4 b and the drift region 2 of the n⁻ type on both sides is included, a voltage drop in the source areas 3 a, 3 b of the p Typs type, the PN junction between the base areas 3 a, 3 b of the p⁻ type and the source areas 4 a, 4 b biased forward and therefore the parasitic NPN transistor, which is formed from the silicon carbide epi layer 2 of the n⁻ type, the base regions 3 a, 3 b and the source regions 4 a, 4 b, to work, which generates a large current . The element is therefore heated, which may be undesirable in terms of reliability. Consequently, this problem can be avoided because the deep base regions 30 a, 30 b are formed on regions that do not overlap with the source region of the n⁺ type.

A manufacturing method for the vertical power MOSFET shown in FIG. 31 will now be explained with reference to FIGS . 33 to 41.

The description of the step shown in Fig. 33 follows.

First, a 4H, 6H or 3C-SiC substrate 1 , that is, a silicon carbide semiconductor substrate 1 of the n⁺ type is prepared. Here, the thickness 1 of the n⁺-type amounts of the silicon carbide semiconductor substrate 400 micrometers, and is the main surface 1a is the (0001) Si face, the (0001) C surface (1120) -a-surface or the (1100) -Pris surface. A silicon carbide layer 2 of the n⁻ type is epitaxially grown to a thickness of 5 to 10 micrometers on the main surface 1 a of the substrate 1 . In this embodiment of the present invention, the silicon carbide epoxy layer 2 of the n⁻ type holds the same crystals as the underlying substrate 1 for a 2H, 4H, 6H, 15R or 3C SiC layer.

The description of the step shown in Fig. 34 follows.

An insulation film 20 is placed on a predetermined area of the silicon carbide epoxy layer 2 of the n⁻ type, and this is used as the mask for ion implantation of group IIIA impurities, that is, B +, Al + or Ga +, around the silicon carbide base regions 3 a, 3 to train b of the p⁻ type. The ion implantation conditions are a temperature of 700 ° C and a dose of 1E14 cm ^-2 .

The description of the step shown in Fig. 35 follows.

After removing the insulation film 20 , an ion implantation of N + is effected from the top of the substrate 1 in order to form a surface channel layer 5 on the surface area of the silicon carbide epoxy layer 2 of the n⁻ type and the surface areas (surface layer sections) of the silicon carbide base regions 3 a, 3 b of the p ⁻-Type. The ion implantation conditions are a temperature of 700 ° C and a dose of 1E12 cm ^-2 . Therefore, the surface channel layer 5 is compensated for on the surface regions of the base regions 3 a, 3 b of the p⁻ type, which is formed there as a layer of the n⁻ type with a low impurity concentration of the n type, and is on the surface region of the Silicon carbide layer 2 of the n⁻-type formed as a layer of the n⁺-type with a high impurity concentration of the n-type.

In this embodiment of the present invention, the surface channel is fabricated with an ion implantation in silicon carbide, since if the fabrication is performed using silicon, it becomes difficult to measure the degree of thermal diffusion of the impurities in the Ob 11955 00070 552 001000280000000200012000285911184400040 0002019809554 00004 11836 surface channel layer 5 to control, which complicates efforts to manufacture a normally-off type MOSFET with the same structure as that previously described be. Accordingly, using SiC as in this embodiment of the present invention, it is possible to manufacture a vertical power MOSFET with greater accuracy than using silicon.

In addition, in order to obtain a normally-off type vertical power MOSFET, it is necessary to adjust the thickness of the surface channel layer 5 so that it meets the condition of equation (5) mentioned before; however, since V _{built is} low when silicon is used, it becomes necessary to form the surface channel layer 5 with a low thickness and a low impurity concentration, which makes it difficult to control the degree of dispersion of the impurity ions, and this makes it very difficult Manufacture. Furthermore, when SiC is used, V _{built is} approximately three times higher than that of silicon, which allows formation of a thick layer of an n⁻ type and a high impurity concentration; and therefore it becomes easier to manufacture an enrichment type normally-off MOSFET.

The description of the step shown in Fig. 36 follows.

An insulation film 21 is placed on a predetermined area of the surface channel layer 5 , and this is used as the mask for ion implantation of N + to form the source regions 4 a, 4 b of the n + type. The ion implantation conditions are a temperature of 700 ° C and a dose of 1E15 cm ^-2 .

The description of the step shown in Fig. 37 follows.

After removal of the insulating film 21, the photoresist process is used to arrange one insulating film 22 on a predetermined area of the surface channel layer 5, and this is used as a mask to partially etch removal of the surface channel layer 5 on the Silizi umkarbidbasisbereichen 3 a, 3 b of the p⁻-type used by RIE.

The description of the step shown in Fig. 38 follows.

Likewise, the insulation film 22 is used as a mask for ion implantation of B + to form deep base layers 30 a, 30 b. This produced thicker areas in the base regions 3 a, 3 b. The deep base layers 30 a, 30 b are formed on areas that do not overlap with the source areas 4 a, 4 b of the n⁺-type and the ver thick areas where the deep base layers 30 a, 30 b in the silicon carbide base areas 3 a , 3 b of the p⁻ type are formed, have a higher impurity concentration than the thinner areas on which the deep base layers 30 a, 30 b are not formed.

The description of the step shown in Fig. 39 follows.

After removing the insulation film 22 , a gate insulation film (gate oxide film) 7 is formed on the substrate by wet oxidation. The atmosphere temperature is 1080 ° C.

Then, a polysilicon gate electrode 8 is piled on the gate insulation film 7 by LPCVD. The film training temperature is 600 ° C.

The description of the step shown in Fig. 40 follows.

Next, after removing the undesired portions of the gate insulation film 7, an insulation film 9 is formed so that it covers the gate insulation film 7 . More specifically, the film formation temperature is 425 ° C and an annealing is carried out at 1000 ° C after the film formation.

The description of the step shown in Fig. 41 follows.

Likewise, a source electrode 10 and a drain electrode 11 are generated by metal sputtering at room temperature. Then, an annealing is carried out at 1000 ° C after the film formation.

According to this exemplary embodiment of the present invention, when the power device is switched off, it is due to a depletion due to the difference in the work functions of the polysilicon gate electrode 8 and the surface channel layer 5 a, 5 b and the PN junction between the silicon carbide base regions 3 a, 3 b of the p⁻ type and the surface channel layer 5 a, 5 b in a lacing condition. On the other hand, it is turned on cherungsbetriebsart by applying a voltage to the polysilicon gate electrode 8 in a Anrei, in which the La on the surface of channel layer 5 a angerei Chern makers. In the switched-on state, the electrons flow from the source regions 4 a, 4 b of the n⁺ type through the surface channel layer 5 a of the n⁻ type and from the surface channel layer Sb of the n⁺ type to the silicon carbide layer 2 of the n ⁻-Type and the electrons flow to He reach the silicon carbide epoxy layer 2 of the n⁻-type (drift region) vertically to the silicon carbide semiconductor substrate 1 of the n⁺-type.

Likewise, are as shown in Fig. 31, the Siliziumkarbidbasisbereiche 3 a, 3 b of the p⁻-type in Kon clock to the source electrode 10 and are therefore connected to ground ge sets. Consequently, the built-in voltage V _built at the PN junction between the surface channel layer 5 and the silicon carbide base regions 3 a, 3 b of the p⁻-type can be used in order to bring the surface channel layer 5 to a pinch. For example, if the silicon carbide base regions 3 a, 3 b of the p⁻ type are not connected to ground and are in a floating state, the depleted layer cannot use the built-in voltage V _built of the silicon carbide base regions 3 a, 3 b of the p⁻-type, and therefore the contact between the silicon carbide base regions 3 a, 3 b of the p⁻-type and the source electrode 10 can be regarded as an effective structure for bringing the surface channel layer 5 to a pinch-off state. According to this embodiment example of the present invention, the silicon carbide base regions 3 a, 3 b of the p⁻-type are formed with a low impurity concentration, but the built-in voltage V _{built can} also be used with a high impurity concentration.

This completes the vertical power MOSFET shown in FIG. 31.

This embodiment of the present invention has the following characteristics.

By establishing the impurity concentration of the Be realm of the surface channel layer, which is on the upper area of the epitaxial layer is that it is higher than that of the epitaxial layer, it is possible to oppose other areas of the surface channel layer than the channel area (enrichment drift resistance of the channel layer), which reduces the forward resistance of the MOSFET reduced. This allows that for the MOSFET rather lower forward resistance is achieved.

A sixth will now be described Embodiment of the present invention.

In the previous embodiment of the present invention, the surface channel layer 5 is formed by direct ion implantation into the surface region of the silicon carbide epoxy layer 2 of the n⁻ type and the surface areas (surface layers) of the silicon carbide base regions 3 a, 3 b of the p⁻ type but, as shown in Fig. 42, an n⁻-type surface channel layer 5 epitaxially grew over it, whereupon the n-type impurity concentration at the regions other than the channel region of the surface channel layer 5 selectively by a photo step and an ion implantation can be lifted. However, since this method increases the number of manufacturing steps, it is preferable for vertical power MOSFETs to be manufactured by the method of the previous embodiment of the present invention.

A seventh off is described below management example of the present invention.

43, after forming the source regions 4 a, 4 b of the n⁺ type, if a surface channel layer 40 is epitaxially applied to the surfaces of the source regions 4 a, 4 b of the n⁺ type, as shown in FIG. 43 or the silicon carbide base regions 3 a, 3 b of the p⁻ type and the silicon carbide epoxy layer 2 of the n⁻ type are grown, the regions other than the channel region are formed as a layer of the n⁺ type. However, in this case as well, since the number of manufacturing steps must be increased by an epitaxial growth of the surface channel layer followed by ion implantation, as in the case shown in FIG. 42, the method according to the previous embodiment is present invention more effective.

Furthermore, in the previous embodiment len the present invention the application to a ver tical MOSFET with an n-channel has been described. The Swap p-type and n-type with each other in each Embodiment of the present invention, that is,  a vertical MOSFET with a P-channel does the same Effect.

As described above, a half created conductor device that a semiconductor substrate, the silicon carbide of a first conductivity type has a silicon carbide epitaxial layer of the first guide ability type, a first semiconductor region based on the Semiconductor substrate is formed and, silicon carbide one has a second conductivity type, a second semi-lead ter area trained on the first semiconductor area det, silicon carbide of the first conductivity type points and through the first semiconductor region of the half conductor substrate of the first conductivity type is separated, a third semiconductor region, which is on the semiconductor area is richly formed with the semiconductor substrate and is connected to the second semiconductor region, the silicon carbide of the first conductivity type and a high has higher resistance than the semiconductor substrate, and has a gate electrode on the third semiconductor ter area is formed over an insulation layer, the third semiconductor region being depleted if none Voltage is applied to the gate electrode, so that the Semiconductor device a normally turned off Has characteristic.

Claims (20)

1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type, which has single crystal silicon carbide and a silicon carbide epitaxial layer of the first conductivity type, which is formed on the main side of the semiconductor substrate;
a first semiconductor region which is formed on the silicon carbide epitaxial layer and has silicon carbide of a second conductivity type;
a second semiconductor region formed on the first semiconductor region, having silicon carbide of the first conductivity type and separated from the silicon carbide epitaxial layer of the first conductivity type by the first semiconductor region;
a third semiconductor region formed on the first semiconductor region, which is connected to the silicon carbide epitaxial layer and the second semiconductor region, which has silicon carbide of the first conductivity type and has a higher resistance than the semiconductor substrate; and
a gate electrode which is formed with an insulation layer located between them on the third semiconductor region, wherein
the third semiconductor region is depleted when no voltage is applied to the gate electrode, so that the semiconductor device has a characteristic that is normally switched off. 2. Semiconductor device according to claim 1, characterized records that the normally switched off character teristics of the third semiconductor area through change side connecting a depletion layer, which is from the gate electrode to the third semiconductor region expands and a depletion layer is achieved which differs from the second semiconductor region in the extends third semiconductor region. 3. A semiconductor device according to claim 1, characterized records that the gate electrode is a polysilicon gate is electrode and the polysilicon gate electrode one Has conductivity type to that of the third Semiconductor region is opposite. 4. A semiconductor device according to claim 1, characterized in that
the first semiconductor region is silicon carbide of the second conductivity type and has a higher resistance than the silicon carbide epitaxial layer or the semiconductor substrate;
the first semiconductor region is a base region that is formed to a predetermined depth on a predetermined region of the silicon carbide epitaxial layer;
the second semiconductor region is a source region which is formed on a predetermined region of the surface layer of the base region and has a shallower depth than the base region;
the third semiconductor region is a surface channel layer which consists of silicon carbide of the first conductivity type, has a higher resistance than the semiconductor substrate and is arranged on the surface of the base region such that it connects the source region and the first semiconductor region, the surface channel layer being depleted when no voltage is applied to the gate electrode to have a characteristic normally off; and
the semiconductor device further includes a gate insulation film formed on the surface channel layer, a gate electrode formed on the gate insulation film, a source electrode formed to contact the base region and the source region, and a drain electrode is formed on the back of the semiconductor substrate. 5. A semiconductor device according to claim 4, characterized indicates that the area of the surface channel layer, which is on the surface of silicon carbide epitaxy layer is arranged, a lower resistance than the silicon carbide epitaxial layer. 6. The semiconductor device according to claim 1, characterized records that the main surface of the silicon carbide semiconductor substrate the (0001) -Si area or the (1120) -a area for a low transition state density at the silicon carbide / insulator junction. 7. The semiconductor device according to claim 4, characterized records that the dopant concentration of the surface channel layer no larger than the dopant con  concentrations of the silicon carbide epitaxial layer and the Base area is. 8. The semiconductor device according to claim 4, characterized records that the gate electrode has a first exit area has potential, the base region a second Has work function potential, the surface ca nal layer a third work function potential points and the first, second and third exit ares beit potentials are set such that the La Lung carrier of the first conductivity type in the upper surface channel layer are depleted. 9. A semiconductor device according to claim 8, characterized records that the first, second and third Aus pedaling potentials are set such that the charge carriers of the first conductivity type in the Surface channel layer are depleted if the Gate electrode with respect to the drain region at zero points tial is located. 10. The semiconductor device according to claim 4, characterized records that the surface channel layer by epitak table growth or ion implantation is. 11. The semiconductor device according to claim 4, characterized records that the surface channel layer by epitak table growth is formed and the crystal system / polymorph of the silicon carbide that the semiconductor substrate, the silicon carbide epitaxial layer, the base area and forms the source area to which the Silicon carbide under the surface channel layer  is different. 12. The semiconductor device according to claim 11, characterized records that the silicon carbide that the semiconductor substrate, the silicon carbide epitaxial layer, the base area and forms the source area, from a hexago system, while the silicon carbide is the upper surface channel layer of a cubic system. 13. The semiconductor device according to claim 4, characterized in that the surface channel layer is formed by epitaxial growth and the silicon carbide, which forms the semiconductor substrate, the silicon carbidepi taxie layer, the base region and the source region, is 6H-SiC, while the silicon carbide of the surface channel layer 3 is C-SiC. 14. The semiconductor device according to claim 4, characterized draws a portion of the base area thicker is made. 15. A semiconductor device according to claim 14, characterized records that the impurity concentration of the thickened th area of the base area higher than the fault steering concentration of the thinner areas is established. 16. The semiconductor device according to claim 14, characterized draws that the thickened area of the base area is formed under the source region. 17. The semiconductor device according to claim 14, characterized  draws that the thickened area of the base area is formed in a place that is not compatible with the Source area overlaps. 18. A semiconductor device according to claim 4, characterized records that the surface channel layer with an Ab intersection of the source area overlaps. 19. A semiconductor device comprising:
a semiconductor substrate composed of silicon carbide of a first conductivity type and a silicon carbidepi taxi layer of the first conductivity type, which is formed on the main side of the semiconductor substrate;
a first semiconductor region formed on the silicon carbide substrate and made of silicon carbide of a second conductivity type;
a second semiconductor region formed on the first semiconductor region and made of silicon carbide of the first conductivity type;
a third semiconductor region formed on the first semiconductor region that connects the silicon carbide epitaxial layer and the second semiconductor region that is made of silicon carbide of the first conductivity type and has a lower dopant concentration than the semiconductor substrate; and
a gate electrode formed over an insulation layer on the third semiconductor region, where the thickness of the third semiconductor region is such a thickness (in the submicron order) that complete depletion occurs when no voltage is applied to the gate electrode. 20. A semiconductor device comprising:
a semiconductor substrate composed of first conductivity type silicon carbide and a first conductivity type silicon carbidepi layer formed on the main surface of the semiconductor substrate;
a first semiconductor region formed on the silicon carbide substrate and made of silicon carbide of a second conductivity type;
a second semiconductor region formed on the first semiconductor region and made of silicon conductivity of the first conductivity type;
a third semiconductor region formed on the first semiconductor region, which is the silicon carbide epitaxial layer and the second semiconductor region, which consists of silicon carbide of the first conductivity type and has a lower dopant concentration than the semiconductor substrate; and
a gate electrode formed over an insulation layer on the third semiconductor region, where at
the impurity concentration of the area of the surface channel layer located on the surface area of the epitaxial layer is higher than that of the remaining area of the surface channel epitaxial layer and the silicon carbide epitaxial layer, thereby reducing the on-resistance.