DE1591215C3 - Phase detector for harmonic square waves with a clock counter in (esp. Hyperbolic) navigation systems - Google Patents

Description

counts, where NF is the frequency of the clock pulses and nF is the frequency of the lowest common harmonic.

2. Phase detector according to claim 1, characterized in that the start-stop logic (16, 17) with the interposition of a further AND circuit (14), an additional release pulse (9) a release pulse generator (8) is supplied.

3. Phase detector according to claim 2, characterized in that for the purpose of averaging A frequency divider (21) is connected upstream of the counter (2) over a number of measuring periods, the number of counting pulses allowed through with a correspondingly extended release pulse (9) divided by the number of measurement periods.

40

The invention relates to a phase detector as specified in the preamble of claim 1.

Such a phase detector is described in DT-AS 16 388. In this phase detector, the two received signals with the frequencies av and bv are first converted into two pulse trains with the repetition frequencies av and bv . These two pulse trains are fed to frequency dividers which emit two pulse trains with the repetition frequency ν. These pulses are fed to a bistable multivibrator that controls a gate circuit. The input of this gate circuit receives further pulses from a pulse generator, the repetition frequency of these pulses being large compared to the frequencies ν . In order to ensure that the output signals of the frequency dividers with the frequency ν are in phase with the fundamental frequency ν of the two signals, additional circuits are provided.

The object of the invention is to provide a simplified phase detector.

This object is achieved with the means specified in the claims.

It is an advantage of this invention that there is always the same relative Phase difference, based on a harmonics common to both signals, is measured independently of when the phase measurement is started. In addition, in the phase detector according to the invention no frequency divider necessary.

The invention is explained in more detail with reference to figures, of which

Fig.l is a block diagram of the phase detector represents according to the invention in

F i g. 2 are voltage curves at the various appropriately labeled points of the circuit illustrated, and

3 shows the circuit of the phase detector again, but with a stage for averaging.

The phase detector according to FIG. 1 contains a ring counter 2 which is connected downstream of the start-stop logic 1 via a clock pulse line 4. In the start-stop logic 1 are input from signal sources 5 and 6 signals that have frequencies m F and mF ; the phase difference of these signals is to be measured. The start-stop logic 1 is also supplied with a release pulse from a pulse generator 8 to enable it; Furthermore, clock pulses of a clock generator 7 of the start-stop logic 1 are input, which serve as a counting frequency. The clock pulses of the frequency NFs'md of a much higher frequency than the frequencies mF and mF; they are in FIG. 2 (F). The ring counter 2 is supplied with a reset pulse from a generator 18, by means of which the ring counter is reset to zero before the next phase measurement begins.

The special embodiment of the start-stop logic known per se works as follows: The release pulse from the pulse generator 8 and the signal from the signal source 5 are fed to the inputs of an AND circuit 14, the output pulse of which is input to one input of a bistable multivibrator 16. The signal from the signal source 6 is fed to the other input of the multivibrator 16. Another AND circuit 17 is provided, the inputs of which are the output signal of the multivibrator 16 and the clock pulses of the clock generator 7 (frequency LF) . The output pulse of the AND circuit 17 is fed to the ring counter 2 via the clock pulse line 4.

The output signals of the signal sources 5 and 6 (see Fig. 1 and 2) have the frequencies / 21F or. mF; they are shown in Figs. 2 (A) and 2 (B), respectively. In the further description it is assumed that the signals are digital in nature, i.e. pulses. The lowest common harmonic is nF. The ring counter 2 is initially brought into its starting position '•' by a reset pulse from the generator 18. After the release pulse (pulse generator 8), which is shown in FIG. 2 (C) is shown at 9, the AND circuit 14 is enabled; Then when the next pulse occurs with the leading edge going in the positive direction - that is the signal of frequency n \ F - the AND circuit 14 is activated, and this generates a signal "1" at its output, which in turn causes the multivibrator 16 to output a signal "1" on its output line 20 as well. This signal "1" is the beginning of the in FIG. 2 (E) illustrated gate pulse 12. This releases the AND circuit 17, which now lets through the clock pulses NF generated by the clock generator 7 and enters them into the ring counter. These are shown in FIG. 2 (G). The ring counter 2 counts from zero to Ni-1 and then automatically starts counting again from zero, where TVi = NIn . After receiving the immediately

Following the leading edge 13 of the next pulse, which goes in the positive direction and corresponds to the signal of the frequency mF, the gate pulse on the output line 20 of the multivibrator 16 is ended by switching the multivibrator 16 to the other position through the leading edge 13. As a result, the clock pulses of the clock generator 7 can no longer pass the AND circuit 17 and reach the ring counter 2. During the time "ft" that has elapsed between the occurrence of the pulse leading edges 11 and 13, the ring counter 2 has reached a certain level. It should be remembered here that the ring counter 2 only counts up to Λ / ι - 1 and starts counting again at / Vi = Nln. The final reading of the ring counter 2 is proportional to the phase difference (in degrees) with respect to the common harmonic of the two signals with the frequencies n \ F and mF. At this point in time, the release pulse 9 is terminated, whereby the AND circuit 14 is blocked. In this special embodiment, the release pulse 9 must last long enough so that the phase measurement can be ended.

The accuracy of the phase measurement is mainly dependent on the frequency NF of the clock pulses; the higher this frequency, the more precisely the measurement can be carried out.

A simple proof that the final reading of the ring counter 2 is proportional to the phase difference between the two input signals n \ F and mF results from the following consideration, in which according to FIG. 2 the leading edges 11 and 13 of the signals mF and mF, respectively, going in the positive direction may occur at any time. The time interval "i" between these leading edges is then determined by: t = t _t + (XInF) M = i, + T , (1)

where My integer, π - KiM = K2N2 ; where Ki and Kz also mean integers, and for t \:

0 ^ i,

nF

If Λ / 2 is equal to the number of clock pulses that have been counted into the ring counter 2 during the time "f", then the following applies:

N ₂ = I ₁ NF + N ₁ M,

(2)

where N / n = N ₁ .

The second term NiM is - since M is an integer - a multiple of Ni; therefore the final reading / V3 of the ring counter 2 is only dependent on "fi", namely because the ring counter starts counting again after VVi pulses, which - in other words - means that it only counts up to M - 1 and then starts again at zero So:

N ₃ = I ₁ NF, (3)

where 0 ^ N ₃ <N ₁ .

The phase angle θ (nF) is therefore given by

It can be seen from this that the phase difference θ (nF) is proportional to the final reading Λή of the ring counter 2, since the size of / Vi is a constant and does not influence the output, because the ring counter starts counting again from the beginning after the state Ni.

It should also be pointed out that the relative phase difference (or time difference) between the two input signals, based on the common harmonic, is independent of the point where the measurement started because the ring counter 2 starts over at 360 ° of the common harmonic begins to count, ie every time after / Vi - 1 counts of the frequency NF. Therefore, the fraction of the counting cycle that is present in the counter - regardless of how many times the counting cycle is executed - is always proportional to the phase difference between the two signals, based on the common harmonic.

The in F i g. 1, for example, the start-stop logic shown can also be designed differently in a known manner if it can only accomplish the task at hand. The ring counter 2 is also known, and it a more detailed description is therefore unnecessary. Generators for generating Reset pulses.

Nor is it absolutely necessary to have one

Provide release pulse; it just has to be ensured that the ring counter 2 before the beginning of the next Phase measurement is reset to zero. However, if you want to carry out the phase measurement periodically, the pulse generator 8 is required for the release pulse; the release pulse (9, FIG. 2C) must then can also be generated periodically.

In Fig. 3 shows a scheme for forming the mean value between several phase measurements. The components common to FIGS. 3 and 1 are also denoted by the same reference numerals. The signal coming from the start-stop logic and pending at the clock pulse circuit 4 is input to a divider 21 which divides by the number of measurements from which the mean value is to be formed (Na). The output value of the divider 21 is then fed to the ring counter 2, which starts counting from the beginning after / Vi-1 counts. With this circuit, the phase measurements must all be made at the same relative time slots so that M is the same for all measurements. For example, at frequencies of 5 / and 6 /, the measurements can be made every Ns / f seconds. It is also clear that in such a case the release pulse generator must be present in order to generate a release pulse every NsIf seconds (/ is the common factor and / Vs is an integer).

As an example it is assumed that the mean value is to be formed over 5 measurements (Na = 5). As in Fig. 1 / Vi counts of the ring counter 2 correspond to 360 ° of the frequency nF. For the sake of simplicity of the explanations it is assumed that the two signals n \ F and mF have the same frequency (ie ni = m) and that the release pulse has a length which is equal to the time required in which all 5 measurements can be carried out. The reset pulse generated first (pulse generator 18) first sets the divider 21 and the ring counter 2 to zero. Then the release pulse is generated by the pulse generator 8. From the occurrence of the leading edge of the next following first input signal, the clock pulses of the clock generator 7 (frequency LF) are input via the clock pulse line 4 into the divider 21 and then into the ring counter 2. The leading edge of the second input signal ends this process, but the next leading edge of the first input signal causes the clock pulses to be counted in again because the enable pulse is still on. This process is repeated as long as the release pulse lasts; this is made so long that the desired number

of measurements can be carried out. The divider 21 divides by the number of measurements over which is to be averaged; the proportion of each measurement is stored in the ring counter 2, which the summed up the individual values. The final reading of the ring counter 2 is then proportional to the averaged phase difference between the two input signals. There, as assumed in this example, the two input signals have the same frequency, the value M is the same for all measurements and these can be between the leading edges of the signals, thereby simplifying the averaging technique will.

The number M of pulses stored in the ring counter 2, if »f« is constant for the measuring period, amounts to:

JV ₄ = tNFNa / Na = tNF
According to equations (1) and (2) we get:

(5)

JV ₄ = I ₁ NF + MNjn = I ₁ NF + MN ₁ (6)

Since my whole number is and the ring counter 2 starts counting again from zero after every A / i - 1 counts, the expression MNi in equation (6) can be neglected; the final reading of the ring counter 2, in which M pulses have been counted, is accordingly proportional to Θ (nF), as has been shown in equations (3) and (4).

The averaging can of course also be carried out with input signals of different, harmonically related frequencies by slightly modifying the start-stop logic 1 and the release pulse generator 8 is designed so that it generates Na release pulses that are spaced such that the Frequency is a common subharmonic of the two input signals. This ensures that M is constant for all measurements. When averaging with input signals of different frequencies, the reset pulse for the divider 21 and the ring counter 2 is only generated by the first of the Na release pulses. However, such modifications are familiar to the person skilled in the art.

For this purpose 2 sheets of drawings

Claims (1)

Patent claims: 1. Phase detector for navigation systems (in particular hyperbolic navigation systems) for determination the phase difference of two signals present as square waves that are different Are harmonics of a fundamental frequency, using a start-stop logic and a this downstream counter, the start ι ο stop logic after switching a bistable Multivibrator with the beginning of the leading edge of the first signal. Clock pulses from a clock generator through an AND circuit in the counter until the beginning of the leading edge of the second signal the multivibrator is switched back again, characterized in that that the counter (2), that of the start-stop logic (16,17) is downstream, cyclically from zero to a maximum value NF