CN217880301U

CN217880301U - Data backboard

Info

Publication number: CN217880301U
Application number: CN202221835560.5U
Authority: CN
Inventors: 李倩
Original assignee: Hefei Zhuoyi Hengtong Information Security Co Ltd
Current assignee: Hefei Zhuoyi Hengtong Information Security Co Ltd
Priority date: 2022-07-13
Filing date: 2022-07-13
Publication date: 2022-11-22
Anticipated expiration: 2032-07-13

Abstract

The utility model relates to a data backplate. The data backplane includes: the back board is arranged on the back board and used for connecting a first CPCIE connector and a second CPCIE connector which correspond to the CPCIE connectors on the mainboard to transmit PCIE X8 signals, and the back board is arranged on a third CPCIE connector, a fourth CPCIE connector, a fifth CPCIE connector and a sixth CPCIE connector which are used for connecting PCIE equipment to transmit PCIE X4 signals; the first CPCIE connector is in communication connection with the third CPCIE connector and the fourth CPCIE connector, and the second CPCIE connector is in communication connection with the fifth CPCIE connector and the sixth CPCIE connector, so that communication connection between the mainboard and PCIE equipment connected to the backboard is established. The utility model discloses a data backplate can expand server PCIE interface quantity.

Description

Data backboard

Technical Field

The utility model relates to a server integrated circuit board technical field especially relates to a data backplate.

Background

The high-speed signal resource of the current server is few, and the interface demand of the high-speed equipment is much. The common server has a single interface, can only be connected with one high-speed device, is fixed in matching mode, and has a large mainboard area.

Among rack server sizes, 1U server, 2U server, and 4U server are common. U is a unit representing the external size of the server, and is an abbreviation for unit. The size of the server is specified, so that the server can be placed on the rack in a certain size. The dimensions specified for the server are the width (48.26cm =19 inches) and height (a multiple of 4.445 cm) of the server, with the thickness (height)) being based on 4.445 cm. The sizes of these servers are: 1u =4.445 cm, 2u =4.445 × 2=8.89 cm, and 4u =4.445 × 4=17.78 cm. In actual use, 1U or 2U servers are most often used. Because the service provider calculates the cost according to the occupied space of the server, the 1U server is most space-saving and lowest in price, but the expansibility of the 1U server is not as good as that of the 2U server

Meanwhile, the traditional server directly uses the interface from the main board, the number of the interfaces is fixed, the interface form usually adopts a standard PCIE (Peripheral Component Interconnect Express) connector, the collocation is single, the physical space is limited, and the defects that the number of the interfaces cannot be expanded and the like are overcome.

SUMMERY OF THE UTILITY MODEL

Therefore, an object of the utility model is to provide a data backplate, extension server PCIE interface quantity.

In order to achieve the above object, the utility model provides a data backboard, include: the back plate is arranged on the back plate and used for connecting a first CPCIE connector and a second CPCIE connector which correspond to the CPCIE connectors on the mainboard to transmit PCIE X8 signals, and the back plate is arranged on the back plate and used for connecting a third CPCIE connector, a fourth CPCIE connector, a fifth CPCIE connector and a sixth CPCIE connector to transmit PCIE X4 signals; the first CPCIE connector is in communication connection with the third CPCIE connector and the fourth CPCIE connector, and the second CPCIE connector is in communication connection with the fifth CPCIE connector and the sixth CPCIE connector, so that communication connection between the mainboard and the PCIE high-speed equipment connected to the backboard is established.

The I2C switch chip is in communication connection with one of the first CPCIE connector and the second CPCIE connector, and the I2C switch chip is also in communication connection with the third CPCIE connector, the fourth CPCIE connector, the fifth CPCIE connector and the sixth CPCIE connector.

Wherein the data backplane is a data backplane adapted for a 2U server.

Wherein the data backplane is adapted for a server of a marine light platform.

The data backplane comprises a data backplane and at least one PCIE driver chip, wherein the data backplane comprises a plurality of PCIE driver chips; the PCIE Redriver chip is in communication connection with the first CPCIE connector and a third CPCIE connector and/or a fourth CPCIE connector corresponding to the first CPCIE connector, or the PCIE Redriver chip is in communication connection with the second CPCIE connector and a fifth CPCIE connector and/or a sixth CPCIE connector corresponding to the second CPCIE connector

The first CPCIE connector and the second CPCIE connector are arranged on one side face of the back plate, and the third CPCIE connector, the fourth CPCIE connector, the fifth CPCIE connector and the sixth CPCIE connector are arranged on the other side face of the back plate.

The third CPCIE connector and the fourth CPCIE connector are arranged on the other side face of the backboard in an up-and-down opposite mode, and the fifth CPCIE connector and the sixth CPCIE connector are arranged on the other side face of the backboard in an up-and-down opposite mode.

Wherein the first and second CPCIE connectors are connectors of model HMMH1200019A 2B.

The third, fourth, fifth and sixth CPCIE connectors are connectors of model number HMFH120P014 A2A.

The PCIE driver chip is a chip with the model number of ASM 1468.

The I2C switch chip is a chip with the model of PCA 9546.

To sum up, the utility model discloses a data backplate can extension server PCIE interface quantity.

Drawings

The technical solution and other advantages of the present invention will become apparent from the following detailed description of the embodiments of the present invention, which is to be read in connection with the accompanying drawings.

In the drawings, there is shown in the drawings,

fig. 1 is a circuit block diagram of a preferred embodiment of the data backplane of the present invention;

fig. 2 is a schematic diagram of a connector layout according to a preferred embodiment of the data backplane of the present invention;

fig. 3 is a schematic diagram of a connector layout on another side of a preferred embodiment of the data backplane of the present invention.

Detailed Description

Referring to fig. 1, it is a circuit block diagram of a preferred embodiment of the data backplane of the present invention. The utility model discloses a data backplate mainly includes: a backplane (not shown), a first CPCIE connector 1 and a second CPCIE connector 2, which are arranged on the backplane and used for connecting corresponding CPCIE (Compact Peripheral Component Interconnect extended) connectors on the motherboard, to transmit PCIE X8 signals, a third CPCIE connector 3, a fourth CPCIE connector 4, a fifth CPCIE connector 5, and a sixth CPCIE connector 6, which are arranged on the backplane and used for connecting PCIE devices, to transmit PCIE X4 signals, and a first PCIE driver chip 7 and a second PCIE driver chip 8, which are arranged on the backplane; the first CPCIE connector 1 is in communication connection with a first PCIE Redriver chip 7, the first PCIE Redriver chip 7 is in communication connection with a third CPCIE connector 3 and a fourth CPCIE connector 4, the second CPCIE connector 2 is in communication connection with a second PCIE Redriver chip 8, and the second PCIE Redriver chip 8 is in communication connection with a fifth CPCIE connector 5 and a sixth CPCIE connector 6, so that communication connection between the mainboard and the PCIE equipment connected to the backboard is established. By applying the data backplane of the embodiment, the number of PCIE interfaces of the server is expanded, 4 PCIE high-speed devices can be connected at most, and 1 PCIE high-speed device, 2 PCIE high-speed devices or 3 PCIE high-speed devices can be normally used, so that different product forms can be matched, flexibility and changeability are achieved, and peripheral equipment can be configured as required.

In this preferred embodiment, the device further comprises an I2C switch chip 9 disposed on the backplane, wherein the I2C switch chip 9 is communicatively connected to the first CPCIE connector 1, and the I2C switch chip 9 is further communicatively connected to the third CPCIE connector 3, the fourth CPCIE connector 4, the fifth CPCIE connector 5 and the sixth CPCIE connector 6. The I2C switch chip 9 is reserved on the data backboard to identify the address of the I2C bus, so that when the high-speed equipment is externally connected, the address of the I2C equipment conflicts under the condition of using an I2C signal. In other embodiments, the I2C switch chip 9 may be connected to the second CPCIE connector 2 instead of the first CPCIE connector 1, however, the connection method is not limited as long as the final requirement is satisfied.

In other preferred embodiments of the present invention, the data backplane can be a data backplane adapted for a 2U server.

Further, the data backplane may be a data backplane adapted to a server of the marine optical platform, and is suitable for various servers of a domestic marine optical platform, such as a storage server and a GPU server, which want to use a PCIE resource expansion interface. Further, in order to satisfy the different peripheral hardware that can arrange in pairs of servers, the utility model discloses a data backplate can be for the data backplate of the 2U server based on the sea light platform. The motherboard of the sea light platform server generally has 3 sets of PCIE X8 signals, two sets of which are respectively connected to one CPCIE connector, and the remaining set of PCIE X8 signals can be designed to be split into two PCIE X4 signals so as to connect PCIE X4, X2 or X1 devices, or not; for example, a marine optical platform server with a model number of HG3250 is adopted, which generally has 32lane (channel) PCIE signal resources, and a motherboard for actual application of a data backplane is split into 3 PCIE 8 lanes and a plurality of 1 lanes; in the applied motherboard, 2 PCIE 8 lanes are connected to one CPCIE connector, and one PCIE 8lane may be connected to a standard PCIE X16 slot to connect to a PCIE high-speed device. In order to match with different product applications, in the embodiment, a 2U data backplane is specially designed to meet the requirement of high-speed signal quality, and if the high-speed equipment is directly connected with the CPCIE connector of the sea light main board, at most two PCIE high-speed equipment can be connected; if the 2U data backplane switching signal of this embodiment is used, 4 PCIE high-speed devices can be connected at most, and 1, 2 or 3 PCIE high-speed devices can also be used normally, and different product forms can be matched, so that flexibility and changeability are achieved, and peripheral equipment can be configured as required.

In this embodiment, the 2U server of the marine lighting platform generally has two CPCIE connectors supporting PCIE X8 signals on the motherboard, for example, a connector available in the market with a model number of HMFH120P024A2, and the shape of the connector satisfies the physical specification of CPCIE, so that the corresponding motherboard can support PCIE high-speed devices with at most two PCIE X8 signals. In this embodiment, the connectors adapted to the motherboard, the first CPCIE connector 1 and the second CPCIE connector 2 on the data backplane may be connectors available on the market and having a model number of HMMH1200019A2B, the connectors support PCIE X8 signals, and the shape of the connectors meet the physical specification of CPCIE, and the connectors may be connected to two corresponding CPCIE connectors on the motherboard. Meanwhile, the third, fourth, fifth and sixth CPCIE connectors on the data backplane may be commercially available connectors of the model HMFH120P014A2A, the form of the connectors meets the physical specification of the CPCIE, and such a design of the data backplane allows the data backplane to simultaneously connect 4 PCIE high-speed devices at most, and the devices are independent from each other, without affecting the use of other interfaces. In this embodiment, the first PCIE driver chip 7 and the second PCIE driver chip 8 may be commercially available chips of an ASM1468 from ASMedia, so as to enhance the PCIE signal driving capability and ensure the signal quality. In this embodiment, the I2C switch chip 9 may be a commercially available chip with model number PCA9546 available from texas instruments in usa, and is used for address identification of an I2C bus, so as to prevent address collision of I2C devices when using I2C signals when externally connecting high-speed devices.

Because the setting of first PCIE driver chip 7 and second PCIE driver chip 8 is for preventing that mainboard PCIE signal can not reach the signal quality requirement, consequently technical personnel in the field can understand, the utility model discloses the quantity and the relation of connection of PCIE driver chip can make the change according to actual demand on the data backplate. For example, in another embodiment of the present invention, the PCIE Redriver chip may not be disposed on the data backplane, that is, the first CPCIE connector 1 does not directly communicate with the third CPCIE connector 3 and the fourth CPCIE connector 4 via the PCIE Redriver chip, and the second CPCIE connector 2 does not directly communicate with the fifth CPCIE connector 5 and the sixth CPCIE connector 6 via the PCIE Redriver chip, which relatively can reduce the cost. The utility model discloses a still another embodiment, PCIE Redriver chip quantity on the data backplate is four, and divide into two sets ofly, a set of two PCIE Redriver chip communications are connected between second CPCIE connector 2 and fifth CPCIE connector 5, another two PCIE Redriver chip communications of group are connected between second CPCIE connector 2 and sixth CPCIE connector 6, to the PCIE signal reinforcing driving force of second CPCIE connector 2 transmission, also can guarantee signal quality when fifth CPCIE connector 5 and sixth CPCIE connector 6 connect 4 PCIE high-speed devices altogether at most. Referring to fig. 2 and 3, fig. 2 is a schematic diagram of a connector layout on one side of a preferred embodiment of the data backplane of the present invention, and fig. 3 is a schematic diagram of a connector layout on the other side of the preferred embodiment. The backplane 10 is typically a PCB circuit board, and those skilled in the art will appreciate that fig. 2 and 3 are only used to illustrate the layout of the connector, and other components on the backplane 10 are omitted. In the preferred embodiment, the first CPCIE connector 1 and the second CPCIE connector 2 are disposed on one side of the backplane 10, and the third CPCIE connector 3, the fourth CPCIE connector 4, the fifth CPCIE connector 5 and the sixth CPCIE connector 6 are disposed on the other side of the backplane 10; the structural space can be fully utilized compared to all connectors on one side of the backplane 10. The positions of the first CPCIE connector 1 and the second CPCIE connector 2 are set corresponding to the corresponding servers on the server motherboard, and in this embodiment, the first CPCIE connector 1 and the second CPCIE connector 2 are spaced in parallel on one side of the backplane 10. The third CPCIE connector 3 and the fourth CPCIE connector 4 are arranged opposite to each other up and down on the other side surface of the backplane 10, and the fifth CPCIE connector 5 and the sixth CPCIE connector 6 are arranged opposite to each other up and down on the other side surface of the backplane 10; therefore, the connected PCIE high-speed devices are all parallel up and down, the structural space is fully utilized, and the area of the chassis of the server cannot be enlarged.

To sum up, the data backplane of the utility model can extend the PCIE interface; and as long as the interface and the signal are in accordance, different PCIE high-speed devices can be carried.

As described above, various other changes and modifications may be made by those skilled in the art based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the scope of the appended claims.

Claims

1. A data backplane, comprising: the back board is arranged on the back board and used for connecting a first CPCIE connector and a second CPCIE connector which correspond to the CPCIE connectors on the mainboard to transmit PCIE X8 signals, and the back board is arranged on a third CPCIE connector, a fourth CPCIE connector, a fifth CPCIE connector and a sixth CPCIE connector which are used for connecting PCIE equipment to transmit PCIE X4 signals; the first CPCIE connector is in communication connection with the third CPCIE connector and the fourth CPCIE connector, and the second CPCIE connector is in communication connection with the fifth CPCIE connector and the sixth CPCIE connector, so that communication connection between the mainboard and PCIE equipment connected to the backboard is established.

2. The data backplane of claim 1, further comprising an I2C switch chip disposed on the backplane, the I2C switch chip communicatively coupled to one of the first CPCIE connector and the second CPCIE connector, and the I2C switch chip further communicatively coupled to a third CPCIE connector, a fourth CPCIE connector, a fifth CPCIE connector, and a sixth CPCIE connector.

3. The data backplane of claim 1, wherein the data backplane is a data backplane adapted for use with a 2U server.

4. The data backplane of claim 1, further comprising at least one PCIE driver chip disposed on the data backplane; the PCIE Redriver chip is in communication connection with the first CPCIE connector and a third CPCIE connector and/or a fourth CPCIE connector corresponding to the first CPCIE connector, or the PCIE Redriver chip is in communication connection with the second CPCIE connector and a fifth CPCIE connector and/or a sixth CPCIE connector corresponding to the second CPCIE connector.

5. The data backplane of claim 1, wherein the first and second CPCIE connectors are disposed on one side of the backplane, and the third, fourth, fifth, and sixth CPCIE connectors are disposed on another side of the backplane.

6. The data backplane of claim 5, wherein the third and fourth CPCIE connectors are disposed opposite one another at a location on the other side of the backplane, and the fifth and sixth CPCIE connectors are disposed opposite one another at a location on the other side of the backplane.

7. The data backplane of claim 1, wherein the first and second CPCIE connectors are connectors of model HMMH1200019 A2B.

8. The data backplane of claim 1, wherein the third, fourth, fifth, and sixth CPCIE connectors are connectors of model number HMFH120P014 A2A.

9. The data backplane of claim 4, wherein the PCIE driver chip is an ASM1468 chip.

10. The data backplane of claim 2, wherein the I2C switch chip is a model PCA9546 chip.