CN210271564U - Display substrate and display device - Google Patents
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- CN210271564U CN210271564U CN201921825851.4U CN201921825851U CN210271564U CN 210271564 U CN210271564 U CN 210271564U CN 201921825851 U CN201921825851 U CN 201921825851U CN 210271564 U CN210271564 U CN 210271564U
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Abstract
The utility model provides a display substrates and display device, wherein, display substrates includes display area and non-display area, the signal spreads into display area through non-display area, wherein, non-display area is including the first conducting layer that is located substrate base plate in proper order, the first insulating layer, the second conducting layer, second insulating layer and third conducting layer, bind the second via hole that includes the first via hole that runs through the first insulating layer and runs through the second insulating layer in the region, first via hole is configured to make first conducting layer and second conducting layer electricity connect, the second via hole is configured to make second conducting layer and third conducting layer electricity connect, it is located non-display area to bind the region, the orthographic projection of first via hole on substrate base plate does not coincide with the orthographic projection of second via hole on substrate base plate. The utility model provides a display substrate and display device can improve the transmission speed of utilizing the signal of binding regional transmission among the display device.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a display substrate and display device.
Background
The display substrate generally includes a display area and a non-display area, wherein the non-display area includes a bonding area, and pads in the bonding area are respectively connected with signal lines and peripheral circuits in the display area to ensure normal operation of the display substrate.
In the related art, in order to improve the display effect of the display device, more and more pixel units are fabricated in the display substrate, and in the display device with high PPI (pixel count per inch), the original signal transmission speed of the pad in the bonding region of the display substrate cannot meet the requirement of the high PPI display device on the signal transmission speed.
SUMMERY OF THE UTILITY MODEL
An embodiment of the utility model provides a display substrates and display device to bind the problem that regional signal transmission speed originally can't satisfy high PPI display device to signal transmission speed's requirement in solving the display substrates among the correlation technique.
In order to solve the technical problem, the utility model provides a technical scheme as follows:
in a first aspect, an embodiment of the present invention provides a display substrate, which includes a display region and a non-display region, wherein a signal is transmitted to the display region through the non-display region, wherein the non-display region comprises a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer which are sequentially arranged on the substrate, the binding region comprises a first via hole penetrating through the first insulating layer and a second via hole penetrating through the second insulating layer, the first via is configured to electrically connect the first conductive layer and the second conductive layer, the second via is configured to electrically connect the second conductive layer and the third conductive layer, the binding region is located in the non-display region, and the orthographic projection of the first via hole on the substrate is not coincident with the orthographic projection of the second via hole on the substrate.
Further, the shortest distance between the orthographic projection contour of the first via hole on the substrate base plate and the orthographic projection contour of the second via hole on the substrate base plate is greater than or equal to one half of the size of the first via hole.
Further, the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
Further, the size of the first via is larger than the size of the second via.
Further, the slope angle of the first via hole is larger than that of the second via hole.
Furthermore, the via holes in the same row in the pads are all first via holes or all second via holes.
Furthermore, the display area comprises sub-pixels, grid lines and data lines which are arranged in an array mode, the sub-pixels comprise thin film transistor array layers and electrodes, the grid electrodes of the thin film transistor array layers are connected with the grid lines, the source electrodes of the thin film transistor array layers are connected with the data lines, and the drain electrodes of the thin film transistor array layers are connected with the electrodes.
Further, the thin film transistor array layer comprises an active layer, a grid electrode insulating layer, a grid electrode, an interlayer insulating layer and a metal layer which are sequentially stacked on the substrate, wherein an orthographic projection area of the grid electrode on the substrate is located in the orthographic projection area of the grid electrode insulating layer on the substrate, third through holes penetrating through the interlayer insulating layer are respectively formed in two sides of the grid electrode of the interlayer insulating layer, and two metal sections which are separated from each other in the metal layer are electrically connected with the active layer through the third through holes respectively to form a source electrode and a drain electrode.
Further, the first conductive layer is made of the same material as the gate electrode, and the first conductive layer extends into the display region.
Further, the second conductive layer is made of the same material as the metal layer, and the display region does not include the second conductive layer.
Further, the third conductive layer is a transparent conductive layer, the material of the third conductive layer is the same as that of the electrode, and the display area does not include the third conductive layer.
Further, the second insulating layer is a passivation layer, extends to the display region, and covers a portion of the metal layer.
Further, the display device further comprises a buffer layer, wherein the buffer layer is located between the first conductive layer and the substrate base plate at the part of the binding region, and the buffer layer is located between the active layer and the substrate base plate at the part of the display region.
Furthermore, the orthographic projection area of the first via hole on the substrate base plate comprises a first conducting layer, a second insulating layer and a third conducting layer which are sequentially located on the substrate base plate.
Furthermore, the orthographic projection area of the second via hole on the substrate base plate comprises a first conducting layer, a first insulating layer, a second conducting layer and a third conducting layer which are sequentially located on the substrate base plate.
Furthermore, the display substrate further comprises a third insulating layer located on one side, away from the substrate, of the third conducting layer, a channel penetrating through the third insulating layer is formed in the third insulating layer, the orthographic projections of the first via hole and the second via hole on the substrate are located in the orthographic projection of the channel on the substrate, and the third insulating layer is located outside the binding region.
In a second aspect, the present invention further provides a display device, including the display substrate as described above.
The utility model provides an among the technical scheme, the orthographic projection of first via hole on the substrate base plate does not coincide with the orthographic projection of second via hole on the substrate base plate to avoid the great condition of the regional unevenness's of binding degree of display substrates when coinciding, can ensure to bind regional degree in the display substrates, also can improve like this and bind the area of contact of electrified particle in third conducting layer and the conducting resin in the region, and then reach the effect that improves signal transmission speed. Therefore, the utility model provides a technical scheme can improve and bind regional mild in the display substrate, and then utilizes the transmission speed of the signal of binding regional transmission among the improvement display device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a top view of a bonding region of a display substrate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1;
fig. 3 is a schematic diagram illustrating distribution of pads in a bonding area of a display substrate according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a positional relationship between pads in a display substrate according to an embodiment of the present invention;
fig. 5 is a diagram illustrating a positional relationship between an orthographic projection of a first via hole on a substrate and an orthographic projection of a second via hole on the substrate in a display substrate according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram of a portion of a film layer in a display area and a bonding area of a display substrate according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a method for manufacturing a display substrate according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
In the related art, in order to improve the display effect of the display device, more and more pixel units are fabricated in the display substrate, and in the display device with high PPI (pixel count per inch), the original signal transmission speed of the pad in the bonding region of the display substrate cannot meet the requirement of the high PPI display device on the signal transmission speed.
The embodiment of the utility model provides a to above-mentioned problem, provide a display substrate and display device, can solve the problem that the signal transmission speed that binds regional pad originally in the display substrate of correlation technique can't satisfy high PPI display device to the requirement of signal transmission speed.
An embodiment of the present invention provides a display substrate, including display area and non-display area, the signal passes through the non-display area spreads into the display area, wherein, as shown in fig. 1 and fig. 2, the non-display area includes first conducting layer 130, first insulating layer 110, second conducting layer 140, second insulating layer 120 and third conducting layer 150 that are located on substrate 100 in proper order, wherein, including the first via hole 111 that runs through the first insulating layer 110 and the second via hole 121 that runs through the second insulating layer 120 in the bonding area of display substrate, the first via hole 111 is configured to make the first conducting layer 130 and the second conducting layer 140 electrically connect, the second via hole 121 is configured to make the second conducting layer 140 and the third conducting layer 150 electrically connect, the bonding area is located in the non-display area, the orthographic projection of the first via hole 111 on the substrate with the orthographic projection of the second via hole 121 on the substrate Are not coincident.
The embodiment of the utility model provides an in, the orthographic projection of first via hole on the substrate base plate does not coincide with the orthographic projection of second via hole on the substrate base plate to the regional unevenness's of binding the great condition of degree of display substrates when avoiding coinciding can ensure to bind regional degree in the display substrates, also can improve like this and bind the area of contact of electrified particle in third conducting layer and the conducting resin in the region, and then reaches the effect that improves signal transmission speed. Therefore, the utility model provides a technical scheme can improve and bind regional mild in the display substrate, and then utilizes the transmission speed of the signal of binding regional transmission among the improvement display device.
In an embodiment of the present invention, the positional relationship of each film layer in the binding region is as shown in fig. 1 and fig. 2 (for convenience of viewing, each film layer above the third conductive layer 150 is hidden in fig. 1, the first conductive layer 130 and the second conductive layer 140 are film layers covered by the third conductive layer 150, and are shown by filling dotted lines in fig. 1 for illustrating the positions of the first conductive layer 130 and the second conductive layer 140, and the first via hole 111 and the second via hole 121 are also structures covered by the third conductive layer 150, and are shown by dotted frames in fig. 1 for illustrating the positions of the first via hole 111 and the second via hole 121), and the forming sequence of each film layer on the substrate 100 may be that the first conductive layer 130, the first insulating layer 110, the second conductive layer 140, the second insulating layer 120, and the third conductive layer 150 are sequentially formed from the substrate to one side.
After the first insulating layer 110 is formed, the first via hole 111 penetrating the first insulating layer 110 is opened, so that the second conductive layer 140 can be connected to the first conductive layer 130 through the first insulating layer 110 by the first via hole 111 when the second conductive layer 140 is formed.
Similarly, after the second insulating layer 120 is formed, the second via 121 penetrating the second insulating layer 120 is opened, so that the third conductive layer 150 can be connected to the second conductive layer 140 through the second insulating layer 120 via the second via 121 when the third conductive layer 150 is formed.
The first conductive layer 130, the first insulating layer 110, the second conductive layer 140, the second insulating layer 120, and the third conductive layer 150, and the first via hole 111 in the first insulating layer 110 and the second via hole 121 in the second insulating layer 120 collectively constitute a pad. The plurality of pads are arranged in the array in the bonding region, as shown in fig. 3, wherein the pads may have a rectangular structure, as shown in fig. 4, the length of the pad may be 1200um, the width of the pad may be 15um, and the distance (pitch) between adjacent pads may be 28.5 um. Of course, the above is merely an example, the length of the pad may also be 1201um, the width of the pad may also be 16um, the pitch value between adjacent pads may be 29um, and so on. The pitch value is a pitch between two adjacent pads on the same long side.
Originally, when the orthographic projection of the first via hole on the substrate base plate and the orthographic projection of the second via hole on the substrate base plate coincide, the step difference between the perforated region and the non-perforated region in the binding region is very large, the contact area between the conductive adhesive and the third conductive layer 150 is reduced, and the signal transmission speed of the bonding pad in the binding region cannot meet the requirement of the high PPI display device on the signal transmission speed.
The embodiment of the utility model provides a, through orthographic projection of first via hole 111 on the substrate base plate and the orthographic projection design of second via hole 121 on the substrate base plate for not coinciding, as shown in FIG. 2, can shorten the section difference between each part of binding region like this, increase the area of contact between conducting resin and the third conducting layer 150 simultaneously, improve the signal transmission speed of bonding pad in the binding region, reach the requirement of high PPI display device to signal transmission speed.
The first via holes 111 are distributed on the first insulating layer 110 in an array, the second via holes 121 are distributed on the second insulating layer 120 in an array, and the first via holes 111 and the second via holes 121 are arranged in a staggered manner. The flatness of the display substrate at the bonding area portion may be adjusted by adjusting the arrangement distance between the first via holes 111 and the arrangement distance between the second via holes 121.
Further, as shown in fig. 2, an orthographic projection area of the first via 111 on the substrate 100 includes a first conductive layer 130, a second conductive layer 140, a second insulating layer 120, and a third conductive layer 150, which are sequentially located on the substrate 100.
Further, as shown in fig. 2, an orthographic projection area of the second via 121 on the substrate 100 includes a first conductive layer 130, a first insulating layer 110, a second conductive layer 140, and a third conductive layer 150, which are sequentially located on the substrate 100.
Further, the shortest distance between the orthographic projection contour of the first via 111 on the substrate base plate and the orthographic projection contour of the second via 121 on the substrate base plate is greater than or equal to one half of the size of the first via 111.
As shown in fig. 5, d indicated in fig. 5 is a shortest distance between an orthographic projection profile 111 'of the first via 111 on the substrate and an orthographic projection profile 121' of the second via 121 on the substrate.
Setting d to be greater than or equal to one-half the size of the first via hole 111 can ensure the smoothness of the entire bonding area. The size of the first via hole 111 and the second via hole 121 is typically 8-10um, and when the size of the first via hole 111 is 8um, d may be 4 um.
Wherein a thickness of the first insulating layer 110 may be greater than a thickness of the second insulating layer 120.
At this time, the size of the first via hole 111 formed in the first insulating layer 110 by using the etching process may be larger than the size of the second via hole 121 formed in the second insulating layer 121.
In addition, the slope angle of the first via hole 111 formed in the first insulating layer 110 by using the etching process may also be greater than the slope angle of the second via hole 121 formed in the second insulating layer 121.
Furthermore, the via holes in the same row in the pads are all first via holes or all second via holes.
That is, in the pads in fig. 3, the vias in one row are all first vias, and the vias in two rows above and below the row are all second vias.
Thus, the positions of the pads in the non-display area can be arranged orderly, and the connection of signal lines and the signal transmission in the display substrate are facilitated.
Further, as shown in fig. 6, the display region includes sub-pixels 600, gate lines and data lines arranged in an array, the sub-pixels include a thin film transistor array layer 610 and electrodes 620, a gate 611 of the thin film transistor array layer 610 is connected to the gate lines, a source 612 of the thin film transistor array layer 610 is connected to the data lines, and a drain 613 of the thin film transistor array layer 610 is connected to the electrodes 620.
As shown in fig. 6, when the electrode 620 is charged, the gate line is used to provide a turn-on signal to the gate electrode 611 of the thin film transistor array layer 610, so that the source electrode 612 and the drain electrode 613 of the thin film transistor array layer 610 are turned on, and at this time, a data signal in the data line can charge the electrode 620, so that the sub-pixel emits light with a preset brightness.
The thin film transistor array layer 610 includes an active layer 614, a gate insulating layer 615, a gate 611, an interlayer insulating layer 616 and a metal layer sequentially stacked on the substrate base plate, wherein an orthographic projection area of the gate 611 on the substrate base plate 100 is located in an orthographic projection area of the gate insulating layer 615 on the substrate base plate 100, the interlayer insulating layer 616 is respectively provided with third via holes 617 penetrating through the interlayer insulating layer 616 on two sides of the gate 611, and two metal segments separated from each other in the metal layer are respectively electrically connected with the active layer 614 through the third via holes 617 to form a source 612 and a drain 613.
In addition, a light-shielding layer 618 may be formed between the buffer layer 160 and the substrate 100, and an orthographic projection of the light-shielding layer 618 on the substrate 100 coincides with an orthographic projection of the active layer 614 on the substrate 100, so as to shield external light, prevent the active layer from being affected by the external light, and improve the reliability of the operation of the thin film transistor array layer 610.
Further, the first conductive layer 130 is made of the same material as the gate electrode 611, and the first conductive layer 130 extends into the display region.
The first conductive layer 130 may be a metal material layer, and when the gate electrode 611 of the thin film transistor array layer is formed in the display region, a metal layer may be simultaneously formed on the entire surface of the display substrate, and then the gate electrode 611 is formed in the display region and the first conductive layer 130 is formed in the non-display region by a single patterning process.
When the pad is located at a Source side of a data signal, the first conductive layer 130 extends to the display region and then is connected to the data line through a trace in the display region, for transmitting the data signal. When the display device does not use a Gate Driver on Array (GOA) and the pad is located at the side of the source of the Gate scan signal, the first conductive layer 130 may extend to the display region and be directly connected to the Gate line.
Further, the second conductive layer 140 is made of the same material as the metal layer, and the display region does not include the second conductive layer 140.
The second conductive layer 140 does not extend to the display area, and is used only to transmit electrical signals of the binding area. When the second conductive layer 140 is manufactured, a metal material layer may be formed on the entire surface of the display substrate at the same time, and then a metal layer may be formed in the display region and the second conductive layer 140 may be formed in the non-display region by a single patterning process.
Thus, compared with the process of separately manufacturing the metal layer and the second conductive layer 140, the time and the process are saved, and the manufacturing efficiency of the display substrate is improved.
Further, the third conductive layer 150 may be a transparent conductive layer, and the material of the third conductive layer 150 is the same as that of the electrode 620.
The material of the third conductive layer 150 may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). And the material of the electrode 620 may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) as well.
Therefore, in this embodiment, the transparent conductive material layer may be formed on the entire surface of the display substrate at the same time, and then the electrode 620 may be formed in the display region and the third conductive layer 150 may be formed in the non-display region through a single patterning process.
Thus, compared with the respective fabrication of the electrode 620 and the third conductive layer 150, time and process are saved, and the fabrication efficiency of the display substrate is improved.
It should be noted that, the extension of any one of the first conductive layer 130, the second conductive layer 140, and the third conductive layer 150 to the display area can achieve the function of transmitting signals of the non-display area to the display area, however, the reason for selecting only the first conductive layer 130 to extend to the display area in this embodiment is that there are other signal traces on the side of the third conductive layer 150 away from the substrate in the area between the bonding area and the display area, and the first conductive layer 130 is the farthest away from other signals and the most insulating layers are disposed between them compared with the second conductive layer 140 and the third conductive layer 150, so that the first conductive layer 130 is the conductive layer which is the least likely to be shorted with other traces among the three conductive layers, and the reliability of transmitting signals by selecting the first conductive layer 130 to extend to the display area is the highest.
Of course, other embodiments of the present invention may employ the second conductive layer 140 or the third conductive layer 150 to extend to the display area, which is not limited herein.
Further, the second insulating layer 120 may be a passivation layer, which extends to the display region and covers a portion of the metal layer.
The passivation layer can protect the second conductive layer 140 from being oxidized, and ensure the normal operation of the second conductive layer 140 in the bonding region. Similarly, the metal layer in the display region also needs a passivation layer to protect it from oxidation, ensuring proper operation of the metal layer.
Therefore, when the passivation layer in the binding region is formed, the passivation layer covering the metal layer can be formed in the display region at the same time, and the manufacturing efficiency of the display substrate is improved.
Further, as shown in fig. 2 and 6, the binding region of the display substrate may further include a buffer layer 160, a portion of the buffer layer 160 in the binding region is between the first conductive layer 130 and the substrate 100, and a portion of the buffer layer 160 in the display region is between the active layer 614 and the substrate 100.
First, the buffer layer 160 can provide a flat surface for the first conductive layer 130; in addition, since the bonding region is generally located at the periphery of the display substrate and is vulnerable to external impact, the buffer layer 160 can also protect the first conductive layer 130 and reduce the impact on the first conductive layer 130.
Meanwhile, the buffer layer 160 is also required in the display region to provide a flat manufacturing surface for the thin film transistor array layer 610, so that when the flat layer in the bonding region is formed, the flat layer can be formed in the display region at the same time, and the manufacturing efficiency of the display substrate is improved.
Further, as shown in fig. 6, the bonding region further includes a channel 171 penetrating through a third insulating layer 170, the third insulating layer 170 is located on a side of the first insulating layer 110 and the second insulating layer 120 away from the substrate 100, and an orthographic projection of the first via 111 and the second via 121 on the substrate 100 is located in an orthographic projection of the channel 170 on the substrate 100.
In the present embodiment, after the second insulating layer 120 is formed and before the second via hole 121 is formed in the process of forming the display substrate, the third insulating layer 170 is formed on the second insulating layer 120; forming a channel 171 penetrating through the third insulating layer 170 on the third insulating layer 170, wherein the channel 171 is greater than or equal to a binding region, and the binding region is located in the channel 171; thereafter, a second via 121 penetrating the second insulating layer 120 is formed through the via 171.
In the manufacturing process of the display substrate, the manufacturing of the outer film layer of the binding region can be completed, and the manufacturing of the bonding pad in the binding region can not be influenced by arranging the channel 171, so that the manufacturing compatibility of the display substrate is improved.
The embodiment of the utility model provides a still provide a display substrate's manufacturing method, as shown in FIG. 7, the method includes:
step 701: forming a first conductive layer on a substrate;
step 702: forming a first insulating layer covering the first conducting layer, and forming a first through hole penetrating through the first insulating layer in the binding region;
step 703: forming a second conductive layer covering the first insulating layer, wherein the second conductive layer is connected with a part of the first conductive layer through the first via hole;
step 704: forming a second insulating layer covering the second conductive layer, and forming a second via hole penetrating through the second insulating layer in the binding region, wherein the orthographic projection of the first via hole on the substrate base plate is not coincident with the orthographic projection of the second via hole on the substrate base plate;
step 705: and forming a third conducting layer covering the second insulating layer, wherein the third conducting layer is connected with part of the second conducting layer through the second through hole.
The embodiment of the utility model provides an in, the orthographic projection of first via hole on the substrate base plate does not coincide with the orthographic projection of second via hole on the substrate base plate to the regional unevenness's of binding the great condition of degree of display substrates when avoiding coinciding can ensure to bind regional degree in the display substrates, also can improve like this and bind the area of contact of electrified particle in third conducting layer and the conducting resin in the region, and then reaches the effect that improves signal transmission speed. Therefore, the utility model provides a technical scheme can improve and bind regional mild in the display substrate, and then utilizes the transmission speed of the signal of binding regional transmission among the improvement display device.
In an embodiment of the present invention, the positional relationship of each film layer in the binding region is as shown in fig. 1 and fig. 2 (for convenience of viewing, each film layer above the third conductive layer 150 is hidden in fig. 1, the first conductive layer 130 and the second conductive layer 140 are film layers covered by the third conductive layer 150, and are shown by filling dotted lines in fig. 1 for illustrating the positions of the first conductive layer 130 and the second conductive layer 140, and the first via hole 111 and the second via hole 121 are also structures covered by the third conductive layer 150, and are shown by dotted frames in fig. 1 for illustrating the positions of the first via hole 111 and the second via hole 121), and the forming sequence of each film layer on the substrate 100 may be that the first conductive layer 130, the first insulating layer 110, the second conductive layer 140, the second insulating layer 120, and the third conductive layer 150 are sequentially formed from the substrate to one side.
After the first insulating layer 110 is formed, the first via hole 111 penetrating the first insulating layer 110 is opened, so that the second conductive layer 140 can be connected to the first conductive layer 130 through the first insulating layer 110 by the first via hole 111 when the second conductive layer 140 is formed.
Similarly, after the second insulating layer 120 is formed, the second via 121 penetrating the second insulating layer 120 is opened, so that the third conductive layer 150 can be connected to the second conductive layer 140 through the second insulating layer 120 via the second via 121 when the third conductive layer 150 is formed.
The first conductive layer 130, the first insulating layer 110, the second conductive layer 140, the second insulating layer 120, and the third conductive layer 150, and the first via hole 111 in the first insulating layer 110 and the second via hole 121 in the second insulating layer 120 collectively constitute a pad. The plurality of pads are arranged in the array in the bonding region, as shown in fig. 3, wherein the pads may have a rectangular structure, as shown in fig. 4, the length of the pad may be 1200um, the width of the pad may be 15um, and the distance (pitch) between adjacent pads may be 28.5 um. Of course, the above is merely an example, the length of the pad may also be 1201um, the width of the pad may also be 16um, the pitch value between adjacent pads may be 29um, and so on. The pitch value is a pitch between two adjacent pads on the same long side.
Originally, when the orthographic projection of the first via hole on the substrate base plate and the orthographic projection of the second via hole on the substrate base plate coincide, the step difference between the perforated region and the non-perforated region in the binding region is very large, the contact area between the conductive adhesive and the third conductive layer 150 is reduced, and the signal transmission speed of the bonding pad in the binding region cannot meet the requirement of the high PPI display device on the signal transmission speed.
The embodiment of the utility model provides a, through orthographic projection of first via hole 111 on the substrate base plate and the orthographic projection design of second via hole 121 on the substrate base plate for not coinciding, as shown in FIG. 2, can shorten the section difference between each part of binding region like this, increase the area of contact between conducting resin and the third conducting layer 150 simultaneously, improve the signal transmission speed of bonding pad in the binding region, reach the requirement of high PPI display device to signal transmission speed.
The first via holes 111 are distributed on the first insulating layer 110 in an array, the second via holes 121 are distributed on the second insulating layer 120 in an array, and the first via holes 111 and the second via holes 121 are arranged in a staggered manner. The flatness of the display substrate at the bonding area portion may be adjusted by adjusting the arrangement distance between the first via holes 111 and the arrangement distance between the second via holes 121.
Further, the step of forming a second insulating layer covering the second conductive layer and forming a second via penetrating through the second insulating layer includes:
forming a second insulating layer covering the second conductive layer;
forming a third insulating layer covering the second conductive layer, and forming a channel penetrating through the third insulating layer, wherein the orthographic projection of the channel on the substrate covers the binding region;
and forming a second through hole penetrating through the second insulating layer in the binding region through the channel, wherein the orthographic projections of the first through hole and the second through hole on the substrate base plate are positioned in the orthographic projection of the channel on the substrate base plate.
In this embodiment, after the second insulating layer is formed and before the second via hole is formed in the process of forming the display substrate, a third insulating layer is formed on the second insulating layer; forming a channel penetrating through the third insulating layer on the third insulating layer, wherein the channel is greater than or equal to a binding region, and the binding region is positioned in the channel; and then forming a second via hole penetrating through the second insulating layer through the channel.
In the manufacturing process of the display substrate, the manufacturing of the outer film layer of the binding region can be completed, and the manufacturing of the bonding pad in the binding region can not be influenced by arranging the channel, so that the manufacturing compatibility of the display substrate is improved.
The embodiment of the utility model provides a display device is still provided, include as above display substrate.
The display device may be a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, etc.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the invention belongs. The use of "first," "second," and similar terms in the description herein do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
The embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, which are only illustrative and not restrictive, and those skilled in the art can make many forms without departing from the spirit and scope of the present invention.
Claims (17)
1. A display substrate, comprising a display region and a non-display region, wherein a signal is transmitted into the display region through the non-display region, wherein the non-display region comprises a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer which are sequentially located on a substrate, a bonding region comprises a first via hole penetrating through the first insulating layer and a second via hole penetrating through the second insulating layer, the first via hole is configured to electrically connect the first conductive layer and the second conductive layer, the second via hole is configured to electrically connect the second conductive layer and the third conductive layer, the bonding region is located in the non-display region, and an orthographic projection of the first via hole on the substrate does not coincide with an orthographic projection of the second via hole on the substrate.
2. The display substrate of claim 1, wherein a shortest distance between an orthographic projection profile of the first via on the substrate base plate and an orthographic projection profile of the second via on the substrate base plate is greater than or equal to one-half of a size of the first via.
3. The display substrate according to claim 1, wherein a thickness of the first insulating layer is larger than a thickness of the second insulating layer.
4. The display substrate of claim 3, wherein the first via has a size larger than a size of the second via.
5. The display substrate of claim 3, wherein a slope angle of the first via is greater than a slope angle of the second via.
6. The display substrate of claim 1, wherein the vias in a same row of the plurality of pads are all first vias or all second vias.
7. The display substrate according to claim 1, wherein the display region comprises sub-pixels, gate lines and data lines arranged in an array, the sub-pixels comprise a thin film transistor array layer and electrodes, a gate electrode of the thin film transistor array layer is connected with the gate lines, a source electrode of the thin film transistor array layer is connected with the data lines, and a drain electrode of the thin film transistor array layer is connected with the electrodes.
8. The display substrate according to claim 7, wherein the thin film transistor array layer comprises an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer and a metal layer sequentially stacked on the substrate, wherein an orthographic projection area of the gate electrode on the substrate is located in an orthographic projection area of the gate insulating layer on the substrate, the interlayer insulating layer is respectively provided with third via holes penetrating through the interlayer insulating layer on two sides of the gate electrode, and two metal segments separated from each other in the metal layer are respectively electrically connected with the active layer through the third via holes to form a source electrode and a drain electrode.
9. The display substrate according to claim 8, wherein the first conductive layer is made of the same material as the gate electrode, and the first conductive layer extends into the display region.
10. The display substrate according to claim 9, wherein the second conductive layer is the same material as the metal layer, and the display region does not include the second conductive layer.
11. The display substrate according to claim 10, wherein the third conductive layer is a transparent conductive layer, the third conductive layer is made of the same material as the electrode, and the display region does not include the third conductive layer.
12. The display substrate according to claim 8, wherein the second insulating layer is a passivation layer, extends to the display region, and covers a portion of the metal layer.
13. The display substrate of claim 8, further comprising a buffer layer between the first conductive layer and the base substrate at a portion of the binding region, the buffer layer between the active layer and the base substrate at a portion of the display region.
14. The display substrate of claim 1, wherein an orthographic projection area of the first via hole on the substrate comprises a first conductive layer, a second insulating layer and a third conductive layer sequentially on the substrate.
15. The display substrate of claim 1, wherein an orthographic projection area of the second via hole on the substrate comprises a first conductive layer, a first insulating layer, a second conductive layer and a third conductive layer sequentially on the substrate.
16. The display substrate according to claim 1, further comprising a third insulating layer on a side of the third conductive layer facing away from the substrate, wherein the third insulating layer defines a channel penetrating through the third insulating layer, an orthogonal projection of the first via hole and the second via hole on the substrate is located within an orthogonal projection of the channel on the substrate, and the third insulating layer is located outside the bonding region.
17. A display device comprising the display substrate according to any one of claims 1 to 16.
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| CN201921825851.4U CN210271564U (en) | 2019-10-28 | 2019-10-28 | Display substrate and display device |
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| CN201921825851.4U CN210271564U (en) | 2019-10-28 | 2019-10-28 | Display substrate and display device |
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| CN112103299A (en) * | 2020-09-04 | 2020-12-18 | Tcl华星光电技术有限公司 | Preparation method of display panel and display panel |
| CN113345950A (en) * | 2021-06-28 | 2021-09-03 | 京东方科技集团股份有限公司 | Display panel and manufacturing method thereof |
| WO2021217600A1 (en) * | 2020-04-30 | 2021-11-04 | 京东方科技集团股份有限公司 | Mirrored face display panel, manufacturing method therefor, and display apparatus |
| CN113867043A (en) * | 2020-06-30 | 2021-12-31 | 京东方科技集团股份有限公司 | Light-emitting substrate, preparation method thereof and display device |
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| WO2021217600A1 (en) * | 2020-04-30 | 2021-11-04 | 京东方科技集团股份有限公司 | Mirrored face display panel, manufacturing method therefor, and display apparatus |
| US12080726B2 (en) | 2020-04-30 | 2024-09-03 | Boe Technology Group Co., Ltd. | Glossy display panel, manufacturing method thereof and display device |
| CN113867043A (en) * | 2020-06-30 | 2021-12-31 | 京东方科技集团股份有限公司 | Light-emitting substrate, preparation method thereof and display device |
| CN113867043B (en) * | 2020-06-30 | 2023-01-10 | 京东方科技集团股份有限公司 | Light-emitting substrate, preparation method thereof and display device |
| CN112103299A (en) * | 2020-09-04 | 2020-12-18 | Tcl华星光电技术有限公司 | Preparation method of display panel and display panel |
| WO2022047971A1 (en) * | 2020-09-04 | 2022-03-10 | Tcl华星光电技术有限公司 | Manufacturing method for display panel, and display panel |
| CN112103299B (en) * | 2020-09-04 | 2022-05-03 | Tcl华星光电技术有限公司 | Preparation method of display panel and display panel |
| US11573462B2 (en) | 2020-09-04 | 2023-02-07 | Tcl China Star Optoelectronics Technology Co., Ltd | Manufacturing method of display panel and display panel |
| CN113345950A (en) * | 2021-06-28 | 2021-09-03 | 京东方科技集团股份有限公司 | Display panel and manufacturing method thereof |
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