CN208654281U - A kind of test circuit based on charging chip - Google Patents
A kind of test circuit based on charging chip Download PDFInfo
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- CN208654281U CN208654281U CN201821192436.5U CN201821192436U CN208654281U CN 208654281 U CN208654281 U CN 208654281U CN 201821192436 U CN201821192436 U CN 201821192436U CN 208654281 U CN208654281 U CN 208654281U
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Abstract
The utility model provides a kind of test circuit based on charging chip, comprising: simulated battery circuit, slowdown monitoring circuit to be checked, charging chip and charging current measuring circuit；Simulated battery circuit includes: that supply port, simulated battery internal resistance and the first output port, supply port are connect with power supply, and simulated battery internal resistance is connected between the first output port and ground, and the first output port is connect with supply port；Slowdown monitoring circuit to be checked includes the second input port, second output terminal mouth and the testing resistance being connected between the second input port and second output terminal mouth；Second input port is electrically connected with the first output port；Charging chip is connected between second output terminal mouth and ground；Charging current measuring circuit includes the first detection port, the second detection port and voltage measurement output port, and the first detection port is electrically connected to the both ends of testing resistance with the second detection port；Voltage measurement output port output voltage measured value.It is whether normal that charging chip work can be monitored.
Description
Technical Field
The utility model relates to an electron technical field especially relates to a test circuit based on charging chip.
Background
In order to ensure the safety of the online banking transaction of the user, the bank can issue intelligent password equipment to the user when transacting the bank card for the user, so as to assist the user transacting the online banking transaction. When the user carries out online banking transaction, various money transactions can be completed only by using the intelligent password device, otherwise, the client prompts the user to insert the intelligent password device.
With the rapid development of the intelligent password device and the dependence of the online banking transaction on the intelligent password device, the intelligent password device is frequently used by users, especially users who often handle large-amount online banking transactions. However, since the smart password device is not detachable, the battery cannot be replaced, and in order to increase the service life of the smart password device, a charging chip is often used in the industry to charge the battery of the smart password device.
The charging chips are produced in large batches by a production line of a factory, and before the charging chips are put into use, a simple test mode for testing whether the charging chips work normally is urgently needed in order to ensure that the charging chips used in the intelligent password equipment can achieve good charging capacity.
SUMMERY OF THE UTILITY MODEL
The present invention aims to solve one of the above problems.
The utility model aims to provide a test circuit based on charging chip.
In order to achieve the above object, the technical solution of the present invention is specifically realized as follows:
the utility model discloses an aspect provides a test circuit based on charging chip, include: the device comprises an analog battery circuit, a circuit to be detected, a charging chip and a charging current measuring circuit; wherein the analog battery circuit comprises at least: the power supply system comprises a power supply port, a simulated battery internal resistance and a first output port, wherein the power supply port is electrically connected with a power supply, the simulated battery internal resistance is connected between the first output port and an electrical ground end of the power supply, and the first output port is electrically connected with the power supply port; the circuit to be detected at least comprises a second input port, a second output port and a resistor to be detected, wherein the resistor to be detected is connected between the second input port and the second output port; the second input port is electrically connected with the first output port; the charging chip is connected between the second output port and the ground end of the power supply to charge the analog battery circuit, and when the charging chip charges the analog battery circuit, current flows through the resistor to be tested; the charging current measuring circuit comprises a first detection port, a second detection port and a voltage measurement output port, and the first detection port and the second detection port are electrically connected to two ends of the resistor to be measured; and the voltage measurement output port outputs a voltage measurement value, and the voltage measurement value is obtained according to the current flowing through the resistor to be measured.
Optionally, the analog battery circuit further includes: a first switching circuit and a first control port; wherein: the first switch circuit is electrically connected between the power supply port and the first output port, and is used for disconnecting or conducting a path between the power supply port and the first output port under the control of an output signal of the first control port.
Optionally, the first switching circuit includes: the switch comprises a first switch unit, a second switch unit, a first port, a second port, a third port and a fourth port; the first port is electrically connected with the power supply port, the second port is electrically connected with the first output port, the third port is electrically connected with the ground end of the power supply, and the fourth port is electrically connected with the first control port; the first switch unit is respectively connected with the first port, the second port and the second switch unit, the second switch unit is respectively connected with the third port, the fourth port and the first switch unit, and the first switch unit is used for conducting a path between the first port and the second port when the first switch unit and the second switch unit are both conducted under the control of an output signal of the first control port; when the first switch unit and the second switch unit are both turned off under the control of the output signal of the first control port, the path between the first port and the second port is disconnected.
Optionally, the analog battery circuit further includes: a unidirectional conducting circuit connected between the first switching circuit and the first output port; in operation, current flows from the first switching circuit through the unidirectional conducting circuit and to the first output port, and cannot flow from the first output port back to the first switching circuit.
Optionally, the analog battery circuit further includes: a filtering component; the filtering component is connected with the internal resistance of the analog battery in parallel and is connected between the first output port and the ground end of the power supply.
Optionally, the circuit to be detected further includes: a second switching circuit and a second control port; wherein: the second switch circuit is connected between the resistor to be tested and the second output port, and is used for switching off or switching on a path between the resistor to be tested and the second output port under the control of an output signal of the second control port.
Optionally, the second switching circuit includes: a third switching unit, a fourth switching unit, a fifth port, a sixth port, a seventh port, and an eighth port; the fifth port is electrically connected to one end of the resistor to be tested, which is connected with the second output port, the sixth port is electrically connected with the second output port, the seventh port is electrically connected with the ground end of the power supply, and the eighth port is electrically connected with the second control port; the third switching unit is respectively connected with the fifth port, the sixth port and the fourth switching unit, and the fourth switching unit is respectively connected with the seventh port, the eighth port and the third switching unit, so that when the third switching unit and the fourth switching unit are both turned on under the control of the output signal of the second control port, a path between the fifth port and the sixth port is turned on; when the third switch unit and the fourth switch unit are both turned off under the control of the output signal of the second control port, a path between the fifth port and the sixth port is disconnected.
Optionally, the charging current measuring circuit further includes: the high-side current detection amplifier, the first gain adjusting resistor and the second gain adjusting resistor; the high-side current detection amplifier comprises a first current detection access end, a second current detection access end, a measurement output end, a feedback end and a reference end, wherein: a first current detection access end of the high-side current detection amplifier is electrically connected to the first detection port, a second current detection access end of the high-side current detection amplifier is electrically connected to the second detection port, a measurement output end of the high-side current detection amplifier is electrically connected to the voltage measurement output port, the first gain adjustment resistor is electrically connected between the measurement output end and the feedback end, the second gain adjustment resistor is electrically connected between the feedback end and the reference end, and the reference end is electrically connected to a ground end of the power supply.
Alternatively to this, the first and second parts may,wherein, VOUTIs the voltage measurement value IsampleFor the current flowing through the resistor to be measured, R22Is the resistance to be measured, Ra1For the first gain adjustment resistor, Ra2Adjusting a resistance for the second gain.
Optionally, the high-side current detection amplifier employs a MAX9922 chip.
By the above-mentioned the technical scheme provided by the utility model, the utility model provides a test circuit based on charging chip through the voltage measurement value of charging current measuring circuit output, can monitor whether charging chip is in normal operating condition to and the charging chip that the discovery has the problem in time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a test circuit based on a charging chip according to embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of an analog battery circuit provided in embodiment 1 of the present invention;
fig. 3 is a schematic structural diagram of a circuit to be detected provided in embodiment 1 of the present invention;
fig. 4 is a schematic structural diagram of a charging current measuring circuit provided in embodiment 1 of the present invention;
fig. 5 is a schematic circuit diagram of a test circuit based on a charging chip according to embodiment 1 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiment of the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or quantity or location.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Example 1
The embodiment provides a test circuit based on a charging chip. Fig. 1 is a schematic structural diagram of a test circuit based on a charging chip according to this embodiment, and as shown in fig. 1, the test circuit 100 includes: the device comprises an analog battery circuit 10, a circuit to be detected 20, a charging chip 30 and a charging current measuring circuit 40; the analog battery circuit 10 at least includes: the power supply system comprises a power supply port 101, a simulated battery internal resistance 102 and a first output port 103, wherein the power supply port 101 is electrically connected with a power supply, the simulated battery internal resistance 102 is connected between the first output port 103 and a ground end GND of the power supply, and the first output port 103 is electrically connected with the power supply port 101; the circuit to be tested 20 at least comprises a second input port 201, a second output port 202 and a resistor to be tested 203 connected between the second input port 201 and the second output port 202; the second input port 201 is electrically connected to the first output port 103; the charging chip 30 is connected between the second output port 202 and the ground of the power supply to charge the analog battery circuit 10, and when the charging chip 30 charges the analog battery circuit 10, a current flows through the resistor 203 to be tested; the charging current measuring circuit 40 comprises a first detection port 401, a second detection port 402 and a voltage measurement output port 403, wherein the first detection port 401 and the second detection port 402 are electrically connected to two ends of the resistor 203 to be measured; the voltage measurement output port 403 outputs a voltage measurement value obtained from the current flowing through the resistor 203 to be measured.
As shown in fig. 1, the charging chip 30 is electrically connected to the resistor 203 to be measured, the analog battery internal resistance 102, and the ground GND of the power supply to form a loop. When the charging chip 30 detects that the voltage value of the analog battery circuit 10 is smaller than the preset value, the charging mode is turned on, and the current flows from the second output port 202 through the resistor 203 to be tested, the first output port 103 and the analog battery internal resistance 102, and finally flows into the ground terminal GND. At this time, a current flows through the resistor 203 to be tested, the charging current measuring circuit 40 obtains an output voltage measurement value by detecting the current of the circuit 203 to be tested, and whether the charging chip is a qualified chip can be tested by detecting whether the voltage measurement value conforms to a voltage range within which the charging chip normally works when charging the internal battery of the product.
Therefore, the embodiment of the utility model provides a based on test circuit of charging chip through the voltage measurement value of charging current measuring circuit output, can monitor whether charging chip is in normal operating condition to and the charging chip that the discovery has a problem in time.
As an optional implementation manner of the embodiment of the present invention, as shown in fig. 2, the analog battery circuit 10 further includes: a first switching circuit 104 and a first control port 105; wherein: and a first switch circuit 104 connected between the power supply port 101 and the first output port 103, and configured to open or close a path between the power supply port and the first output port under control of an output signal of the first control port.
In this alternative embodiment, as shown in fig. 2, the first switching circuit 104 includes: a first switching unit 1041, a second switching unit 1042, a first port S1, a second port S2, a third port S3, and a fourth port S4; the first port S1 is electrically connected to the power supply port 101, the second port S2 is electrically connected to the first output port 103, the third port S3 is electrically connected to the ground of the power supply source, the fourth port S4 is electrically connected to the first control port 105, and the path from the first port S1 to the second port S2 is opened or closed under the control of the output signal of the first control port 105. The first switch unit 1041 is connected to the first port S1, the second port S2 and the second switch unit 1042, respectively, the second switch unit 1042 is connected to the third port S3, the fourth port S4 and the first switch unit 1041, respectively, and when the first switch unit 1041 and the second switch unit 1042 are both turned on under the control of the output signal of the first control port 105, the path between the first port S1 and the second port S2 is turned on; when the first switch unit 1041 and the second switch unit 1042 are both turned off under the control of the output signal of the first control port 105, the path between the first port S1 and the second port S2 is disconnected.
As an optional manner, the first switch circuit 104 may further include, as shown in fig. 5: the circuit comprises a first PMOS tube Q1, a first NMOS tube Q2, a first resistor R1, a second resistor R2 and a third resistor R3. Refer to the following detailed description of the circuit schematic (fig. 5) of the charging chip based test circuit 100.
As an optional implementation manner of the embodiment of the present invention, as shown in fig. 2, the analog battery circuit 10 further includes: a unidirectional conducting circuit 106 connected between the first switching circuit 104 and the first output port 103; in operation, current flows from the first switch circuit 104 through the unidirectional conducting circuit 106 and to the first output port 103, and cannot flow from the first output port 103 back to the first switch circuit 104. Optionally, the unidirectional conducting circuit 106 may be a rectifying diode D1, the rectifying diode D1 rectifies unidirectionally, the reverse connection end of the unidirectional conducting circuit is electrically connected to the first output port 103, the forward connection end of the unidirectional conducting circuit is electrically connected to the first switch circuit 104, the unidirectional conducting circuit 106 may prevent current from flowing from the charging chip 30 to the first switch circuit when the charging chip 30 charges the analog battery circuit 10, and other devices in the test circuit may not be burned when the first switch circuit is turned on.
As an optional implementation manner of the embodiment of the present invention, as shown in fig. 2, the analog battery circuit 10 further includes: a filtering component 107; the filtering component is connected in parallel with the internal resistance of the analog battery and is connected between the first output port and the ground end of the power supply. As an alternative, the filtering component 107 may be a capacitor or other component capable of isolating direct current, which is not limited in this embodiment. Through this filtering subassembly can keep apart direct current signal, can be with remaining interchange in the power of power supply port input and harmonic composition return circuit ground, filtering promptly to can the energy storage promote direct current voltage's effective value.
As an optional implementation manner of the embodiment of the present invention, as shown in fig. 3, the circuit 20 to be detected further includes: a second switching circuit 204 and a second control port 205; wherein: and a second switch circuit 204 connected between the resistor 203 to be tested and the second output port 202, and disconnecting or connecting a path between the resistor 203 to be tested and the second output port 202 under the control of an output signal of the second control port 205.
In this alternative embodiment, as shown in fig. 3, the second switching circuit 204 includes: a third switching unit 2041, a fourth switching unit 2042, a fifth port T1, a sixth port T2, a seventh port T3, and an eighth port T4;
the fifth port T1 is electrically connected to one end of the resistor 203 to be tested, which is connected to the second output port 202, the sixth port T2 is electrically connected to the second output port 202, the seventh port T3 is electrically connected to the ground of the power supply, the eighth port T4 is electrically connected to the second control port 205, and the path between the fifth port T1 and the sixth port T2 is disconnected or connected under the control of the output signal of the second control port 205. The third switching unit 2041 is connected to the fifth port T1, the sixth port T2 and the fourth switching unit 2042, respectively, the fourth switching unit 2042 is connected to the seventh port T3, the eighth port T4 and the third switching unit 2041, respectively, and when the third switching unit 2041 and the fourth switching unit 2042 are both turned on under the control of the output signal of the second control port 205, a path between the fifth port T1 and the sixth port T2 is turned on; when both the third and fourth switching units 2041 and 2042 are turned off under the control of the output signal of the second control port 205, a path between the fifth port T1 and the sixth port T2 is opened.
As an optional manner, the second switch circuit 204 may also include, as shown in fig. 5: a second PMOS transistor Q3, a second NMOS transistor Q4, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6. Refer to the following detailed description of the circuit schematic (fig. 5) of the charging chip based test circuit 100.
As an optional implementation manner of the embodiment of the present invention, as shown in fig. 4, the charging current measuring circuit 40 further includes: a high-side current sense amplifier 404, a first gain adjustment resistor 405, and a second gain adjustment resistor 406; the high-side current sense amplifier 404 includes a first current sense access terminal RS +, a second current sense access terminal RS-, a measurement output terminal OUT, a feedback terminal FB, and a reference terminal REF, wherein:
the first current detection access terminal RS + of the high-side current detection amplifier is electrically connected to the first detection port 401, the second current detection access terminal RS-of the high-side current detection amplifier is electrically connected to the second detection port 402, the measurement output terminal OUT of the high-side current detection amplifier is electrically connected to the voltage measurement output port 403, the first gain adjustment resistor 405 is electrically connected between the measurement output terminal OUT and the feedback terminal FB, the second gain adjustment resistor 406 is electrically connected between the feedback terminal FB and the reference terminal REF, and the reference terminal REF is electrically connected to the ground of the power supply.
In this embodiment, the high-side current detection amplifier may optionally use a MAX9922 chip. The voltage measurement is obtained by the following equation:wherein, VOUTAs a voltage measurement value, IsampleFor the current flowing through the resistor to be measured, R22To the resistance to be measured, Ra1For the first gain adjustment resistor, Ra2A resistance is adjusted for the second gain. The amplification factor of the output voltage is determined by the first gain adjusting resistor and the second gain adjusting resistor
Hereinafter, the charging chip-based test circuit 100 provided by the present invention is illustrated, and fig. 5 is a schematic circuit diagram of an optional charging chip-based test circuit 100 according to an embodiment of the present invention. In this alternative circuit schematic:
the analog battery circuit 10 includes: the power supply circuit comprises a power supply port VBAT-OUT, a first control port CHAR-TEST _ EN, a first PMOS tube Q1, a first NMOS tube Q2, a first resistor R1, a second resistor R2, a third resistor R3, a rectifier diode D1, an analog battery internal resistance R11 and a first capacitor C1; the first switch circuit 104 is composed of a first PMOS transistor Q1, a first NMOS transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3, the first PMOS transistor Q1 is a first switch unit 1041, and the first NMOS transistor Q2 is a second switch unit 1042. Wherein: the power supply port VBAT-OUT is electrically connected to a power supply source; a source electrode (S) of the first PMOS tube Q1 is electrically connected with the power supply port, a drain electrode (D) of the first PMOS tube Q1 is electrically connected with a forward access end (1) of the rectifying diode D1, and a grid electrode (G) of the first PMOS tube Q1 is electrically connected with a drain electrode (D) of the first NMOS tube Q2; a source (S) of the first NMOS transistor Q2 is electrically connected to a ground GND of the power supply, a gate (G) of the first NMOS transistor Q2 is electrically connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the first control port CHAR-TEST _ EN, and the first PMOS transistor Q1 is turned on or off under the control of a control signal output from the first control port CHAR-TEST _ EN; the first resistor R1 is electrically connected between the power supply port VBAT-OUT and the grid (G) of the first PMOS tube; the second resistor R2 is electrically connected between the gate (G) of the first NMOS transistor Q2 and the ground GND of the power supply; the reverse access end (2) of the rectifier diode D1 is electrically connected to one end of the resistor R22 to be tested; the analog battery internal resistance R11 is connected with the first capacitor C1 in parallel and is electrically connected between the reverse access end (2) of the rectifier diode D1 and the ground end GND of the power supply; when the charging chip to be tested needs to be tested, the analog battery circuit 10 needs to work, so when the control signal is at a high level, the first NMOS transistor Q2 is conducted with the first PMOS transistor Q1, the first switch circuit 104 is conducted, and the analog battery circuit 10 works normally. When the control signal is at a low level, the first NMOS transistor Q2 and the first PMOS transistor Q1 are turned off, the first switch circuit 104 is turned off, and the analog battery circuit 10 stops working. When the test is not needed, the analog battery circuit can be controlled to stop working through the control signal, so that the loss of the circuit can be reduced.
The circuit 20 to be tested comprises: the device comprises a second control port CHAR-TEST _ EN, a resistor R22 to be tested, a second PMOS tube Q3, a second NMOS tube Q4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a second output port VBAT-OUT 1; the second switch circuit 204 is formed by a second PMOS transistor Q3, a second NMOS transistor Q4, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6, the second PMOS transistor Q3 is a third switch unit 2041, and the second NMOS transistor Q4 is a fourth switch unit 2042. Wherein: the reverse access end (2) of the rectifier diode D1 is electrically connected to one end of the resistor R22 to be tested; the other end of the resistor R22 to be tested is electrically connected with the drain (D) of a second PMOS tube Q3, the source (S) of the second PMOS tube Q3 is electrically connected with a second output port VBAT-OUT1, and the gate (G) of the second PMOS tube Q3 is electrically connected with the drain (D) of a second NMOS tube Q4; a source (S) of the second NMOS transistor Q4 is electrically connected with a ground end GND of the power supply, a gate (G) of the second NMOS transistor Q4 is electrically connected with one end of a sixth resistor R6, the other end of the sixth resistor R6 is connected to a second control port CHAR-TEST _ EN, and a second PMOS transistor is switched on or off under the control of a control signal output by the second control port CHAR-TEST _ EN; the fourth resistor R4 is electrically connected between the gate (G) of the second NMOS transistor Q4 and the ground GND of the power supply; the fifth resistor R5 is connected between the gate (G) of the second PMOS transistor Q3 and the second output port VBAT-OUT 1. Only when the charging chip to be tested needs to be tested, the circuit to be tested 20 needs to work, so when the control signal output by the second control port CHAR-TEST _ EN is at a high level, the second NMOS transistor Q4 is conducted with the second PMOS transistor Q3, the second switch circuit 204 is conducted, and the circuit to be tested 20 works normally. When the control signal is at a low level, the second NMOS transistor Q4 and the second PMOS transistor Q3 are turned off, the second switch circuit 204 is turned off, and the circuit 20 to be detected stops working. When the test is not needed, the circuit to be tested 20 can be controlled to stop working through the control signal, so that the loss of the circuit can be reduced. It will be appreciated that the first output port 103 and the second input port 201, which are not shown in the circuit schematic, may be a wire or a pad in the actual test circuit, and are not necessarily an actual hardware input/output interface.
The charging chip 30 is connected between the second output port VBAT-OUT1 and the ground GND of the power supply, and forms a loop with the resistor R22 to be tested, the analog battery internal resistance R11 and the ground GND of the power supply. When the charging chip 30 detects that the voltage value of the analog battery circuit 10 is smaller than the preset value, the charging mode is turned on, and the current flows from VBAT-OUT1 through R22, R11 and finally flows into the ground GND. At this time, a current flows through the resistor R22 to be tested, the charging current measuring circuit 40 obtains an output voltage measurement value by detecting the current of the circuit R22 to be tested, and whether the charging chip is a qualified chip can be tested by detecting whether the voltage measurement value conforms to the voltage range of the charging chip for charging the internal battery of the product to normally work.
The charging current measuring chip adopts a MAX9922 chip, the detection access ends RS + and RS-of the charging current measuring chip are connected to two ends of the resistor R22 to be measured, the output end OUT of the charging current measuring chip outputs a voltage measured value, and the voltage measured value is obtained according to the current flowing through the resistor to be measured. First gain adjustment resistor Ra1A second gain adjusting resistor R electrically connected between the output terminal OUT of the charging current measuring chip and the feedback terminal FB of the charging current measuring chipa2The reference terminal REF is electrically connected between the feedback terminal FB of the charging current measuring chip and the reference terminal REF of the charging current measuring chip, and the reference terminal REF is electrically connected with the ground terminal GND of the power supply. A second capacitor C2 and a first gain adjusting resistor Ra1And the parallel connection is connected between the output end OUT of the charging current measuring chip and the feedback end FB of the charging current measuring chip, and plays the roles of isolating direct current signals and returning residual alternating current and harmonic components in a power supply input by the power supply port VBAT-OUT to the ground.
In the optional circuit schematic diagram, during normal operation, a control terminal CHAR-TEST _ EN outputs a high level to turn on Q1, Q2, Q3 and Q4, when the charging chip detects that the analog battery circuit needs to be charged, the charging chip charges the analog battery circuit, a current flows through a circuit to be tested R22, and the measuring chip outputs a voltage measurement value according to the current flowing through R22, so that technicians can analyze whether the charging chip operates in a normal charging voltage range. When the operation is not needed, the control terminal CHAR-TEST _ EN outputs low level, so that Q1, Q2, Q3 and Q4 are all turned off, and the voltage measurement value output by the measurement chip is zero.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the principles and spirit of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A test circuit based on a charging chip is characterized by comprising: the device comprises an analog battery circuit, a circuit to be detected, a charging chip and a charging current measuring circuit; wherein,
the analog battery circuit includes at least: the power supply system comprises a power supply port, a simulated battery internal resistance and a first output port, wherein the power supply port is electrically connected with a power supply, the simulated battery internal resistance is connected between the first output port and an electrical ground end of the power supply, and the first output port is electrically connected with the power supply port;
the circuit to be detected at least comprises a second input port, a second output port and a resistor to be detected, wherein the resistor to be detected is connected between the second input port and the second output port; the second input port is electrically connected with the first output port;
the charging chip is connected between the second output port and the ground end of the power supply;
the charging current measuring circuit comprises a first detection port, a second detection port and a voltage measurement output port, and the first detection port and the second detection port are electrically connected to two ends of the resistor to be measured; the voltage measurement output port outputs a voltage measurement value.
2. The test circuit of claim 1, wherein the analog battery circuit further comprises: a first switching circuit and a first control port; wherein:
the first switch circuit is electrically connected between the power supply port and the first output port, and is used for disconnecting or conducting a path between the power supply port and the first output port under the control of an output signal of the first control port.
3. The test circuit of claim 2,
the first switching circuit includes: the switch comprises a first switch unit, a second switch unit, a first port, a second port, a third port and a fourth port;
the first port is electrically connected with the power supply port, the second port is electrically connected with the first output port, the third port is electrically connected with the ground end of the power supply, and the fourth port is electrically connected with the first control port;
the first switch unit is respectively connected with the first port, the second port and the second switch unit, the second switch unit is respectively connected with the third port, the fourth port and the first switch unit, and the first switch unit is used for conducting a path between the first port and the second port when the first switch unit and the second switch unit are both conducted under the control of an output signal of the first control port; when the first switch unit and the second switch unit are both turned off under the control of the output signal of the first control port, the path between the first port and the second port is disconnected.
4. The test circuit of claim 2 or 3, wherein the analog battery circuit further comprises: a unidirectional conducting circuit connected between the first switching circuit and the first output port; in operation, current flows from the first switching circuit through the unidirectional conducting circuit and to the first output port, and cannot flow from the first output port back to the first switching circuit.
5. The test circuit of claim 4, wherein the analog battery circuit further comprises: a filtering component; the filtering component is connected with the internal resistance of the analog battery in parallel and is connected between the first output port and the ground end of the power supply.
6. The test circuit according to any of claims 1 to 3, 5, wherein the circuit under test further comprises: a second switching circuit and a second control port; wherein:
the second switch circuit is connected between the resistor to be tested and the second output port, and is used for switching off or switching on a path between the resistor to be tested and the second output port under the control of an output signal of the second control port.
7. The test circuit of claim 6,
the second switching circuit includes: a third switching unit, a fourth switching unit, a fifth port, a sixth port, a seventh port, and an eighth port;
the fifth port is electrically connected to one end of the resistor to be tested, which is connected with the second output port, the sixth port is electrically connected with the second output port, the seventh port is electrically connected with the ground end of the power supply, and the eighth port is electrically connected with the second control port;
the third switching unit is respectively connected with the fifth port, the sixth port and the fourth switching unit, and the fourth switching unit is respectively connected with the seventh port, the eighth port and the third switching unit, so that when the third switching unit and the fourth switching unit are both turned on under the control of the output signal of the second control port, a path between the fifth port and the sixth port is turned on; when the third switch unit and the fourth switch unit are both turned off under the control of the output signal of the second control port, a path between the fifth port and the sixth port is disconnected.
8. The test circuit of claim 7, wherein the charge current measurement circuit further comprises: the high-side current detection amplifier, the first gain adjusting resistor and the second gain adjusting resistor; the high-side current detection amplifier comprises a first current detection access end, a second current detection access end, a measurement output end, a feedback end and a reference end, wherein:
a first current detection access end of the high-side current detection amplifier is electrically connected to the first detection port, a second current detection access end of the high-side current detection amplifier is electrically connected to the second detection port, a measurement output end of the high-side current detection amplifier is electrically connected to the voltage measurement output port, the first gain adjustment resistor is electrically connected between the measurement output end and the feedback end, the second gain adjustment resistor is electrically connected between the feedback end and the reference end, and the reference end is electrically connected to a ground end of the power supply.
9. The test circuit of claim 8,
wherein, VOUTIs the voltage measurement value IsampleFor the current flowing through the resistor to be measured, R22Is the resistance to be measured, Ra1For the first gain adjustment resistor, Ra2Adjusting a resistance for the second gain.
10. The test circuit according to claim 8 or 9,
the high-side current detection amplifier adopts a MAX9922 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821192436.5U CN208654281U (en) | 2018-07-25 | 2018-07-25 | A kind of test circuit based on charging chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821192436.5U CN208654281U (en) | 2018-07-25 | 2018-07-25 | A kind of test circuit based on charging chip |
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| CN208654281U true CN208654281U (en) | 2019-03-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201821192436.5U Withdrawn - After Issue CN208654281U (en) | 2018-07-25 | 2018-07-25 | A kind of test circuit based on charging chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031098A (en) * | 2018-07-25 | 2018-12-18 | 天地融电子（天津）有限公司 | A kind of test circuit based on charging chip |
| CN112147484A (en) * | 2020-08-28 | 2020-12-29 | 珠海市一微半导体有限公司 | Test system based on charging chip and charging test system |
-
2018
- 2018-07-25 CN CN201821192436.5U patent/CN208654281U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031098A (en) * | 2018-07-25 | 2018-12-18 | 天地融电子（天津）有限公司 | A kind of test circuit based on charging chip |
| CN109031098B (en) * | 2018-07-25 | 2024-07-05 | 天地融电子（天津）有限公司 | Test circuit based on charging chip |
| CN112147484A (en) * | 2020-08-28 | 2020-12-29 | 珠海市一微半导体有限公司 | Test system based on charging chip and charging test system |
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