CN204795120U - Split type extensible network message storage device - Google Patents
Split type extensible network message storage device Download PDFInfo
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- CN204795120U CN204795120U CN201520354590.8U CN201520354590U CN204795120U CN 204795120 U CN204795120 U CN 204795120U CN 201520354590 U CN201520354590 U CN 201520354590U CN 204795120 U CN204795120 U CN 204795120U
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Abstract
The utility model discloses a split type extensible network message storage device, it belongs to message storage device field, and it includes main message memory cell, main message memory cell includes CPU treater, FPGA chip, PCI -E bus interface chip and PCI -E bus port, through inside PCI -E bus connection between CPU treater and the FPGA chip, be equipped with on the FPGA chip from taking the net gape, be connected from taking net gape and the switch in the outside intelligent transformer substation, the PORT COM both way junction of CPU treater and PCI -E bus interface chip, be equipped with a plurality of PCI -E bus port on the PCI -E bus interface chip, the PCI -E bus port is connected through pluggable outside PCI -E bus and outside expansion equipment. The utility model has the advantages that real -time, reliability and stability are good.
Description
Technical field
The utility model relates to a kind of network message storage device, is specifically related to a kind of split type extendible network message storage device, belongs to packet storage apparatus field.
Background technology
In transformer station, network message storage device is by all communication message of each layer of automation system network in online record station, the network operation situation of real time monitoring automated system also to be reported to the police to abnormal in time, and off-line/on-line analysis can be carried out according to recorded system communication message, help the hidden danger that technical staff's seeking system exists, analytical system exception and error reason, instruct navigation system hidden danger and fault.
Along with the application of the network equipment a large amount of in automated system in current Intelligent transformer station and conventional substation; the record analysis of network message is had higher requirement; and legacy network packet storage device is often due to the restriction of hardware design structure, often there will be the problem such as packet loss, deadlock when large scale network message storm.Therefore be badly in need of new design one and can improve packet storage robustness, the hardware configuration with stronger extensibility solves these problems.
Utility model content
Technical problem to be solved in the utility model there is provided a kind of distributed, split type extendible network message storage device that modularization, real-time, reliability and stability are good.
The utility model adopts following technical scheme:
A kind of split type extendible network message storage device, it comprises primary message memory cell; Described primary message memory cell comprises CPU processor, fpga chip, PCI-E Bus Interface Chip and PCI-E bus port; Connected by inner PCI-E bus between described CPU processor and fpga chip, described fpga chip is provided with and carries network interface, described in carry network interface and be connected with the switch in external smart transformer station; The PORT COM of described CPU processor and PCI-E Bus Interface Chip is bi-directionally connected, described PCI-E Bus Interface Chip is provided with several PCI-E bus ports, and described PCI-E bus port is connected with outside expansion equipment by pluggable exterior PC I-E bus.
Further, the model of described PCI-E Bus Interface Chip is CH367.
Further, the utility model also comprises sub-packet storage unit, and described sub-packet storage unit comprises the external network port of Ethernet PCI-E server adapter and some expansions; Described Ethernet PCI-E server adapter is provided with the PCI-E bus port that connect corresponding to PCI-E bus port in primary message memory cell; PCI-E bus port on described sub-packet storage unit is connected with the bus end of Ethernet PCI-E server adapter, and described external network port is connected with the network interface end of Ethernet PCI-E server adapter.
Further, the model of described Ethernet PCI-E server adapter is BNE1G44HF-SX.
Further, the expansion equipment of described outside comprises sub-packet storage unit and other memory devices.
Further, the point-to-point full duplex high bandwidth transmission of data acquisition serial of described PCI-E bus, each FPGA unshared bandwidth.
Further, described CPU processor adopts Embedded high speed CPU chip, and described fpga chip adopts high performance fpga chip.
Further, described CPU processor adopts advanced COM-Express embedded type CPU chip, can provide perfect high performance solution for Embedded Application, supports the various signal of PCI-E bus high efficiency of transmission simultaneously.
The beneficial effects of the utility model are:
The utility model adopts distributed, Modular Structure Design, packet storage robustness can be improved, extensibility is good, adopt large-scale F PGA as front end data process chip, greatly reduce the load of CPU processor, reach the low-power consumption of CPU processor and fan-free application, improve the real-time of packet storage device simultaneously, also improve the reliability and stability of its long-time running, the requirement of all kinds of transformer station to the information high-throughput of packet storage device can be met; Expand by adopting PCI-E Bus Interface Chip, PCI-E bus can not only the various signal of high efficiency of transmission, and multiple pluggable PCI-E bus port is set, and can the outside expansion equipment such as multiple external message receiver modules of subsequent expansion, improve follow-up extensibility.High performance fpga chip is as front end communication stipulations process chip, and the PCI-E bus data interface built by it is up-to-date bus and interface standard, belongs to the point-to-point full duplex high bandwidth transmission of serial, each fpga chip unshared bandwidth.
The utility model is by the hardware configuration of modularization, Distributed Design network message storage device, originally the large scale network storm data loss problem being difficult to realize and subsequent expansion difficult problem are solved, the utility model uses in mass field Practical Project, has good effect.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Wherein, 1CPU processor, 2 inner PCI-E buses, 3-1PCI-E Bus Interface Chip, 3-2PCI-E bus port, 4 exterior PC I-E buses, 5FPGA chip, 6 sub-packet storage unit, 7 carry network interface, 8 Ethernet PCI-E server adapters, 9 external network ports.
Embodiment
Below in conjunction with Fig. 1, the utility model is described in further detail.
Embodiment 1, with reference to Fig. 1: it comprises primary message memory cell; Described primary message memory cell comprises CPU processor 1, fpga chip 5, PCI-E Bus Interface Chip 3-1 and PCI-E bus port 3-2; Connected by inner PCI-E bus 2 between described CPU processor 1 and fpga chip 5, described fpga chip 5 is provided with and carries network interface 7, described in carry network interface 7 and be connected with the switch in outside Intelligent transformer station; Described CPU processor 1 is bi-directionally connected with the PORT COM of PCI-E Bus Interface Chip 3-1, described PCI-E Bus Interface Chip 3-1 is provided with several PCI-E bus ports 3-2, and described PCI-E bus port 3-2 is connected with outside expansion equipment by pluggable exterior PC I-E bus 4.
Further, the model of described PCI-E Bus Interface Chip 3-1 is CH367.
Further, the utility model also comprises sub-packet storage unit 6, and described sub-packet storage unit 6 comprises the external network port 9 of Ethernet PCI-E server adapter 8 and some expansions; Described Ethernet PCI-E server adapter 8 is provided with the PCI-E bus port 3-2 that connect corresponding to PCI-E bus port 3-2 in primary message memory cell; PCI-E bus port 3-2 on described sub-packet storage unit 6 is connected with the bus end of Ethernet PCI-E server adapter 8, and described external network port 9 is connected with the network interface end of Ethernet PCI-E server adapter 8.
Further, the model of described Ethernet PCI-E server adapter 8 is BNE1G44HF-SX.
Further, the expansion equipment of described outside comprises sub-packet storage unit 6 and other memory devices.
Further, the point-to-point full duplex high bandwidth transmission of data acquisition serial of described PCI-E bus, each FPGA unshared bandwidth.
Further, described CPU processor adopts Embedded high speed CPU chip, and described fpga chip adopts high performance fpga chip.
Further, described CPU processor adopts advanced COM-Express embedded type CPU chip, can provide perfect high performance solution for Embedded Application, supports the various signal of PCI-E bus high efficiency of transmission simultaneously.
Operation principle and the process of the present embodiment are as follows:
As shown in Figure 1, described CPU processor 1, inner PCI-E bus 2, PCI-E Bus Interface Chip 3, pluggable exterior PC I-E bus 4, fpga chip 5 and carry the indoor design that network interface 7 is present networks packet storage device, i.e. primary message memory cell, when apparatus design and apparatus integration design.
Described Ethernet PCI-E server adapter 8, external network port 9 are that external distributed extension storage unit uses, i.e. sub-packet storage unit 6.Described fpga chip 5 carries out high speed communication by inner PCI-E bus 2 with CPU processor 1, can ensure the high speed processing of message on the one hand, can realize the lossless storage of message on the other hand.Fpga chip 5 is as built-in message process chip.Sub-packet storage unit 6 is as outside message process device.
In embodiment 1, described primary message memory cell arrangements 4 carries network interface 7 and directly can carry out packet storage, subsequent expansion or network interface inadequate time can be connected with sub-packet storage unit 6 by extending out PCI-E bus port 3-2, carry out subsequent expansion, in embodiment 1, each primary message memory cell can expand at most 4 sub-packet storage unit 6.
Every sub-packet storage unit 6 utilizes exterior PC I-E bus 4 to be connected with primary message memory cell by PCI-E bus port 3-2, and every sub-packet storage unit 6 carries 4 external network ports 9 and carry out message and receive storage simultaneously.
Under above-mentioned this structure, can ensure that the message high-speed lossless carrying network interface 7 stores on the one hand, the network interface that realizes that on the other hand can be convenient and reliable is expanded, and the scene simultaneously not affecting original packet storage function is run.
The above execution mode is only preferred embodiment of the present utility model, and is not the exhaustive of the feasible enforcement of the utility model.For persons skilled in the art, to any apparent change done by it under the prerequisite not deviating from the utility model principle and spirit, all should be contemplated as falling with within claims of the present utility model.
Claims (4)
1. a split type extendible network message storage device, is characterized in that: it comprises primary message memory cell; Described primary message memory cell comprises CPU processor (1), fpga chip (5), PCI-E Bus Interface Chip (3-1) and PCI-E bus port (3-2); Connected by inner PCI-E bus (2) between described CPU processor (1) and fpga chip (5), described fpga chip (5) is provided with and carries network interface (7), described in carry network interface (7) and be connected with the switch in the Intelligent transformer station of outside; Described CPU processor (1) is bi-directionally connected with the PORT COM of PCI-E Bus Interface Chip (3-1), described PCI-E Bus Interface Chip (3-1) is provided with several PCI-E bus ports (3-2), and described PCI-E bus port (3-2) is connected with outside expansion equipment by pluggable exterior PC I-E bus (4).
2. the split type extendible network message storage device of one according to claim 1, is characterized in that: the model of described PCI-E Bus Interface Chip (3-1) is CH367.
3. the split type extendible network message storage device of one according to claim 1, it is characterized in that: it also comprises sub-packet storage unit (6), described sub-packet storage unit (6) comprises the external network port (9) of Ethernet PCI-E server adapter (8) and some expansions; Described Ethernet PCI-E server adapter (8) is provided with the PCI-E bus port (3-2) that connect corresponding to PCI-E bus port (3-2) in primary message memory cell; PCI-E bus port (3-2) on described sub-packet storage unit (6) is connected with the bus end of Ethernet PCI-E server adapter (8), and described external network port (9) is connected with the network interface end of Ethernet PCI-E server adapter (8).
4. the split type extendible network message storage device of one according to claim 3, is characterized in that: the model of described Ethernet PCI-E server adapter (8) is BNE1G44HF-SX.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520354590.8U CN204795120U (en) | 2015-05-28 | 2015-05-28 | Split type extensible network message storage device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520354590.8U CN204795120U (en) | 2015-05-28 | 2015-05-28 | Split type extensible network message storage device |
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| CN204795120U true CN204795120U (en) | 2015-11-18 |
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| CN201520354590.8U Expired - Fee Related CN204795120U (en) | 2015-05-28 | 2015-05-28 | Split type extensible network message storage device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105490844A (en) * | 2015-12-05 | 2016-04-13 | 中国航空工业集团公司洛阳电光设备研究所 | PCIe port reconstruction method |
| CN107707492A (en) * | 2017-11-22 | 2018-02-16 | 杭州迪普科技股份有限公司 | A kind of method and device reported with downward message |
-
2015
- 2015-05-28 CN CN201520354590.8U patent/CN204795120U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105490844A (en) * | 2015-12-05 | 2016-04-13 | 中国航空工业集团公司洛阳电光设备研究所 | PCIe port reconstruction method |
| CN107707492A (en) * | 2017-11-22 | 2018-02-16 | 杭州迪普科技股份有限公司 | A kind of method and device reported with downward message |
| CN107707492B (en) * | 2017-11-22 | 2020-05-12 | 杭州迪普科技股份有限公司 | Method and device for reporting and issuing message |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151118 |