CN202513820U - Charge pump single-stage circuit and charge pump circuit - Google Patents
Charge pump single-stage circuit and charge pump circuit Download PDFInfo
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Abstract
The utility model discloses a charge pump single-stage circuit and a charge pump circuit, and defects that an existing Dickson charge pump is influenced by an NMOS threshold voltage and work efficiency is low are overcome. In the charge pump single-stage circuit, a first transmission unit comprises a first clock access terminal, a first input terminal used for accessing a first input signal and a first output terminal used for outputting a first output signal, a second transmission unit comprises a second clock access terminal, a second input terminal used for accessing a second input signal and a second output terminal used for outputting a second output signal, the first clock access terminal and the second clock access terminal are respectively accessed to one of two complementary clock signals, the first transmission unit is used for following an accessed clock signal and transmitting charge from the first input terminal to the first output terminal, and the second transmission unit is used for following an accessed clock signal and transmitting charge from the second input terminal to the second output terminal. The charge pump circuit comprises at least two grades of the above single-stage circuit. According to the utility model, a single stage voltage gain of a charge pump and efficiency of charge transmission are raised.
Description
Technical field
The utility model relates to the IC design field, relates in particular to a kind of charge pump single-level circuit and a kind of charge pump circuit.
Background technology
Fig. 1 is the sketch map of existing Dickson charge pump circuit.In charge pump circuit shown in Figure 1; Comprise the individual NMOS pipe of the x (x is an integer) that links to each other step by step; NMOS pipes at different levels all are serially connected with diode (being that grid and drain electrode link together), and wherein the drain electrode of first order NMOS pipe N1 inserts input voltage Vdd, and the drain electrode of second level NMOS pipe N2 connects the source electrode of first order NMOS pipe N1; The drain electrode of third level NMOS pipe N3 connects the source electrode of second level NMOS pipe N2; ..., the drain electrode of x level NMOS pipe Nx connects the source electrode of x-1 level NMOS pipe Nx-1, and source electrode is a voltage output end.The NMOS of x-1 level pipe before corresponding, correspondence has access to the pump electric capacity of x-1 level, and first termination of pump electric capacity wherein at different levels is gone into the source electrode of the NMOS pipe of corresponding progression, and the other end alternately inserts the first phase clock signal clka and the second phase clock signal clka '.The source electrode of x level (also claiming output stage) NMOS pipe Nx connects first end of output capacitance Cout, the second end ground connection of output capacitance Cout.Wherein, NMOS pipes at different levels all are charge transfer pipes, and being cascaded forms a charge transfer path; The first phase clock signal clka and the second phase clock signal clka ' are as shown in Figure 2 two complementary clocks mutually.Under the effect of two phase complementary clocks (the first phase clock signal clka and the second phase clock signal clka '), charge pump circuit shown in Figure 1 can transfer to output voltage V out from Vdd step by step with electric charge, raises the output voltage of charge pump.
Fig. 3 is the sketch map with Dickson charge pump circuit of complementary function.It mainly is made up of two charge transfer path as shown in Figure 1; Article two, insert input voltage Vdd after the drain electrode of the first order NMOS of charge transfer path pipe links together; Afterbody (x level; Wherein x is an integer) the source electrode of the NMOS pipe back that links together connect first end of output capacitance Cout, and output voltage V out is provided.
Dickson charge pump circuit with complementary function shown in Figure 3 is compared with Dickson charge pump circuit shown in Figure 1; The main distinction is that two phase complementary clocks alternately are linked into the order difference on the charge transfer path; Particularly; That be linked into first order NMOS pipe N1 in first transmission path is the first phase clock signal clka, and that be linked into first order NMOS pipe N1 ' in second transmission path is the second phase clock signal clka '.
But in the Dickson charge pump, the grid and the drain electrode of NMOS diode link together; The NMOS pipe is operated in the saturation region during the charge transfer; Make source voltage all the time than the low threshold voltage vt h of drain voltage, the electric charge of previous stage can not fully transfer to the back level like this, has reduced charge transfer efficiency; And operating voltage is low more, and the influence of threshold voltage vt h is just remarkable more.In addition, the progression of NMOS pipe is high more, and the voltage on its source electrode is just high more, and in the standard CMOS process of P-sub, the substrate ground connection of NMOS, then V
SB(source electrode of metal-oxide-semiconductor and the voltage difference between the substrate) increases, the influence of receptor effect, and threshold voltage vt h increases; This has further reduced the voltage gain of level behind the Dickson charge pump; And the progression of the pipe of the NMOS on the charge transfer path is many more, and the closer to output stage, one pass gain is just more little.More than these deficiencies, all reduced the operating efficiency of Dickson charge pump.
Therefore, traditional Dickson charge pump receive the NMOS threshold voltage to influence operating efficiency on the low side, and it receives the restriction of operating voltage and progression apparent in view, need improve.
The utility model content
The utility model technical problem to be solved be overcome that existing Dickson charge pump receives the NMOS threshold voltage influence operating efficiency defective on the low side.
In order to solve the problems of the technologies described above, the utility model provides a kind of charge pump single-level circuit, comprises first transmission unit and second transmission unit, wherein:
Said first transmission unit comprises the first clock incoming end, first input end and first output, and said first input end is used to insert first input signal, and said first output is used to export the first output signal;
Said second transmission unit comprises second clock incoming end, second input and second output, and said second input is used to insert second input signal, and said second output is used to export the second output signal;
Said first clock incoming end and second clock incoming end insert the wherein phase in the two phase complementary clock signals respectively; Said first transmission unit is used to follow the clock signal that is inserted electric charge is transferred to first output from said first input end, and said second transmission unit is used to follow the clock signal that is inserted electric charge is transferred to second output from said second input.
Preferably, said first transmission unit comprises first transmission circuit and comprises first output control circuit of four control ends; Wherein:
Said first transmission circuit comprises the said first clock incoming end, first input end and first output, also comprises the first input control end and first output control terminal;
First control end of said first output control circuit connects said first output, and second control end connects the said first clock incoming end, and the 3rd control end connects said first output control terminal;
The 4th control end of the said first input control end and first output control circuit connects said second transmission unit respectively, is used to follow the clock signal shutoff of said first clock incoming end access or open the said second transmission unit transmission charge.
Preferably, said first transmission circuit comprises the first transmission NMOS pipe Nt1, the first transmission PMOS pipe Pt1 and the first transmission capacitor C t1, wherein:
The drain electrode of the said first transmission NMOS pipe Nt1 is said first input end, and grid is the said first input control end, and source electrode connects the drain electrode of first end and the said first transmission PMOS pipe Pt1 of the said first transmission capacitor C t1;
Second end of the said first transmission capacitor C t1 is the said first clock incoming end;
The grid of the said first transmission PMOS pipe Pt1 is said first output control terminal, and source electrode and substrate link together, and are said first output.
Preferably, said first output control circuit comprises the first charging PMOS pipe Pc1 and the first control pmos system capacitor C p1, wherein:
Source electrode and the substrate of the said first charging PMOS pipe Pc1 link together, and are first control end of said first output control circuit, and grid is the 3rd control end of said first output control circuit, drains to be the 4th control end of said first output control circuit;
First end of the first control pmos system capacitor C p1 connects the drain electrode of the said first charging PMOS pipe Pc1, and second end is second control end of said first output control circuit.
Preferably, said second transmission unit comprises second transmission circuit and comprises second output control circuit of four control ends; Wherein:
Said second transmission circuit comprises said second clock incoming end, second input and second output, also comprises the second input control end and second output control terminal;
First control end of said second output control circuit connects said second output, and second control end connects the said first clock incoming end, and the 3rd control end connects said second output control terminal;
The 4th control end of the said second input control end and second output control circuit connects said first transmission unit respectively, is used to follow the clock signal shutoff of said second clock incoming end access or open the said first transmission unit transmission charge.
Preferably, said second transmission circuit comprises the second transmission NMOS pipe Nt1 ', the second transmission PMOS pipe Pt1 ' and the second transmission capacitor C t1 ', wherein:
The drain electrode of the said second transmission NMOS pipe Nt1 ' is said second input, and grid is the said second input control end, and source electrode connects the drain electrode of first end and the said second transmission PMOS pipe Pt1 ' of the said second transmission capacitor C t1 ';
Second end of the said second transmission capacitor C t1 ' is said second clock incoming end;
The grid of the said second transmission PMOS pipe Pt1 ' is said second output control terminal, and source electrode and substrate link together, and are said second output.
Preferably, said second output control circuit comprises the second charging PMOS pipe Pc1 ' and the second control pmos system capacitor C p1 ', wherein:
Source electrode and the substrate of the said second charging PMOS pipe Pc1 ' link together; First control end for said second output control circuit; Grid is the 3rd control end of said second output control circuit, drains to be the 4th control end of said second output control circuit;
First end of the second control pmos system capacitor C p1 ' connects the drain electrode of the said second charging PMOS pipe Pc1 ', and second end is second control end of said second output control circuit.
The utility model has also passed through a kind of charge pump circuit, comprises the foregoing single-level circuit of two-stage at least, wherein:
The first input end of first order single-level circuit and second input link together, and are the input of said charge pump circuit; First output and second output of afterbody single-level circuit link together, and are the output of said charge pump circuit, and through output capacitance ground connection;
The progression x of said charge pump circuit was greater than 2 o'clock, and the first input end of i level single-level circuit connects first output of i-1 level single-level circuit, and second input connects second output of i-1 level single-level circuit; Wherein, i is more than or equal to 2 smaller or equal to x-1, and x level single-level circuit is said afterbody single-level circuit;
The clock signal that first transmission unit of the single-level circuit of adjacent two-stage inserts is complementary.
Compared with prior art; The embodiment of the utility model has effectively eliminated the influence that present Dickson charge pump receives NMOS pipe threshold voltage; And reduced the conducting resistance of switching tube, thereby the single electrode voltage gain of charge pump and the efficient of charge transfer have been significantly improved.The embodiment of the utility model is more suitable for being operated in (1.2V even lower) under the low input than existing Dickson charge pump.
Description of drawings
Fig. 1 is the sketch map of existing Dickson charge pump circuit.
Fig. 2 is two phase complementary clock waveform sketch mapes.
Fig. 3 is the sketch map with Dickson charge pump circuit of complementary function.
Fig. 4 is a kind of charge pump single-level circuit that the utility model embodiment provides.
Fig. 5 is the structural representation of a kind of charge pump circuit of providing of the utility model embodiment.
Embodiment
Below will combine accompanying drawing and embodiment to specify the execution mode of the utility model, how the application technology means solve technical problem to the utility model whereby, and the implementation procedure of reaching technique effect can make much of and implement according to this.
Fig. 4 is a kind of charge pump single-level circuit that the utility model embodiment provides.As shown in Figure 4, present embodiment charge pump single-level circuit comprises first transmission unit 410 and second transmission unit 420.
First transmission unit comprises the first clock incoming end, first input end and first output, and first input end is used to insert first input signal, and first output is used to export the first output signal;
Second transmission unit comprises second clock incoming end, second input and second output, and second input is used to insert second input signal, and second output is used to export the second output signal;
The first clock incoming end and second clock incoming end insert the wherein phase in the two phase complementary clock signals respectively; First transmission unit is used to follow the clock signal that is inserted electric charge is transferred to first output from first input end, and second transmission unit is used to follow the clock signal that is inserted electric charge is transferred to second output from second input.
Among the embodiment of the utility model, first transmission unit comprises first transmission circuit and comprises first output control circuit of four control ends; Wherein:
First transmission circuit comprises the first clock incoming end, first input end and first output, also comprises the first input control end and first output control terminal;
First control end of first output control circuit connects first output, and second control end connects the first clock incoming end, and the 3rd control end connects first output control terminal;
The 4th control end of the first input control end and first output control circuit connects second transmission unit respectively, is used to follow the clock signal shutoff of first clock incoming end access or open the second transmission unit transmission charge.
Among the embodiment of the utility model, first transmission circuit comprises the first transmission NMOS pipe Nt1, the first transmission PMOS pipe Pt1 and the first transmission capacitor C t1, wherein:
The drain electrode of the first transmission NMOS pipe Nt1 is a first input end, and grid is the first input control end, and source electrode connects the drain electrode of first end and the first transmission PMOS pipe Pt1 of the first transmission capacitor C t1;
Second end of the first transmission capacitor C t1 is the first clock incoming end;
The grid of the first transmission PMOS pipe Pt1 is first output control terminal, and source electrode and substrate link together, and are first output.
Among the embodiment of the utility model, first output control circuit comprises the first charging PMOS pipe Pc1 and the first control pmos system capacitor C p1, wherein:
Source electrode and the substrate of the first charging PMOS pipe Pc1 link together, and are first control end of first output control circuit, and grid is the 3rd control end of first output control circuit, and drain electrode is the 4th control end of first output control circuit;
First end of the first control pmos system capacitor C p1 connects the drain electrode of the first charging PMOS pipe Pc1, and second end is second control end of first output control circuit.
Among the embodiment of the utility model, second transmission unit comprises second transmission circuit and comprises second output control circuit of four control ends; Wherein:
Second transmission circuit comprises second clock incoming end, second input and second output, also comprises the second input control end and second output control terminal;
First control end of second output control circuit connects second output, and second control end connects the first clock incoming end, and the 3rd control end connects second output control terminal;
The 4th control end of the second input control end and second output control circuit connects first transmission unit respectively, is used to follow the clock signal shutoff of second clock incoming end access or open the first transmission unit transmission charge.
Among the embodiment of the utility model, second transmission circuit comprises the second transmission NMOS pipe Nt1 ', the second transmission PMOS pipe Pt1 ' and the second transmission capacitor C t1 ', wherein:
The drain electrode of the second transmission NMOS pipe Nt1 ' is second input, and grid is the second input control end, and source electrode connects the drain electrode of first end and the second transmission PMOS pipe Pt1 ' of the second transmission capacitor C t1 ';
Second end of the second transmission capacitor C t1 ' is the second clock incoming end;
The grid of the second transmission PMOS pipe Pt1 ' is second output control terminal, and source electrode and substrate link together, and are second output.
Among the embodiment of the utility model, second output control circuit comprises the second charging PMOS pipe Pc1 ' and the second control pmos system capacitor C p1 ', wherein:
Source electrode and the substrate of the second charging PMOS pipe Pc1 ' link together, and are first control end of second output control circuit, and grid is the 3rd control end of second output control circuit, and drain electrode is the 4th control end of second output control circuit;
First end of the second control pmos system capacitor C p1 ' connects the drain electrode of the second charging PMOS pipe Pc1 ', and second end is second control end of second output control circuit.
As shown in Figure 4; Among the embodiment of the utility model, first transmission unit 410 comprises the first transmission NMOS pipe Nt1 (N type metal-oxide-semiconductor), the first charging PMOS pipe Pc1 (P type metal-oxide-semiconductor), the first transmission PMOS pipe Pt1 (P type metal-oxide-semiconductor), the first control pmos system capacitor C p1 and the first transmission capacitor C t1.
In first transmission unit 410, the drain electrode of the first transmission NMOS pipe Nt1 is a first input end, inserts the first input signal Vin, and source electrode connects the drain electrode of first end and the first transmission PMOS pipe Pt1 of the first transmission capacitor C t1.The grid of the first transmission PMOS pipe Pt1 connects the grid of the first charging PMOS pipe Pc1, and source electrode and substrate link together, and connects source electrode and the substrate of the first charging PMOS pipe Pc1, is first output, the output first output signal Vo1.The drain electrode of the first charging PMOS pipe Pc1 connects first end of the first control pmos system capacitor C p1.Second end of the first transmission capacitor C t1 and the first control pmos system capacitor C p1 links together, and inserts the first phase clock signal clka.
As shown in Figure 4; Among the embodiment of the utility model, second transmission unit 420 comprises the second transmission NMOS pipe Nt1 ' (N type metal-oxide-semiconductor), the second charging PMOS pipe Pc1 ' (P type metal-oxide-semiconductor), the second transmission PMOS pipe Pt1 ' (P type metal-oxide-semiconductor), the second control pmos system capacitor C p1 ' and the second transmission capacitor C t1 '.
In second transmission unit 420, the drain electrode of the second transmission NMOS pipe Nt1 ' is second input, inserts the second input signal Vin ', and source electrode connects the drain electrode of first end and the second transmission PMOS pipe Pt1 ' of the second transmission capacitor C t1 '.The grid of the second transmission PMOS pipe Pt1 ' connects the grid of the second charging PMOS pipe Pc1 ', and source electrode and substrate link together, and connects source electrode and the substrate of the second charging PMOS pipe Pc1 ', is second output, the output second output signal Vo1 '.The drain electrode of the second charging PMOS pipe Pc1 ' connects first end of the second control pmos system capacitor C p1 '.Second end of the second transmission capacitor C t1 ' and the second control pmos system capacitor C p1 ' links together, and inserts the second phase clock signal clka '.
And the grid of the transmission of first in first transmission unit 410 NMOS pipe Nt1 also connects the source electrode of the transmission of second in second transmission unit 420 NMOS pipe Nt1 ', first end of the second transmission capacitor C t1 ' and the drain electrode of the second transmission PMOS pipe Pt1 '.The grid of in second transmission unit 420 second transmission NMOS pipe Nt1 ' also connects the source electrode of the first transmission NMOS pipe Nt1, first end of the first transmission capacitor C t1 and the drain electrode of the first transmission PMOS pipe Pt1.
The grid of in first transmission unit 410 first transmission PMOS pipe Pt1 and the grid of the first charging PMOS pipe Pc1 also connect the drain electrode of the charging of second in second transmission unit 420 PMOS pipe Pc1 ' and first end of the second control pmos system capacitor C p1 '.The grid of in second transmission unit 420 second transmission PMOS pipe Pt1 ' and the grid of the second charging PMOS pipe Pc1 ' also connect the drain electrode of the charging of first in first transmission unit 410 PMOS pipe Pc1 and first end of the first control pmos system capacitor C p1.
Embodiment shown in Figure 4; The first control pmos system capacitor C p1 is the control capacitance of the second charging PMOS pipe Pc1 ' and the second transmission PMOS pipe Pt1 ', and the second control pmos system capacitor C p1 ' is the control capacitance of the first charging PMOS pipe Pc1 and the first transmission PMOS pipe Pt1.The first transmission NMOS pipe Nt1 and the second transmission NMOS pipe Nt1 ' are the NMOS pipes on the charge transfer path, and the first transmission PMOS pipe Pt1 and the second transmission PMOS pipe Pt1 ' are the PMOS pipes on the charge transfer path.The first charging PMOS pipe Pc1 is used to first control pmos system capacitor C p1 charging, and the second charging PMOS pipe Pc1 ' is used to the second control pmos system capacitor C p1 ' charging.The first transmission capacitor C t1 and the second transmission capacitor C t1 ' mainly are used for to the next stage transmission charge.
The first phase clock signal clka and the second phase clock signal clka ' are as shown in Figure 3 two complementary clock signals mutually; Can make at any one time; Among the first transmission NMOS pipe Nt1 (N type metal-oxide-semiconductor), the first transmission PMOS pipe Pt1, the second transmission NMOS pipe Nt1 ' and the second transmission PMOS pipe Pt1 ' two metal-oxide-semiconductors in running order (labor of stating after please refer to) are arranged all, improved the efficient of charge transfer in the charge pump single-level circuit.
Fig. 5 is a kind of charge pump circuit that the utility model embodiment provides.As shown in Figure 5; It comprises step by step link to each other multistage (two-stage or more than the two-stage) charge pump single-level circuit as shown in Figure 4; The numeral that identifies among figure charge pump single-level circuits at different levels are arranged in the progression (which level) of charge pump circuit; X is an integer, the quantity of expression charge pump single-level circuit, and the while is also represented the progression of charge pump circuit in the present embodiment.
As shown in Figure 5, the charge pump circuit of present embodiment, in first order charge pump single-level circuit, the first input end and second input link together, and as the input of whole charge pump circuit, insert input voltage Vdd.In x level (the x level is an afterbody) charge pump single-level circuit, first output and second output link together, and connect first end of output capacitance Cout, and as the output of whole charge pump circuit, output voltage V out are provided; The second end ground connection of output capacitance Cout.
At the progression x of charge pump circuit greater than 2 o'clock; Except that the charge pump single-level circuit of the first order and afterbody; In all the other charge pump single-level circuits at different levels, the first input end of i level single-level circuit connects first output of i-1 level, and second input connects second output of i-1 level; First output connects the first input end of i+1 level, and second output connects second input of i+1 level; Wherein, i is more than or equal to 2 and smaller or equal to the integer of x-1, x level single-level circuit is the afterbody single-level circuit.Connect first output of first order charge pump single-level circuit such as the first input end of second level charge pump single-level circuit, second input connects second output of first order charge pump single-level circuit; And for example the first input end of third level charge pump single-level circuit connects first output of second level charge pump single-level circuit, and second input connects second output of second level charge pump single-level circuit; Or the like, by that analogy, charge pump single-level circuits at different levels are serially connected, and form the charge pump circuit of present embodiment.
As shown in Figure 5, clock signal that first transmission unit of the single-level circuit of adjacent two-stage is inserted complementary (simultaneously, the clock signal that inserted of second transmission unit of the single-level circuit of adjacent two-stage is also complementary).First the replacing property of transmission unit ground in the single-level circuits at different levels inserts two phase complementary clock signals, and second transmission unit in the single-level circuits at different levels also alternately inserts to property this two phases complementary clock signal simultaneously.
Embodiment as shown in Figure 5; Total two charge transfer path up and down; Below in one first charge transfer path, electric charge is successively via power supply Vdd, the first order charge pump single-level circuit first transmission NMOS pipe Nt1, the first transmission capacitor C t1 and the first transmission PMOS pipe Pt1; The second level charge pump single-level circuit first transmission NMOS pipe Nt2, the first transmission capacitor C t2 and the first transmission PMOS pipe Pt2; ..., the x level charge pump single-level circuit first transmission NMOS pipe Ntx, the first transmission capacitor C tx and the first transmission PMOS pipe Ptx transfer to output at last.Above in one second charge transfer path transmission of electric charge corresponding with the transmission of electric charge in following one first charge transfer path; Successively via power supply Vdd; The first order charge pump single-level circuit second transmission NMOS pipe Nt1 ', the second transmission capacitor C t1 ' and the second transmission PMOS pipe Pt1 '; The second level charge pump single-level circuit second transmission NMOS pipe Nt2 ', the second transmission capacitor C t2 ' and the second transmission PMOS pipe Pt2 '; ..., the x level charge pump single-level circuit second transmission NMOS pipe Ntx ', the second transmission capacitor C tx ' and the second transmission PMOS pipe Ptx ' transfer to output at last.Article two, the operation principle of charge transfer path is identical, below elaborates.
Suppose that at first the first phase clock signal clka is low level (is 0 such as voltage magnitude) in the starting stage, the second phase clock signal clka ' is high level (is input voltage Vdd such as amplitude), and the voltage at all electric capacity two ends all is input voltage Vdd.In first order charge pump single-level circuit, gate source voltage Vgs＜cut-in voltage Vthn of the second transmission NMOS pipe Nt1 ', promptly it is operated in cut-off region, and input voltage Vdd can not charge to the second transmission capacitor C t1 '.The gate source voltage Vgs of in the first order charge pump single-level circuit the second transmission PMOS pipe Pt1 ' and the second charging PMOS pipe Pc1 ' is much larger than cut-in voltage Vthp; The gate source voltage Vgs of in the charge pump single-level circuit of the second level second transmission NMOS pipe Nt2 ' is also much larger than cut-in voltage Vthn; They all are operated in dark linear zone; Electric charge transfers to the transmission of second in the charge pump single-level circuit of second level capacitor C t2 ' by the drain electrode of the second transmission NMOS pipe Nt2 ' in the source electrode of the second transmission PMOS pipe Pt1 ' of second in first order charge pump single-level circuit transmission capacitor C t1 ' in first order single-level circuit and the second level single-level circuit, and (second in the first order charge pump single-level circuit transmits the capacitor C t1 ' and the second control pmos system capacitor C p1 ' this moment in other words; These three electric capacity of in the charge pump single-level circuit of the second level second transmission capacitor C t2 ' are shared electric charge, till their electromotive force of positive plate equates).
Meanwhile; On first charge transfer path; In the first order charge pump single-level circuit first transmission NMOS pipe Nt1 is operated in dark linear zone, and electric charge transfers to the first transmission capacitor C t1 by input (Vdd), until the voltage charging of the first transmission capacitor C t1 till the input voltage Vdd; In the first order charge pump single-level circuit the first transmission PMOS pipe Pt1 and the first charging PMOS pipe Pc1; In the charge pump single-level circuit of the second level first transmission NMOS pipe Nt2 all is operated in cut-off region, and electric charge can not be transferred on the transmission of first in the charge pump single-level circuit of the second level capacitor C t2 by the source electrode of the first transmission PMOS pipe Pt1 of the transmission of first in first order charge pump single-level circuit capacitor C t1 in first order single-level circuit and the drain electrode of the first transmission NMOS pipe Nt2 in the single-level circuit of the second level.
When the first phase clock signal clka is a high level by the low level upset; After the second phase clock signal clka ' is low level by the high level upset; In first order charge pump single-level circuit; The grid voltage of the second transmission NMOS pipe Nt1 ' increases, and it is operated in dark linear zone, and electric charge transfers to the second transmission capacitor C t1 ' by input (Vdd); The grid voltage of in the first order charge pump single-level circuit the second transmission PMOS pipe Pt1 ' and the second charging PMOS pipe Pc1 ' increases; Two pipe works are at cut-off region; The grid voltage of in the charge pump single-level circuit of the second level second transmission NMOS pipe Nt2 ' reduces; Also be operated in cut-off region, so electric charge can not transfer to the transmission of second in the charge pump single-level circuit of second level capacitor C t2 ' by the source electrode of the second transmission PMOS pipe Pt1 ' of the transmission of second in first order charge pump single-level circuit capacitor C t1 ' in first order single-level circuit and the drain electrode of the second transmission NMOS pipe Nt2 ' in the single-level circuit of the second level.
Meanwhile, on first charge transfer path, the transmission of first in first order charge pump single-level circuit NMOS pipe Nt1 is operated in cut-off region, and input voltage Vdd can not charge to the first transmission capacitor C t1; In the first order charge pump single-level circuit the first transmission PMOS pipe Pt1 and the first charging PMOS pipe Pc1; In the charge pump single-level circuit of the second level first transmission NMOS pipe Nt2 is operated in dark linear zone; Electric charge transfers to the transmission of first in the charge pump single-level circuit of second level capacitor C t2 by the drain electrode of the first transmission NMOS pipe Nt2 in the source electrode of the first transmission PMOS pipe Pt1 of first in first order charge pump single-level circuit transmission capacitor C t1 in first order single-level circuit and the second level single-level circuit and goes up that (first in the first order charge pump single-level circuit transmits the capacitor C t1 and the first control pmos system capacitor C p1 in other words this moment; These three electric capacity of in the charge pump single-level circuit of the second level second transmission capacitor C t2 are shared electric charge, till their electromotive force of positive plate equates).
Like this, charge pump circuit shown in Figure 5 has just been accomplished an interior charge transfer job of clock cycle.In the subsequent clock cycle, the second level ..., identical until the course of work and the first order of x level, can understand with reference to the process of the aforementioned first order and second level charge pump single-level circuit transmission electric charge, do not do here and give unnecessary details.
Afterwards, along with the propelling of clock, the electric charge in the charge pump circuit of present embodiment is constantly by prime level transfer backward, up to output voltage is raised to desired value.
Can know that by the top course of work course of work of two charge transfer path is complementary up and down, if promptly in preceding half period of clock; Second charge transfer path by top provides electric charge to output; Then to output electric charge is provided by the first following charge transfer path in second cycle of clock, thereby guarantees in the whole clock cycle, the driving force of charge pump is all the same; So just improve operating efficiency, reduced the ripple of charge pump output voltage.
In addition; Manage when next stage charge pump single-level circuit transmits via PMOS at electric charge; The grid voltage of this PMOS pipe remains at a constant electronegative potential, rather than As time goes on current potential increases, and this working method can guarantee that the PMOS pipe always works in dark linear zone; And be in a lower conducting resistance, highly significant ground has improved the efficiency of transmission of electric charge like this.Article two, the pipe of the NMOS in the charge transfer path has adopted cross-linked structure, also can guarantee that they are operated in dark linear zone, and not receive the influence of threshold voltage, has improved the single electrode voltage gain of charge pump, has improved the efficiency of transmission of electric charge.
The embodiment of the utility model adopts PMOS switching tube (i.e. the first transmission PMOS pipe Pt1) and nmos switch pipe (i.e. the first transmission NMOS pipe Nt1) to replace the diode in traditional Dickson charge pump in the charge pump single-level circuit, can eliminate the influence of threshold voltage to charge transfer efficiency.Switching tube is usually operated at dark linear zone, and its gate source voltage is much larger than its threshold voltage, therefore for the nmos switch pipe, mainly is the grid voltage that improves it, and mainly is the grid voltage that reduces it for the PMOS switching tube.The circuit structure of the utility model embodiment charge pump has guaranteed to remain on the constant electronegative potential at the grid voltage of charge transfer period P MOS switching tube, and then reduces its conducting resistance.
Compare existing Dickson charge pump, the embodiment of the utility model is more suitable for being operated under the low input, such as 1.2 volts (V) even lower.Because the threshold voltage of NMOS pipe is 0.8 volt of V, is 1.2V if adopt the input voltage of existing Dickson charge pump, charge to 0.4V then can only for the transmission electric capacity of the first order; And the closer to output stage; The receptor effect influence is just big more, and the threshold voltage of NMOS pipe can increase, like 1.0V or the like.If threshold voltage increases to 1.2V, more backward just can not transmission charge, output voltage just can not increase.The embodiment of the utility model has overcome this defective, and each in the charge pump circuit grade can be transmitted whole electric charges.
Though the execution mode that the utility model disclosed as above, the execution mode that described content just adopts for the ease of understanding the utility model is not in order to limit the utility model.Technical staff under any the utility model in the technical field; Under the prerequisite of spirit that does not break away from the utility model and disclosed and scope; Can do any modification and variation what implement in form and on the details; But the scope of patent protection of the utility model still must be as the criterion with the scope that appending claims was defined.
Claims (8)
1. a charge pump single-level circuit is characterized in that, comprises first transmission unit and second transmission unit, wherein:
Said first transmission unit comprises the first clock incoming end, first input end and first output, and said first input end is used to insert first input signal, and said first output is used to export the first output signal;
Said second transmission unit comprises second clock incoming end, second input and second output, and said second input is used to insert second input signal, and said second output is used to export the second output signal;
Said first clock incoming end and second clock incoming end insert the wherein phase in the two phase complementary clock signals respectively; Said first transmission unit is used to follow the clock signal that is inserted electric charge is transferred to first output from said first input end, and said second transmission unit is used to follow the clock signal that is inserted electric charge is transferred to second output from said second input.
2. charge pump single-level circuit as claimed in claim 1 is characterized in that:
Said first transmission unit comprises first transmission circuit and comprises first output control circuit of four control ends; Wherein:
Said first transmission circuit comprises the said first clock incoming end, first input end and first output, also comprises the first input control end and first output control terminal;
First control end of said first output control circuit connects said first output, and second control end connects the said first clock incoming end, and the 3rd control end connects said first output control terminal;
The 4th control end of the said first input control end and first output control circuit connects said second transmission unit respectively, is used to follow the clock signal shutoff of said first clock incoming end access or open the said second transmission unit transmission charge.
3. charge pump single-level circuit as claimed in claim 2 is characterized in that, said first transmission circuit comprises the first transmission NMOS pipe Nt1, the first transmission PMOS pipe Pt1 and the first transmission capacitor C t1, wherein:
The drain electrode of the said first transmission NMOS pipe Nt1 is said first input end, and grid is the said first input control end, and source electrode connects the drain electrode of first end and the said first transmission PMOS pipe Pt1 of the said first transmission capacitor C t1;
Second end of the said first transmission capacitor C t1 is the said first clock incoming end;
The grid of the said first transmission PMOS pipe Pt1 is said first output control terminal, and source electrode and substrate link together, and are said first output.
4. charge pump single-level circuit as claimed in claim 2 is characterized in that, said first output control circuit comprises the first charging PMOS pipe Pc1 and the first control pmos system capacitor C p1, wherein:
Source electrode and the substrate of the said first charging PMOS pipe Pc1 link together, and are first control end of said first output control circuit, and grid is the 3rd control end of said first output control circuit, drains to be the 4th control end of said first output control circuit;
First end of the first control pmos system capacitor C p1 connects the drain electrode of the said first charging PMOS pipe Pc1, and second end is second control end of said first output control circuit.
5. charge pump single-level circuit as claimed in claim 1 is characterized in that:
Said second transmission unit comprises second transmission circuit and comprises second output control circuit of four control ends; Wherein:
Said second transmission circuit comprises said second clock incoming end, second input and second output, also comprises the second input control end and second output control terminal;
First control end of said second output control circuit connects said second output, and second control end connects the said first clock incoming end, and the 3rd control end connects said second output control terminal;
The 4th control end of the said second input control end and second output control circuit connects said first transmission unit respectively, is used to follow the clock signal shutoff of said second clock incoming end access or open the said first transmission unit transmission charge.
6. charge pump single-level circuit as claimed in claim 5 is characterized in that, said second transmission circuit comprises the second transmission NMOS pipe Nt1 ', the second transmission PMOS pipe Pt1 ' and the second transmission capacitor C t1 ', wherein:
The drain electrode of the said second transmission NMOS pipe Nt1 ' is said second input, and grid is the said second input control end, and source electrode connects the drain electrode of first end and the said second transmission PMOS pipe Pt1 ' of the said second transmission capacitor C t1 ';
Second end of the said second transmission capacitor C t1 ' is said second clock incoming end;
The grid of the said second transmission PMOS pipe Pt1 ' is said second output control terminal, and source electrode and substrate link together, and are said second output.
7. charge pump single-level circuit as claimed in claim 5 is characterized in that, said second output control circuit comprises the second charging PMOS pipe Pc1 ' and the second control pmos system capacitor C p1 ', wherein:
Source electrode and the substrate of the said second charging PMOS pipe Pc1 ' link together; First control end for said second output control circuit; Grid is the 3rd control end of said second output control circuit, drains to be the 4th control end of said second output control circuit;
First end of the second control pmos system capacitor C p1 ' connects the drain electrode of the said second charging PMOS pipe Pc1 ', and second end is second control end of said second output control circuit.
8. a charge pump circuit is characterized in that, comprises at least the described single-level circuit of each claim in two-stage such as the claim 1 to 7, wherein:
The first input end of first order single-level circuit and second input link together, and are the input of said charge pump circuit; First output and second output of afterbody single-level circuit link together, and are the output of said charge pump circuit, and through output capacitance ground connection;
The progression x of said charge pump circuit was greater than 2 o'clock, and the first input end of i level single-level circuit connects first output of i-1 level single-level circuit, and second input connects second output of i-1 level single-level circuit; Wherein, i is more than or equal to 2 smaller or equal to x-1, and x level single-level circuit is said afterbody single-level circuit;
The clock signal that first transmission unit of the single-level circuit of adjacent two-stage inserts is complementary.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200396861U CN202513820U (en) | 2012-02-08 | 2012-02-08 | Charge pump single-stage circuit and charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200396861U CN202513820U (en) | 2012-02-08 | 2012-02-08 | Charge pump single-stage circuit and charge pump circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202513820U true CN202513820U (en) | 2012-10-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012200396861U Expired - Lifetime CN202513820U (en) | 2012-02-08 | 2012-02-08 | Charge pump single-stage circuit and charge pump circuit |
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| Country | Link |
|---|---|
| CN (1) | CN202513820U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107070204A (en) * | 2017-04-24 | 2017-08-18 | 上海华力微电子有限公司 | A kind of multi-charge pumping system for optimizing power consumption |
| CN110858749A (en) * | 2018-08-22 | 2020-03-03 | 半导体组件工业公司 | Cross-coupled charge pump and method of operating the same |
| CN112332657A (en) * | 2020-10-20 | 2021-02-05 | 深迪半导体(上海)有限公司 | Charge pump circuit and MEMS sensor |
-
2012
- 2012-02-08 CN CN2012200396861U patent/CN202513820U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107070204A (en) * | 2017-04-24 | 2017-08-18 | 上海华力微电子有限公司 | A kind of multi-charge pumping system for optimizing power consumption |
| CN110858749A (en) * | 2018-08-22 | 2020-03-03 | 半导体组件工业公司 | Cross-coupled charge pump and method of operating the same |
| TWI703802B (en) * | 2018-08-22 | 2020-09-01 | 美商半導體組件工業公司 | Cross-coupled charge pumps and methods of operating same |
| CN110858749B (en) * | 2018-08-22 | 2022-01-04 | 半导体组件工业公司 | Cross-coupled charge pump and method of operating the same |
| CN112332657A (en) * | 2020-10-20 | 2021-02-05 | 深迪半导体(上海)有限公司 | Charge pump circuit and MEMS sensor |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: BEIJING GIGADEVICE SEMICONDUCTOR CO., LTD. Free format text: FORMER NAME: BEIJING GIGADEVICE SEMICONDUCTOR INC. |
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| CP03 | Change of name, title or address |
Address after: 100083 Beijing City, Haidian District Xueyuan Road No. 30, large industrial building A block 12 layer Patentee after: GigaDevice Semiconductor (Beijing) Inc. Address before: 100084 Room 301, B building, Tsinghua Science and Technology Park, Haidian District, Beijing Patentee before: GigaDevice Semiconductor Inc. |
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| CX01 | Expiry of patent term |
Granted publication date: 20121031 |
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| CX01 | Expiry of patent term |