CN118378710B - Quantum processor and quantum computer - Google Patents
Quantum processor and quantum computer Download PDFInfo
- Publication number
- CN118378710B CN118378710B CN202410806083.7A CN202410806083A CN118378710B CN 118378710 B CN118378710 B CN 118378710B CN 202410806083 A CN202410806083 A CN 202410806083A CN 118378710 B CN118378710 B CN 118378710B
- Authority
- CN
- China
- Prior art keywords
- superconducting
- qubit
- frequency
- quantum
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002096 quantum dot Substances 0.000 claims abstract description 277
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 230000008878 coupling Effects 0.000 claims description 106
- 238000010168 coupling process Methods 0.000 claims description 106
- 238000005859 coupling reaction Methods 0.000 claims description 106
- 230000003071 parasitic effect Effects 0.000 claims description 31
- 239000003990 capacitor Substances 0.000 claims description 21
- 230000004907 flux Effects 0.000 claims description 16
- 229910052738 indium Inorganic materials 0.000 claims description 14
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 174
- 238000004422 calculation algorithm Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 230000001276 controlling effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000003993 interaction Effects 0.000 description 6
- 230000001427 coherent effect Effects 0.000 description 5
- 238000011161 development Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 239000002070 nanowire Substances 0.000 description 5
- 241000238366 Cephalopoda Species 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 239000012895 dilution Substances 0.000 description 4
- 238000010790 dilution Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 238000005457 optimization Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000010365 information processing Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005672 electromagnetic field Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000002887 superconductor Substances 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000003113 dilution method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- SWQJXJOGLNCZEY-BJUDXGSMSA-N helium-3 atom Chemical compound [3He] SWQJXJOGLNCZEY-BJUDXGSMSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000003507 refrigerant Substances 0.000 description 1
- 238000005057 refrigeration Methods 0.000 description 1
- 238000010845 search algorithm Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000000411 transmission spectrum Methods 0.000 description 1
- 230000005428 wave function Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computational Mathematics (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Artificial Intelligence (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
The invention relates to the technical field of quantum processors, and discloses a quantum processor and a quantum computer, wherein the quantum processor comprises a plurality of quantum bit layers and a control layer; a qubit layer comprising a first substrate layer and a plurality of superconducting qubits located on a first surface of the first substrate layer and coupled to each other; the control layer comprises a second substrate layer and a plurality of first control circuits, the plurality of first control circuits are positioned on the second surface of the second substrate layer, and the second surface and the third surface are connected through superconducting columns; the plurality of first substrate layers are arranged on the second surface at intervals, the first qubit layer and the second qubit layer are coupled through a coupler, and the first qubit layer and the second qubit layer are two of the plurality of qubit layers. The invention can expand the number of superconducting qubits without reducing the performance of superconducting qubits and introducing additional error channels to reduce the fidelity of gate operation.
Description
Technical Field
The invention relates to the technical field of quantum processors, in particular to a quantum processor and a quantum computer.
Background
The superconducting quantum processor has single-quantum bit gate and double-quantum bit gate with flexibility and high fidelity and rapid reading operation, and is one of platforms for realizing large-scale quantum computation at present. While the number of superconducting qubits that need to be used to implement complex quantum algorithm demonstration may be millions, currently, under the condition of ensuring the bit quality (such as decoherence time and gate operation error rate, etc.), the number of superconducting qubits in a superconducting qubit processor can only reach hundreds or thousands, so that a significant challenge is to ensure the expansion of the number of superconducting qubits, and meanwhile, the performance of the bits is not reduced and additional error channels are not introduced to reduce the fidelity of the gate operation.
At present, the number of the quantum bits can be increased through a mode of interconnection of a plurality of superconducting quantum processors, but in order to avoid the problem that the performance of the superconducting quantum bits is affected by insufficient refrigerating capacity, the superconducting quantum processors of the plurality of interconnection need to cross-refrigerating machines, and the cross-refrigerating machines are interconnected, so that a great challenge is presented to the quality of the refrigerating machines. In addition, when the superconducting quantum processors are interconnected, in order to reduce the loss of photons in the transmission process, the superconducting quantum processors are connected by using high-purity materials, and the process has higher difficulty. Thus, there is a need for a new way to increase the number of superconducting qubits in a quantum processor, and to be able to reduce the fidelity of gate operation without degrading bit performance and introducing additional false channels.
Disclosure of Invention
In view of the above, the present invention provides a quantum processor and a quantum computer to solve the problem of reduced performance of the bits and reduced fidelity of gate operation by introducing additional error channels while increasing the number of superconducting qubits in the quantum processor.
In a first aspect, the present invention provides a quantum processor comprising a plurality of qubit layers and a control layer; the qubit layer comprises a first substrate layer and a plurality of superconducting qubits, wherein the plurality of superconducting qubits are positioned on a first surface of the first substrate layer and are coupled with each other; the control layer comprises a second substrate layer and a plurality of first control lines, the plurality of first control lines are positioned on a second surface of the second substrate layer, the second surface and a third surface are connected through superconducting columns, wherein the plurality of first control lines are in one-to-one correspondence with superconducting qubits of the plurality of qubit layers, and the third surface is a surface, opposite to the first surface, of the first substrate layer; the plurality of first substrate layers are arranged on the second surface at intervals, and the first qubit layer and the second qubit layer are coupled through a coupler, wherein the first qubit layer and the second qubit layer are two of the plurality of qubit layers.
The quantum processor provided by the invention adopts a modularized method, superconducting quantum bits (each quantum bit layer) of different chips and couplers for coupling the superconducting quantum bits on different chips are arranged on the same layer, a first control line for reading superconducting quantum bit information and controlling the superconducting quantum bits is arranged on another layer (control layer), and the two layers are connected through a superconducting pole and the couplers so as to complete quantum coherent interconnection between different chips. The invention expands the quantity of superconducting quantum bits in the quantum processor by a modularized method, does not increase the quantity of superconducting quantum bits on a single chip (quantum bit layer), does not influence the performance of the quantum bits, and independently arranges a layer of first control circuit, thereby reducing the difficulty of wiring when the quantity of superconducting quantum bits is increased, and avoiding the problem of gate operation error channel increase caused by large-scale wiring. The modularized structure provided by the invention is essentially different from a mode of completing interconnection across a refrigerator, so that the requirements on the performance of the refrigerator are reduced, and the quantum coherence interconnection can be completed through a flip chip bonding process for the connection between a plurality of quantum bit layers and between the quantum bit layers and a control layer in a quantum processor.
In an alternative embodiment, the coupler is located on the first surface of the first substrate layer of the second qubit layer, one end of the coupler is grounded, the other end of the coupler is connected with a first superconducting qubit through the superconducting column, and the other end of the coupler is connected with a second superconducting qubit, so that the first qubit layer and the second qubit layer are coupled, wherein the first superconducting qubit is one of a plurality of superconducting qubits of the first qubit layer in an edge region, and the second superconducting qubit is one of a plurality of superconducting qubits of the second qubit layer in an edge region.
In an alternative embodiment, the coupler includes a first capacitance and a first superconducting quantum interferometer, the first capacitance and the first superconducting quantum interferometer being connected in parallel.
In the embodiment, the coupler is arranged into a structure that a capacitor and a superconducting quantum interferometer are connected in parallel, so that a direct coupling path between superconducting quantum bits at the edges of two quantum bit layers can be optimized, energy loss is reduced, the coherence time of the superconducting quantum bits is prolonged, and the fidelity of a quantum gate is improved. Furthermore, the adjustability of the superconducting quantum interferometer (SQUID) structure allows the coupling strength of each superconducting qubit to be independently adjusted, enabling specific quantum algorithms and multiple quantum bit gate operations.
In an alternative embodiment, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler are determined based on a preset effective coupling strength, wherein the preset effective coupling strength is a preset effective coupling strength between the first superconducting qubit and the second superconducting qubit.
In this embodiment, the effective coupling strength can be flexibly controlled by adjusting the frequency of the first superconducting qubit, the frequency of the second superconducting qubit, and the frequency of the coupler.
In an alternative embodiment, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler are determined by the preset effective coupling strength and a first correspondence, wherein the first correspondence is used for representing the correspondence among the effective coupling strength, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler.
In an alternative embodiment, the first correspondence is expressed by the following formula:
Wherein, Representing the strength of the effective coupling in question,Representing the strength of the direct coupling between the first superconducting qubit and the second superconducting qubit,Representing the coupling strength between the first superconducting qubit and the coupler,Representing the coupling strength between the second superconducting qubit and the coupler,，Representing the frequency of the first superconducting qubit,Representing the frequency of the coupler,，Representing the frequency of the second superconducting qubit,，。
In an alternative embodiment, the first superconducting qubit includes a second capacitance and the second superconducting qubit includes a third capacitance; the saidIs determined by the following formula:
Wherein, Representing the capacity of the second capacitor,Representing the capacity of said third capacitor,Representing the coupling capacities of the second capacitor and the third capacitor.
In an alternative embodiment, theLess than or equal to 2MHz.
In an alternative embodiment, the4GHz, said4.6GHz, said0.25MHz of the10MHz of the50MHz of theAnd determining based on the preset effective coupling strength.
In an alternative embodiment, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler are determined based on a preset effective coupling strength and a preset residual parasitic coupling strength, wherein the preset residual parasitic coupling strength is a preset residual parasitic coupling strength between the first superconducting qubit and the second superconducting qubit.
In this embodiment, by adjusting the frequency of the first superconducting qubit, the frequency of the second superconducting qubit, and the frequency of the coupler, the remaining parasitic coupling strength can be controlled to be an accessory of 0MHz, and the fidelity of the quantum gate operation can be improved.
In an alternative embodiment, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler are determined by presetting an effective coupling strength, presetting a residual parasitic coupling strength and a second correspondence, wherein the second correspondence is used for representing the correspondence among the effective coupling strength, the residual parasitic coupling strength, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler.
In an alternative embodiment, the second correspondence is expressed by the following formula:
Wherein, Representing an effective hamiltonian amount between the first superconducting qubit and the second superconducting qubit,Representing the frequency of the first superconducting qubit,Representing the frequency of the second superconducting qubit,、、AndThe bubble-benefit operator is represented by a bubble-benefit operator,Representing the strength of the effective coupling in question,Representing the strength of the remaining parasitic coupling,，Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesIs a constant value of (a) and (b).
In an alternative embodiment, the4GHz, saidThe frequency of the coupler is determined based on the preset effective coupling strength and the preset residual parasitic coupling strength at 4.6 GHz.
In an alternative embodiment, the material of the superconducting pillar is indium.
In the embodiment, the indium column is not easy to deform after low-temperature superconduction, and quantum information can be transmitted in a superconducting state without loss, so that the accuracy and stability of quantum information transmission are improved.
In an alternative embodiment, the superconducting cylinder is cylindrical, and the diameter of the superconducting cylinder ranges from 30 μm to 50 μm.
In an alternative embodiment, the height of the superconducting pillars ranges from 7 μm to 9 μm.
In this embodiment, the diameter of the superconducting pillars is limited to 30 μm to 50 μm, and the height of the superconducting pillars is limited to 7 μm to 9 μm, so as to avoid the influence of the indium pillars on the coupling strength between superconducting qubits.
In an alternative embodiment, the second surface and the third surface are connected by flip-chip bonding based on the superconducting pillars.
In an alternative embodiment, the control layer further includes a second control line located on the second surface of the second substrate layer, the second control line being disposed corresponding to the coupler, the first control line and the second control line each including a magnetic flux control line, the magnetic flux control line of the first control line being used to adjust the frequency of the corresponding superconducting qubit, the magnetic flux control line of the second control line being used to adjust the frequency of the coupler.
In an alternative embodiment, the first control line comprises a drive line for controlling the state of the superconducting qubit.
In a second aspect, the present invention provides a quantum computer comprising: the quantum processor of the first aspect or any one of the embodiments corresponding thereto.
According to the quantum processor provided by the invention, the modularized plurality of quantum bit layers are subjected to quantum coherent interconnection through the superconducting pole and the coupler, the number of superconducting quantum bits on a single chip is not increased, the number of superconducting quantum chips in the quantum processor is expanded, the performance of the quantum bits is not reduced, and the circuit for reading superconducting quantum bit information and controlling bit states (namely the first control circuit) is independently provided with one layer, so that the wiring difficulty when the number of superconducting quantum bits is increased can be reduced, and the problem of gate operation error channel increase caused by large-scale wiring is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the description of the embodiments or the related art will be briefly described, and it is apparent that the drawings in the description below are some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic diagram of a quantum processor under a first viewing angle according to an embodiment of the present invention;
Fig. 2 is a schematic diagram of the structure of a plurality of qubit layers at a second viewing angle according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the structure of a control layer at a second viewing angle according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the connection of a coupler, a superconducting pillar, and a qubit layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the correspondence of frequency, direct coupling strength, and effective coupling strength of a coupler according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the correspondence of frequency and effective coupling strength of a coupler according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the correspondence of the frequency, the direct coupling strength and the residual parasitic coupling strength of a coupler according to an embodiment of the present invention;
Fig. 8 is a schematic diagram of the correspondence between the frequency of the coupler and the residual parasitic coupling strength according to an embodiment of the present invention.
Reference numerals: 110. a qubit layer; 111. a first substrate layer; 112. superconducting qubits; 120. a control layer; 121. a second substrate layer; 122. a first control line; 1221. a magnetic flux control line; 1222. a driving line; 1223. a reading chamber; 123. a second control line; 130. a super-guide post; 140. a coupler.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Before explaining the quantum processor of the present application, first, related terms involved in the embodiments of the present application are explained for easy understanding.
(1) Quantum computer
Quantum computers are complete systems that utilize the superconducting properties exhibited by superconducting materials at very low temperatures to achieve quantum information processing by constructing superconducting qubits (typically based on josephson junctions), and include quantum processors, cryocooling systems (e.g., dilution cryocoolers), and software stacks required to achieve quantum algorithms and quantum error correction, among others. The objective of a quantum computer is to solve the problem that the traditional computer is difficult to process, such as large-scale factor decomposition, optimization problem, quantum simulation and the like, by utilizing the superposition state and entanglement equivalent quantum characteristics of quantum bits.
(2) Quantum processor
Quantum processors are the core components of quantum computers, integrated circuits fabricated by superconducting circuit technology for implementing quantum information processing. Quantum processors typically contain a series of superconducting qubits (e.g., superconducting josephson junction bits) and the necessary control and readout circuitry to perform quantum computation, quantum simulation, and quantum communication equivalent quantum information tasks.
Superconducting qubits are the basic computational unit of a quantum processor, typically consisting of superconducting josephson junctions or their derivative structures). Superconducting qubits utilize quantum properties of superconducting states (e.g., cooper pairs, macroscopic quantum coherence, etc.) to encode and manipulate quantum information. The quantum state of a superconducting qubit is typically read out by its strong coupling to the superconducting resonator. The resonant cavity acts as an interface between the qubit and the microwave signal, and by detecting small changes in the resonant frequency of the microwave cavity (caused by the qubit state), the state of the qubit can be inferred indirectly. Quantum processors must operate on cryogenic platforms such as dilution refrigerators, typically on the order of millikelvin (mK), to reduce thermal noise and extend the coherence time of the qubits.
Quantum processor design and optimization has focused on improving the performance of the qubits (e.g., reducing quantum decoherence (Decoherence) time and improving quantum gate fidelity), increasing the number of qubits, and achieving efficient inter-qubit interconnections to support more complex quantum algorithm execution.
Implementing complex algorithmic demonstrations, such as the schiff (Shor) algorithm, the Grover (Grover) algorithm, etc., with sufficiently low error rates, the number of physical bits of superconducting qubits that need to be used can be millions of levels, and 1121 physical bit numbers are currently implemented on a quantum processor, which is structured in a honeycomb-like hexagonal structure, but this number is also difficult to accomplish complex quantum calculations. Stacking the number of qubits from a single chip is very difficult and requires compatible resolution of challenges in all layers of the quantum computer stack at the same time, e.g., the underlying quantum hardware, the middle classical control electronics, the higher-level software (i.e., the micro instruction set, the compiler, and the high-level programming language), etc.
It should be understood that the shell algorithm is a quantum algorithm, which can perform factorization on large integers in polynomial time, and the Grover algorithm is a quantum search algorithm, which can find specific items in an unordered database, and the speed is far faster than any known classical algorithm, and the Grover algorithm has potential application in the fields of processing large data sets, password cracking, optimization problems, pattern recognition, large data analysis, and the like.
(3) Refrigerating machine
A refrigerator is a cryogenic device that is primarily used to create an extremely low temperature environment near absolute zero (0K, approximately equal to-273.15 ℃) and is a critical tool for achieving ultra low temperatures. The working principle of the refrigerator is based on the dilution refrigeration technology, and the extremely low temperature is achieved by utilizing the dilution process of a dilution refrigerant (usually helium-3 (≡3He)) in superfluid helium-4 (≡4He).
(4) Fidelity (Fidelity)
In the field of quantum computing and quantum information processing, fidelity is generally defined as the degree of overlap between two quantum states or between an actual implemented quantum operation and its ideal theoretical operation, and is a measure (key indicator) of the degree to which a quantum state or quantum process approaches an ideal state or process. High fidelity means that quantum gates can perform with very little error rate and that the information is less disturbed during transmission.
In order to solve the problem of how to ensure the expansion of the quantity of superconducting qubits without reducing the performance of the superconducting qubits and introducing an additional error channel to reduce the fidelity of gate operation, the invention assembles superconducting qubit modules corresponding to a small-sized high-yield sub-processor in a modularized mode to form a quantum processor with larger quantity of superconducting qubits. The modular structure is essentially different from the interconnection between chips finished by a cross-refrigerator, so that the requirements on the performance of the refrigerator are reduced, and meanwhile, the quantum coherent interconnection can be realized by using a flip-chip bonding process to realize the connectivity of each module.
The quantum processor provided by the invention is described in detail below with reference to the accompanying drawings.
As shown in fig. 1,2 and 3, the quantum processor includes a plurality of qubit layers 110 and a control layer 120. Fig. 1 and 2 illustrate an example in which the number of the qubit layers 110 is 2, but are not limited thereto. For example, the number of qubit layers 110 in a quantum processor may be 5, 8, 10, 20, or the like.
Specifically, the qubit layer 110 includes a first substrate layer 111 and a plurality of superconducting qubits 112, the plurality of superconducting qubits 112 being located on a first surface of the first substrate layer 111 and coupled to each other. The first surface is a side surface of the first substrate layer 111, for example, in the view of fig. 1, the first surface may be an upper surface of the first substrate layer 111, the plurality of superconducting qubits 112 may be disposed on the upper surface of the first substrate layer 111 at intervals, and the plurality of superconducting qubits 112 are coupled to each other.
The control layer 120 includes a second substrate layer 121 and a plurality of first control lines 122, the plurality of first control lines 122 being located on a second surface of the second substrate layer 121, the second surface and the third surface being connected by the superconducting pillars 130.
The second surface is a side surface of the second substrate layer 121, the third surface is a surface of the first substrate layer 111 opposite to the first surface, for example, in the view of fig. 1, the second surface of the second substrate layer 121 may be an upper surface of the second substrate layer 121, and the third surface may be a lower surface of the first substrate layer 111. Specifically, the device structure diagram corresponding to the first view angle in this embodiment may be a cross-sectional view.
The plurality of first control lines 122 and the superconducting qubits 112 of the plurality of qubit layers 110 are in one-to-one correspondence, that is, the number of the plurality of first control lines 122 is the same as the total number of the superconducting qubits 112 of the plurality of qubit layers 110, and the first control lines 122 are disposed around each superconducting qubit 112, and the first control lines 122 are used for reading information of the corresponding superconducting qubit 112 and controlling a state (e.g., 0 or 1) of the corresponding superconducting qubit. The superconducting pillar 130 may be a structure prepared by superconducting materials for connecting the qubit layer 110 and the control layer 120 to transmit quantum information without loss in a superconducting state.
The plurality of first substrate layers 111 are spaced apart on the second surface, and the first qubit layers and the second qubit layers are coupled by a coupler 140. Wherein the first qubit layer and the second qubit layer are two of the plurality of qubit layers 110, for example, as shown in fig. 1, the first qubit layer may be the qubit layer 110 located at the left side of the control layer 120, and the second qubit layer may be the qubit layer 110 located at the right side of the control layer 120.
Coupler 140 is a coupling structure that couples together superconducting qubits of two qubit layers (i.e., a first qubit layer and a second qubit layer). That is, quantum coherent interconnection between any two of the plurality of qubit layers 110 may be achieved through the coupler 140 and the superconducting pillar 130.
The quantum processor provided by the invention adopts a modularized method, superconducting quantum bits (each quantum bit layer) of different chips and couplers for coupling the superconducting quantum bits on different chips are arranged on the same layer, a first control line for reading superconducting quantum bit information and controlling the superconducting quantum bits is arranged on another layer (control layer), and the two layers are connected through a superconducting pole and the couplers so as to complete quantum coherent interconnection between different chips. The invention expands the quantity of superconducting quantum bits in the quantum processor by a modularized method, does not increase the quantity of superconducting quantum bits on a single chip (quantum bit layer), does not influence the performance of the quantum bits, and independently arranges a layer of first control circuit, thereby reducing the difficulty of wiring when the quantity of superconducting quantum bits is increased, and avoiding the problem of gate operation error channel increase caused by large-scale wiring. The modularized structure provided by the invention is essentially different from a mode of completing interconnection across a refrigerator, so that the requirements on the performance of the refrigerator are reduced, and the quantum coherence interconnection can be completed through a flip chip bonding process for the connection between a plurality of quantum bit layers and between the quantum bit layers and a control layer in a quantum processor.
The invention does not limit the number of superconducting qubits 112 on the qubit layer, so long as the performance is not affected and the requirement that the error channel is not increased can be satisfied. For example, the number of superconducting qubits 112 on the qubit layer 110 may be around 100, such as 60, 80, 90, 100, 120, etc., depending on the existing micronano-fabrication level.
Wherein fig. 2 only shows a first superconducting qubit Q 1 located at an edge of the first qubit layer and a second superconducting qubit Q 2 located at an edge of the second qubit layer, the number of superconducting qubits on the qubit layer is not limited thereto.
Specifically, superconducting qubit 112 generally includes a capacitance and a superconducting quantum interferometer, which are connected in parallel. It will be appreciated that superconducting quantum interferometers (Superconducting Quantum INTERFERENCE DEVICES, SQUID) are typically composed of two josephson junctions in parallel. The josephson junction (or superconducting tunnel junction) consists of two superconductors that are weakly connected to each other, and the weakly connected structure may be a thin insulating layer, a small section of non-superconducting metal, or a narrow section that can weaken the superconductivity of the contact point. SQUID is essentially a magnetic flux sensor that converts magnetic flux into voltage.
For example, as shown in FIG. 2, the first superconducting qubit Q 1 includes a second capacitance C 1 and a second superconducting quantum interferometerSecond capacitor C 1 and second superconducting quantum interferometerAnd are connected in parallel. The second superconducting qubit Q 2 comprises a third capacitor C 2 and a third superconducting quantum interferometerThird capacitor C 2 and third superconducting quantum interferometerAnd are connected in parallel. Wherein the second superconducting quantum interferometerStructure of (2) and third superconducting quantum interferometerCan be obtained by connecting two Josephson junctions in parallel.
The present invention also does not limit the distribution position and the distribution shape of the plurality of superconducting qubits 112, and the distribution position and the distribution shape of the plurality of superconducting qubits 112 may be determined by a worker according to the needs, for example, the plurality of superconducting qubits 112 may be equidistantly and alternately arranged in a preset area on the first surface, and the distribution shape of the plurality of superconducting qubits 112 may be rectangular.
Illustratively, both the first substrate layer 111 and the second substrate layer 121 may be silicon substrates. Silicon has good chemical stability and a relatively high melting point (about 1440 ℃) and is convenient for subsequent processing.
The present invention is not limited to the location of the coupler 140, and may be disposed on the first substrate layer 111 of the first qubit layer or may be disposed on the first substrate layer 111 of the second qubit layer, and fig. 2 in this embodiment is an example in which the coupler Q c is disposed on the first substrate layer 111 of the second qubit layer, but is not limited thereto.
The present invention is not limited to the structure of the coupler 140 as long as the first and second qubit layers can be facilitated to interact (couple). For example, coupler 140 may be a microwave resonant cavity, a superconducting wire, or a capacitive coupling structure, among others.
Exemplary, coupler Q c may include a first capacitor C C and a first superconducting quantum interferometerFirst capacitor C C and first superconducting quantum interferometerParallel, first superconducting quantum interferometerCan be combined with a second superconducting quantum interferometerThe structure of (2) is the same. That is, coupler Q c may also be formed from first capacitor C C and a first superconducting quantum interferometerThe parallel result is that coupler Q c is also essentially a superconducting qubit.
In the embodiment, the coupler is arranged into a structure that a capacitor and a superconducting quantum interferometer are connected in parallel, so that a direct coupling path between superconducting quantum bits at the edges of two quantum bit layers can be optimized, energy loss is reduced, the coherence time of the superconducting quantum bits is prolonged, and the fidelity of a quantum gate is improved. Furthermore, the adjustability of the superconducting quantum interferometer (SQUID) structure allows the coupling strength of each superconducting qubit to be independently adjusted, enabling specific quantum algorithms and multiple quantum bit gate operations.
In other alternative embodiments, coupler Q c may include a capacitor and a nanowire junction connected in parallel to form coupler Q c. Specifically, the nanowire junction (Nanowire Junction) is a structure in which a layer of metal aluminum film grows on the surface layer of the nanowire, then the middle of the aluminum film is completely cut and divided into two pieces, and the two pieces of aluminum are mutually connected through the nanowire. This particular structure can be equivalent to a josephson junction, since aluminum will become a superconductor at low temperatures.
Specifically, as shown in fig. 4, coupler Q c is located on the first surface of the first substrate layer of the second qubit layer (qubit layer 110 shown on the right side of fig. 4), one end of coupler Q c is grounded, the other end of coupler Q c is connected to the first superconducting qubit Q 1 through superconducting pillar 130, and the other end of coupler Q c is connected to the second superconducting qubit Q 2 to couple the first qubit layer (qubit layer 110 shown on the left side of fig. 4) and the second qubit layer.
Wherein the first superconducting qubit Q 1 is one of the plurality of superconducting qubits of the first qubit layer in the edge region, and the second superconducting qubit Q 2 is one of the plurality of superconducting qubits of the second qubit layer in the edge region.
Illustratively, the material of the superconducting pillars 130 may be indium, i.e., the superconducting pillars 130 may be indium pillars. In the embodiment, the indium column is not easy to deform after low-temperature superconduction, and quantum information can be transmitted in a superconducting state without loss, so that the accuracy and stability of quantum information transmission are improved.
Illustratively, the superconducting pillars 130 may have a cylindrical shape, the diameter of the superconducting pillars 130 may have a value ranging from 30 μm to 50 μm, and the height of the superconducting pillars 130 may have a value ranging from 7 μm to 9 μm. That is, the diameter of the superconducting column 130 may be any value between 30 μm and 50 μm, the height of the superconducting column 130 may be any value between 7 μm and 9 μm, for example, the diameter of the superconducting column 130 may be 30 μm, 35 μm, 40 μm, 42 μm, 50 μm, or the like, and the height of the superconducting column 130 may be 7 μm, 8 μm, 9 μm, or the like.
In the present embodiment, the range of the diameter of the superconducting pillars 130 is defined to be 30 μm to 50 μm, and the range of the height of the superconducting pillars 130 is defined to be 7 μm to 9 μm, so as to avoid the influence of the indium pillars on the coupling strength between superconducting qubits.
The second surface and the third surface are illustratively connected by flip-chip bonding based on indium columns.
It should be understood that Flip-Chip (Flip-Chip) is an advanced electronic packaging technology, and the qubit layer can be connected with the corresponding position on the control layer through a micro bump (indium column), so that pins and leads are omitted, signal paths are shortened, parasitic capacitance and inductance are reduced, and the transmission speed of quantum information is improved.
In this embodiment, when the indium columns are used to interconnect the two qubit layers, the distance between the indium columns can be widened, the distance between the two qubit layers is indirectly increased, the difficulty of wiring is further reduced, and crosstalk caused by the difficulty of wiring is reduced.
Illustratively, as shown in fig. 3, the control layer 120 further includes a second control line 123 disposed on the second surface of the second substrate layer 121, the second control line 123 being disposed corresponding to the coupler 140, the second control line 123 being configured to control the state of the coupler 140, and the second control line 123 may have the same structure as the first control line 122.
As shown in fig. 3, the first control line 122 and the second control line 123 may each include a magnetic flux control line 1221, the magnetic flux control line 1221 of the first control line 122 being used to adjust the frequency of the corresponding superconducting qubit, and the magnetic flux control line 1221 of the second control line 123 being used to adjust the frequency of the coupler.
Where frequency is the basis of the qubit operation, determining the speed and type of quantum gate operation. The frequency is regulated through the magnetic flux control line, so that the initialization (set to a specific energy level) of the quantum bits, the inversion of the quantum states (for example, the inversion of the quantum bits is realized through resonance driving) and the interaction regulation among the quantum bits can be realized, and corresponding quantum algorithms can be performed.
Specifically, the magnetic flux control line 1221 indirectly regulates the frequency of the superconducting qubit by changing the effective magnetic field environment in which the superconducting qubit is located, and the magnetic flux control line is disposed below or near the corresponding superconducting qubit, and is capable of introducing an adjustable magnetic field. When a current is passed through the control line, a current-dependent magnetic field is generated which interacts with the intrinsic magnetic field in the superconducting qubit, thereby changing the effective magnetic flux of the superconducting qubit. That is, the frequency of the superconducting qubit can be adjusted by precisely controlling the magnitude of the externally applied magnetic field.
Illustratively, as shown in FIG. 3, the first control line 122 also includes a drive line 1222, the drive line 1222 for controlling the state of the superconducting qubit. In particular, the state of the superconducting qubit may be 0, 1, or other states (e.g., an superposition of 0 and 1).
The drive line 1222 refers to a microwave line for transmitting a control signal (precisely modulated microwave pulse) to the superconducting qubit, i.e., the drive line 1222 is a channel for transmitting a precisely modulated microwave pulse to the superconducting qubit to trigger transitions between superconducting qubit energy levels, thereby changing the state of the superconducting qubit. For example, when it is necessary to control the state of the superconducting qubit to be 0 or 1, a specific microwave pulse is applied through the driving line, so that the state of the superconducting qubit is changed from an initial state (for example, an overlapped state) to 0 or 1.
Illustratively, as shown in FIG. 3, the first control line 122 also includes a read chamber 1223, the read chamber 1223 being configured to read information of a corresponding superconducting qubit. The read cavity 1223 refers to a microwave resonant cavity coupled to a superconducting qubit for non-destructive reading of the state of the superconducting qubit.
In particular, the state of the superconducting qubit may be read based on the interaction between the electromagnetic field of the cavity and the qubit state. When the energy state of the superconducting quantum bit changes, the electromagnetic field of the cavity is influenced, so that the resonant frequency or the energy absorption/emission characteristic of the cavity is changed, and the state of the superconducting quantum bit can be determined by measuring the microwave transmission spectrum or the reflection spectrum of the cavity.
Illustratively, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit, and the frequency of the coupler are determined based on a predetermined effective coupling strength.
The preset effective coupling strength is the effective coupling strength between the preset first superconducting qubit and the preset second superconducting qubit. The effective coupling strength describes the strength of interaction between the first superconducting qubit and the second superconducting qubit, and directly influences the speed and efficiency of conversion of quantum information between the two superconducting qubits, namely the effective coupling strength is a key parameter for measuring the interaction strength between the two superconducting qubits, and is important for realizing high-quality operation of two superconducting qubit gates and verifying and optimizing the connectivity of the quantum bits between chips.
Specifically, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler are determined through preset effective coupling strength and a first corresponding relation, wherein the first corresponding relation is used for representing the corresponding relation among the effective coupling strength, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler.
Illustratively, the first correspondence may be represented by the following formula (1):
Wherein, Indicating the strength of the effective coupling and,Representing the strength of the direct coupling between the first superconducting qubit and the second superconducting qubit,Representing the coupling strength between the first superconducting qubit and the coupler,Representing the coupling strength between the second superconducting qubit and the coupler,，Representing the frequency of the first superconducting qubit,Indicating the frequency of the coupler,，Representing the frequency of the second superconducting qubit,，。
Specifically, the effective coupling strength is the strength of interaction between two superconducting qubits achieved by a coupler, and determines the efficiency of operations such as quantum entanglement generation and quantum gate implementation between superconducting qubits. The direct coupling strength refers to the interaction strength between two superconducting qubits, which is the most basic and not regulated by any coupling structure.
Exemplary, the direct coupling strength between the first superconducting qubit and the second superconducting qubitCan be determined by the following formula (2):
Wherein, Representing the capacity of the second capacitor,Representing the capacity of the third capacitor,Representing the coupling capacities of the second capacitor and the third capacitor.
In some of the alternative embodiments of the present invention,Less than or equal to 2MHz, for example,May be 0.2MHz, 0.5MHz, 1MHz, 2MHz, etc. In particular, the frequency of the first superconducting qubit and the frequency of the second superconducting qubit can be adjustedDefined as 0.25MHz.
By way of example only, and not by way of limitation,At the frequency of 4GHz,At the time of 4.6GHz,At a frequency of 0.25MHz,At the frequency of 10MHz,At a frequency of 50MHz,Based on the preset effective coupling strength.
In particular, inIn this case, based on the above-described formula (1) and formula (2), it can be determined that、With effective coupling strengthThe correspondence between them is, for example,、With effective coupling strengthThe correspondence between these may be as shown in fig. 5.
As can be seen from fig. 5, asAndIs used for the increase of (a),And also gradually increases. The data of fig. 5 may also illustrate that there is a certain effective coupling strength between the first qubit layer and the second qubit layer, and the multiple qubit layers in the quantum processor provided by the present invention may implement related interconnection. In addition, it can be seen from the data of fig. 5 that the effective coupling strength between the first qubit layer and the second qubit layer can be from negative to 0MHz and then from 0MHz to positive, which also illustrates that the two qubit layers can be used independently without affecting each other.
Further, fixIn the following，In this case, based on the above formula (1), it can be determined thatWith effective coupling strengthThe correspondence between them is, for example,With effective coupling strengthThe correspondence between these may be as shown in fig. 6.
As can be seen from fig. 6, asIs used for the increase of (a),Also gradually increasing and can go from negative to 0MHz and from 0MHz to positive. The data of fig. 6 further illustrates that the structure of the quantum processor provided by the present invention is possible.
Illustratively, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit, and the frequency of the coupler are determined based on a preset effective coupling strength and a preset residual parasitic coupling strength.
The preset residual parasitic coupling strength is the residual parasitic coupling strength between the preset first superconducting qubit and the preset second superconducting qubit. The residual parasitic coupling strength refers to the strength of capacitive coupling between two superconducting qubits, and may cause crosstalk between superconducting qubits, affecting the fidelity of implementing a two-bit gate operation between two qubit layers.
Specifically, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler are determined by presetting an effective coupling strength, presetting a residual parasitic coupling strength and a second corresponding relation. The second correspondence is used for representing the correspondence among the effective coupling strength, the residual parasitic coupling strength, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler.
Illustratively, the second correspondence may be represented by the following formula (3):
Wherein, Representing the effective hamiltonian amount between the first superconducting qubit and the second superconducting qubit,、、AndThe bubble-benefit operator is represented by a bubble-benefit operator,Indicating the strength of the remaining parasitic coupling,，Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesCan be determined by solving for the effective hamiltonian、、And。
Specifically, the effective Hamiltonian refers to a Hamiltonian of a simplified model obtained by ignoring or averaging out some high-energy or unimportant effects under specific conditions, and the Hamiltonian (Hamiltonian) can be an operator, which acts on a wave function of a system (quantum processor) to describe an energy state of the system. The bubble sharp operator (Pauli Operators) is a group of basic matrix operators in quantum computation and quantum information, plays a key role in describing the spin dynamics of a quantum system, constructing a quantum gate, realizing quantum coding and the like, and constructs a quantum algorithm and a powerful tool for understanding the symmetry of the quantum system.
By way of example only, and not by way of limitation,At the frequency of 4GHz,The frequency of the coupler is determined based on the predetermined effective coupling strength and the predetermined residual parasitic coupling strength at 4.6 GHz.
In particular, inIn this case, based on the above-described formula (1), formula (2) and formula (3), it can be determined that、With residual parasitic coupling strengthThe correspondence between them is, for example,、With residual parasitic coupling strengthThe correspondence between these may be as shown in fig. 7.
As can be seen from fig. 7, by reducingAndCan be used forPress to 0 attachment. That is, the data of fig. 7 can illustrate that the quantum processor provided by the present invention can minimize the influence of the residual parasitic coupling strength on the two-bit gate operation between different chips.
Further, fixIn the following，At this time, based on the above-described formula (3) and formula (1), it can be determined thatWith residual parasitic coupling strengthThe correspondence between them is, for example,With residual parasitic coupling strengthThe correspondence between these may be as shown in fig. 8.
As can be seen from fig. 8, asIs used for the increase of (a),The increase is carried out firstly and then the decrease is carried out,Can be close to 0MHz from negative values. The data of fig. 8 further illustrates that the structure of the quantum processor provided by the present invention is possible.
The invention also provides a preparation method of the quantum processor, which comprises the following steps:
And a step a1, forming a first quantum bit layer.
Specifically, a first substrate layer is provided, and etching treatment is performed on a first surface of the first substrate layer to form a plurality of superconducting qubits, so that a first qubit layer is obtained.
Illustratively, the step of etching the first surface of the first substrate layer to form a plurality of superconducting qubits includes: and forming a photoresist layer on the first surface of the first substrate layer, performing exposure treatment on the photoresist layer based on the first mask plate, performing development treatment on the photoresist layer after performing exposure treatment, and performing etching treatment on the first surface of the first substrate layer by taking the residual photoresist as a mask after performing development treatment to form a plurality of superconducting qubits on the first surface. The pattern of the first mask plate corresponds to the pattern formed by the superconducting quantum bits.
And a step a2 of forming a second qubit layer.
Specifically, a first substrate layer is provided, and etching treatment is carried out on the first surface of the first substrate layer to form a plurality of superconducting qubits and couplers, so that a second qubit layer is obtained. Wherein the coupler is connected with one of the superconducting qubits in the edge region among the plurality of superconducting qubits.
Illustratively, the step of etching the first surface of the first substrate layer to form a plurality of superconducting qubits and couplers includes: and forming a photoresist layer on the first surface of the first substrate layer, performing exposure treatment on the photoresist layer based on the second mask plate, performing development treatment on the photoresist layer after performing the exposure treatment, and performing etching treatment on the first surface of the first substrate layer by taking the residual photoresist as a mask after performing the development treatment, thereby forming a plurality of superconducting qubits and couplers on the first surface. The pattern of the second mask plate corresponds to the pattern formed by the superconducting qubits and the coupler.
And a step a3 of forming a control layer.
Specifically, a second substrate layer is provided, etching treatment is carried out on the second surface of the second substrate layer, a plurality of first control circuits are formed, and then the control layer is obtained.
Illustratively, the step of etching the second surface of the second substrate layer to form a plurality of first control lines includes: and forming a photoresist layer on the second surface of the second substrate layer, performing exposure treatment on the photoresist layer based on the third mask plate, performing development treatment on the photoresist layer after performing exposure treatment, performing etching treatment on the second surface of the second substrate layer by taking the residual photoresist as a mask, and forming a plurality of first control circuits on the second surface. The patterns of the third mask plate correspond to the patterns formed by the first control circuits.
And a step a4, fixing the first qubit layer and the second qubit layer on the control layer.
Specifically, based on the indium columns, the first qubit layer and the second qubit layer are fixed on the control layer in a flip-chip bonding mode, so that the quantum processor provided by any one of the embodiments is obtained.
One end of the coupler is grounded, the other end of the coupler is connected with the first superconducting qubit through an indium column, and the other end of the coupler is connected with the second superconducting qubit so as to couple the first qubit layer and the second qubit layer. The first superconducting qubit is one of a plurality of superconducting qubits in the first qubit layer, which is located in an edge area, and the second superconducting qubit is one of a plurality of superconducting qubits in the second qubit layer, which is located in an edge area.
The preparation method of the quantum processor provided by the invention can conveniently and efficiently prepare the quantum processor provided by any embodiment, and the problem that the performance of the quantum bit is not reduced while the number of physical bits is difficult to increase on one chip and the increase of a gate operation error channel caused by large-scale wiring is reduced can be solved by preparing the quantum processor in a modularized mode. The quantum processor with the modularized structure provided by the invention has essential difference from a quantum processor finished by a cross-refrigerator, so that the requirements on the performance of the refrigerator are reduced. In addition, each modularized quantum bit layer can be subjected to bit number design and wiring scheme with minimum error according to the scheme with optimal performance, and then each quantum bit layer is connected together by using the modularized structure provided by the invention, so that the problems of great reduction of bit performance and serious crosstalk caused by difficult wiring, which are easily caused by stacking a large number of superconducting quantum bits on a single quantum bit layer (chip), are reduced.
The invention also provides a quantum computer, which comprises the quantum processor provided by any embodiment.
Specifically, the quantum computer also comprises a microwave measurement and control instrument, a microwave cable, a refrigerator and a packaging box. The microwave measurement and control instrument mainly comprises a microwave source, a signal generator, an amplifier, a modulator, a mixer, an analyzer and the like, and is used for generating and controlling microwave pulses of microwave morphology, initializing, operating (such as quantum gate operation) and reading of quantum bit states can be achieved, and the microwave measurement and control instrument is also used for transmitting corresponding control signals and controlling the refrigerator to regulate temperature.
The microwave cable is a bridge connecting the microwave measurement and control instrument and the quantum processor and is responsible for transmitting control signals and reading signals. Because the control of the quantum bit in the quantum computation has extremely high requirements on the purity and the fidelity of the signal, the microwave cable must have extremely low signal attenuation, low noise, high stability and anti-interference capability. These cables typically employ special materials and designs (e.g., ultra low loss cables, coaxial cables) to accommodate low temperature environments, ensuring lossless transmission of quantum information.
Quantum computation needs to be performed in an extremely low temperature environment to reduce interference of thermal noise on quantum states and maintain quantum coherence. The refrigerator is used for providing a low-temperature environment, so that superconducting quantum bits and related equipment can work normally, and the performance of the refrigerator directly influences the stability of the quantum computer and the coherence time of the quantum bits.
The enclosure (or package) is the physical container of the quantum processor, providing protection for the superconducting qubits and associated circuitry. The enclosure is capable of withstanding extremely low temperatures, maintaining a vacuum or a specific gaseous environment, and minimizing electromagnetic interference. The package design also includes thermal management, microwave transmission path optimization, signal integrity, etc. to ensure reliable operation of the qubits. The packaging box comprises an interface for connecting superconducting qubits with the outside (such as a microwave cable and a reading cavity), so that the physical stability and the signal transmission efficiency of all connecting parts are ensured.
The quantum computer provided by the invention has the quantum processor provided by any one of the embodiments, so that the quantum computer has all the beneficial effects of the quantum processor provided by any one of the embodiments, and the detailed description is omitted.
Claims (19)
1. A quantum processor, the quantum processor comprising a plurality of qubit layers and a control layer;
The qubit layer comprises a first substrate layer and a plurality of superconducting qubits, wherein the plurality of superconducting qubits are positioned on a first surface of the first substrate layer and are coupled with each other;
The control layer comprises a second substrate layer and a plurality of first control lines, the plurality of first control lines are positioned on a second surface of the second substrate layer, the second surface and a third surface are connected through superconducting columns, wherein the plurality of first control lines are in one-to-one correspondence with superconducting qubits of the plurality of qubit layers, and the third surface is a surface, opposite to the first surface, of the first substrate layer;
The plurality of first substrate layers are arranged above the second surface at intervals, the first qubit layer and the second qubit layer are coupled through a coupler, the coupler is arranged on the first surface of the first substrate layer of the second qubit layer, one end of the coupler is grounded, the other end of the coupler is connected with a first superconducting qubit through the superconducting column, the other end of the coupler is connected with a second superconducting qubit so that the first qubit layer and the second qubit layer are coupled, the first qubit layer and the second qubit layer are two of the plurality of qubit layers, the first superconducting qubit is one of the plurality of superconducting qubits of the first qubit layer, and the second superconducting qubit is one of the plurality of superconducting qubits of the second qubit layer, and the first superconducting qubit is one of the superconducting qubit of the second qubit layer.
2. The quantum processor of claim 1, wherein the coupler comprises a first capacitance and a first superconducting quantum interferometer, the first capacitance and the first superconducting quantum interferometer being in parallel.
3. The quantum processor of claim 1 or 2, wherein the frequency of the first superconducting qubit, the frequency of the second superconducting qubit, and the frequency of the coupler are determined based on a preset effective coupling strength, wherein the preset effective coupling strength is a preset effective coupling strength between the first superconducting qubit and the second superconducting qubit.
4. A quantum processor as claimed in claim 3, wherein the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler are determined by the preset effective coupling strength and a first correspondence, wherein the first correspondence is used to characterize the correspondence between the effective coupling strength, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit and the frequency of the coupler.
5. The quantum processor of claim 4, wherein the first correspondence is represented by the formula:
Wherein, Representing the strength of the effective coupling in question,Representing the strength of the direct coupling between the first superconducting qubit and the second superconducting qubit,Representing the coupling strength between the first superconducting qubit and the coupler,Representing the coupling strength between the second superconducting qubit and the coupler,，Representing the frequency of the first superconducting qubit,Representing the frequency of the coupler,，Representing the frequency of the second superconducting qubit,，。
6. The quantum processor of claim 5, wherein the first superconducting qubit comprises a second capacitance and the second superconducting qubit comprises a third capacitance;
The said Is determined by the following formula:
Wherein, Representing the capacity of the second capacitor,Representing the capacity of said third capacitor,Representing the coupling capacities of the second capacitor and the third capacitor.
7. The quantum processor of claim 5, wherein the quantum processor isLess than or equal to 2MHz.
8. The quantum processor of claim 5, wherein the quantum processor is4GHz, said4.6GHz, said0.25MHz of the10MHz of the50MHz of theAnd determining based on the preset effective coupling strength.
9. The quantum processor of claim 3, wherein the frequency of the first superconducting qubit, the frequency of the second superconducting qubit, and the frequency of the coupler are determined based on a pre-set effective coupling strength and a pre-set residual parasitic coupling strength, wherein the pre-set residual parasitic coupling strength is a pre-set residual parasitic coupling strength between the first superconducting qubit and the second superconducting qubit.
10. The quantum processor of claim 9, wherein the frequency of the first superconducting qubit, the frequency of the second superconducting qubit, and the frequency of the coupler are determined by a preset effective coupling strength, a preset residual parasitic coupling strength, and a second correspondence, wherein the second correspondence is used to characterize the correspondence between the effective coupling strength, the residual parasitic coupling strength, the frequency of the first superconducting qubit, the frequency of the second superconducting qubit, and the frequency of the coupler.
11. The quantum processor of claim 10, wherein the second correspondence is represented by the formula:
Wherein, Representing an effective hamiltonian amount between the first superconducting qubit and the second superconducting qubit,Representing the frequency of the first superconducting qubit,Representing the frequency of the second superconducting qubit,A bubble operator representing the first superconducting qubit in the z direction,A bubble operator representing the second superconducting qubit in the z direction,A bubble operator representing the first superconducting qubit in the x-direction,A bubble operator representing the second superconducting qubit in the x-direction,Representing the strength of the effective coupling in question,Representing the strength of the remaining parasitic coupling,，Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesIs used to determine the eigenvalues of (c),Representing eigenstatesIs a constant value of (a) and (b).
12. The quantum processor of claim 11, wherein the quantum processor comprises4GHz, saidThe frequency of the coupler is determined based on the preset effective coupling strength and the preset residual parasitic coupling strength at 4.6 GHz.
13. The quantum processor of claim 1 or 2, wherein the material of the superconducting pillars is indium.
14. The quantum processor of claim 13, wherein the superconducting pillar is cylindrical, and the diameter of the superconducting pillar ranges from 30 μm to 50 μm.
15. The quantum processor of claim 14, wherein the height of the superconducting pillars ranges from 7 μιη to 9 μιη.
16. The quantum processor of claim 13, wherein the second surface and the third surface are flip-chip bonded based on the superconducting pillars.
17. The quantum processor of claim 1 or 2, wherein the control layer further comprises a second control line on a second surface of the second substrate layer, the second control line being disposed in correspondence with the coupler, the first control line and the second control line each comprising a magnetic flux control line, the magnetic flux control line of the first control line being for adjusting the frequency of the corresponding superconducting qubit, the magnetic flux control line of the second control line being for adjusting the frequency of the coupler.
18. A quantum processor as claimed in claim 1 or 2, wherein the first control line comprises a drive line for controlling the state of the superconducting qubit.
19. A quantum computer, comprising: a quantum processor as claimed in any one of claims 1 to 18.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410806083.7A CN118378710B (en) | 2024-06-21 | 2024-06-21 | Quantum processor and quantum computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410806083.7A CN118378710B (en) | 2024-06-21 | 2024-06-21 | Quantum processor and quantum computer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118378710A CN118378710A (en) | 2024-07-23 |
| CN118378710B true CN118378710B (en) | 2024-09-17 |
Family
ID=91902154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410806083.7A Active CN118378710B (en) | 2024-06-21 | 2024-06-21 | Quantum processor and quantum computer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118378710B (en) |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050250651A1 (en) * | 2004-03-29 | 2005-11-10 | Amin Mohammad H S | Adiabatic quantum computation with superconducting qubits |
| JP4913501B2 (en) * | 2006-08-15 | 2012-04-11 | 日本電信電話株式会社 | Quantum computing device and quantum entanglement control method |
| US10552755B2 (en) * | 2014-08-22 | 2020-02-04 | D-Wave Systems Inc. | Systems and methods for improving the performance of a quantum processor to reduce intrinsic/control errors |
| US9501748B2 (en) * | 2014-11-04 | 2016-11-22 | Northrop Grumman Systems Corporation | Mixed coupling between a qubit and resonator |
| EP3583626B1 (en) * | 2017-09-19 | 2023-09-06 | Google LLC | Pillars as stops for precise chip-to-chip separation |
| CN110738320B (en) * | 2019-10-11 | 2022-11-22 | 北京百度网讯科技有限公司 | Superconducting circuit structure, superconducting quantum chip and superconducting quantum computer |
| CN111967603B (en) * | 2020-09-01 | 2022-04-08 | 腾讯科技（深圳）有限公司 | Quantum chip, quantum processor and quantum computer |
| WO2022140674A1 (en) * | 2020-12-23 | 2022-06-30 | Rigetti & Co, Llc | Applying two-qubit quantum logic gates in a superconducting quantum processing unit |
| CN214378496U (en) * | 2021-03-09 | 2021-10-08 | 合肥本源量子计算科技有限责任公司 | Quantum chip |
| CN113206364B (en) * | 2021-04-29 | 2022-03-25 | 浙江大学 | Quantum signal circulator and quantum chip |
| CN115884665B (en) * | 2021-09-26 | 2024-09-03 | 腾讯科技（深圳）有限公司 | Quantum bit assembly preparation method, quantum bit assembly, quantum chip and device |
| WO2023174307A1 (en) * | 2022-03-15 | 2023-09-21 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip, method for preparing quantum chip, layout structure, and quantum computer |
| CN115438793B (en) * | 2022-07-29 | 2024-08-13 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip, preparation method thereof and quantum computer |
| CN115438792B (en) * | 2022-07-26 | 2024-07-16 | 本源量子计算科技（合肥）股份有限公司 | Layout structure and quantum chip |
| CN115438796B (en) * | 2022-03-15 | 2024-07-16 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip, preparation method thereof and quantum computer |
| CN114611704B (en) * | 2022-05-11 | 2022-10-25 | 苏州浪潮智能科技有限公司 | Quantum bit coupling method and structure |
| CN217982407U (en) * | 2022-07-29 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Quantum chip and quantum computer |
| WO2024058208A1 (en) * | 2022-09-16 | 2024-03-21 | 国立研究開発法人科学技術振興機構 | Quantum gate device, superconducting quantum gate device, quantum computer, and quantum gate operating method |
| CN116187461A (en) * | 2023-02-16 | 2023-05-30 | 合肥本源量子计算科技有限责任公司 | Bit structure, quantum chip, manufacturing method of quantum chip and quantum computer |
| CN117291272A (en) * | 2023-11-01 | 2023-12-26 | 中国科学院物理研究所 | Superconducting qubit chip and preparation method thereof |
| CN117454999A (en) * | 2023-11-10 | 2024-01-26 | 北京百度网讯科技有限公司 | Superconducting qubit coupling unit and superconducting quantum chip |
| CN117575034A (en) * | 2023-11-28 | 2024-02-20 | 山东云海国创云计算装备产业创新中心有限公司 | Quantum chip coupling strength control method and device and quantum chip |
| CN118095467A (en) * | 2024-01-15 | 2024-05-28 | 中国人民解放军战略支援部队信息工程大学 | Large-scale superconducting quantum chip based on two-dimensional array expansion and packaging structure |
| CN117808112B (en) * | 2024-03-01 | 2024-05-14 | 山东云海国创云计算装备产业创新中心有限公司 | Method and device for suppressing state leakage of superconducting quantum chip, chip and medium |
-
2024
- 2024-06-21 CN CN202410806083.7A patent/CN118378710B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN118378710A (en) | 2024-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7410975B2 (en) | quantum chips, quantum processors and quantum computers | |
| US10879446B2 (en) | Vertical flux bias lines coupled to vertical squid loops in superconducting qubits | |
| US10468578B2 (en) | Package substrates with top superconductor layers for qubit devices | |
| US10256206B2 (en) | Qubit die attachment using preforms | |
| US20190044044A1 (en) | Reducing crosstalk from flux bias lines in qubit devices | |
| Rosenberg et al. | Solid-state qubits: 3D integration and packaging | |
| CN112331693B (en) | Easily-expanded high-fidelity superconducting quantum chip structure and operation method | |
| US10665769B2 (en) | Quantum circuit assemblies with vertically-stacked parallel-plate capacitors | |
| US20200265334A1 (en) | Improved qubit designs for quantum circuits | |
| US12001922B2 (en) | Quantum circuit and quantum processor | |
| Maezawa et al. | Toward practical-scale quantum annealing machine for prime factoring | |
| US20190042967A1 (en) | Quantum circuit assemblies with josephson junctions utilizing resistive switching materials | |
| WO2019004991A1 (en) | Quantum computing assemblies | |
| WO2018231241A1 (en) | Low loss high isolation first level interconnects for qubit device packages | |
| Vozhakov et al. | State control in superconducting quantum processors | |
| EP4012628A1 (en) | Optical communication in quantum computing systems | |
| US20230409942A1 (en) | Applying Two-qubit Quantum Logic Gates in a Superconducting Quantum Processing Unit | |
| CN115994579B (en) | Two-bit gate circuit, superconducting chip, quantum computing system and control method | |
| US20240020562A1 (en) | Quantum computing systems with diabatic single flux quantum (sfq) readout for superconducting quantum bits | |
| CN118378710B (en) | Quantum processor and quantum computer | |
| CN114254754A (en) | Efficient pulse shaping for controlling multiple qubits with shared channel | |
| Riel | Quantum computing technology and roadmap | |
| Jia et al. | Superconducting and Silicon-Based Semiconductor Quantum Computers: A review | |
| AU2022450360A1 (en) | Connecting quantum processor chips in a modular quantum processing unit | |
| Ezratty | Is there a Moore's law for quantum computing? |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |