CN118265438A - Method for manufacturing magnetic memory cell - Google Patents
Method for manufacturing magnetic memory cell Download PDFInfo
- Publication number
- CN118265438A CN118265438A CN202211700769.5A CN202211700769A CN118265438A CN 118265438 A CN118265438 A CN 118265438A CN 202211700769 A CN202211700769 A CN 202211700769A CN 118265438 A CN118265438 A CN 118265438A
- Authority
- CN
- China
- Prior art keywords
- top electrode
- mtj
- hard mask
- metal hard
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- 239000010410 layer Substances 0.000 claims abstract description 44
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000011241 protective layer Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 12
- 238000005498 polishing Methods 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052715 tantalum Inorganic materials 0.000 claims description 8
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract 1
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- -1 less than about 3.9) Chemical compound 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Abstract
The invention provides a method for manufacturing a magnetic memory cell, which comprises the following steps: providing a substrate, wherein a bottom interconnection structure and an MTJ bottom electrode positioned on the bottom interconnection structure are formed on the substrate; forming a magnetic tunnel junction on the MTJ bottom electrode, wherein a metal hard mask is reserved at the top of the magnetic tunnel junction; depositing a protective layer and an interlayer medium; flattening the interlayer medium; etching back the interlayer dielectric and the protective layer to expose the surface and part of the side wall of the metal hard mask; forming a top electrode metal layer on the metal hard mask; etching the top electrode metal layer, the interlayer medium below the top electrode metal layer and the protective layer to form the MTJ top electrode. The invention improves the preparation process of the MTJ top electrode.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a method for manufacturing a magnetic memory cell.
Background
In recent years, a Magnetic Random Access Memory (MRAM) employing the magnetoresistive effect of a magnetic tunnel junction (MTJ, magnetic Tunnel Junction) is considered as a future solid-state nonvolatile memory, which has characteristics of high-speed reading and writing, large capacity, and low power consumption. The MTJ cell serves as a core component of the MRAM, and the basic structure includes a bottom electrode, an MTJ stack, and a top electrode.
In the process of forming interconnection with the MTJ top electrode, the conventional MTJ cell usually employs a Chemical Mechanical Polishing (CMP) method to expose a metal hard mask on top of the MTJ, and then deposits the MTJ top electrode metal. However, as MTJ cell dimensions continue to shrink, CMP planarization processes require a high removal selectivity between the metal hard mask on top of the MTJ cell and the dielectric to be planarized and ensure good uniformity. This puts a very high process requirement on the CMP process, which is difficult to implement.
Disclosure of Invention
In view of this, the present invention provides a method for manufacturing a magnetic memory cell, which improves the manufacturing process of the MTJ top electrode, reduces the process difficulty, and improves the process window.
The invention provides a method for manufacturing a magnetic memory cell, which comprises the following steps:
providing a substrate, wherein a bottom interconnection structure and an MTJ bottom electrode positioned on the bottom interconnection structure are formed on the substrate;
Forming a magnetic tunnel junction on the MTJ bottom electrode, wherein a metal hard mask is reserved at the top of the magnetic tunnel junction;
Depositing a protective layer and an interlayer medium;
flattening the interlayer medium;
etching back the interlayer dielectric and the protective layer to expose the surface and part of the side wall of the metal hard mask;
Forming a top electrode metal layer on the metal hard mask;
And photoetching a top electrode pattern, and etching the top electrode metal layer, the interlayer medium below the top electrode metal layer and the protective layer according to the top electrode pattern to form an MTJ top electrode.
Optionally, performing planarization treatment on the interlayer medium, including:
And measuring a pre-thickness value before polishing, determining polishing duration according to the polishing rate and the post-thickness value, and performing timing polishing.
Optionally, after exposing the metal hard mask, before forming the top electrode metal layer, the method further comprises: and performing in-situ plasma cleaning, dry photoresist removal and wet cleaning processes on the metal hard mask to remove polymer or metal oxide on the surface of the metal hard mask.
Alternatively, the metal hard mask may be a single layer structure formed of one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and ruthenium (Ru), or a combination of multiple layers.
Optionally, the material of the MTJ top electrode is one or a combination of more of tantalum, tantalum nitride, titanium, and titanium nitride.
Optionally, the material of the protective layer is polyethyl silicate (TEOS).
Optionally, the material of the interlayer dielectric is silicon oxide (SiO 2), silicon nitride (Si 3N4), or silicon oxynitride (SiON).
Optionally, the MTJ top electrode has a feature size that is larger than a feature size of the MTJ bottom electrode.
Optionally, after forming the MTJ top electrode, the method further includes: a top interconnect structure is formed.
According to the manufacturing method of the magnetic memory unit, when the MTJ top electrode is formed, the interlayer dielectric is firstly flattened through the CMP process, the metal hard mask is not required to be exposed, and then the metal hard mask at the top of the MTJ is opened through the etching process, so that the complexity of the CMP process is reduced, and the circulation speed of products is improved. And the etching speed is low and the condition of high selection is adopted for the etching of the top of the MTJ, so that the process window can be increased, and the loss of the metal hard mask can be reduced.
Drawings
FIG. 1 is a flow chart of a method for fabricating a magnetic memory cell according to an embodiment of the invention;
Fig. 2 to 9 are schematic cross-sectional views corresponding to steps of a method for manufacturing a magnetic memory cell according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, but it should be understood that these descriptions are only illustrative and are not intended to limit the scope of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
An embodiment of the present invention provides a method for manufacturing a magnetic memory cell, as shown in fig. 1, including the following steps:
s101, providing a substrate, wherein a bottom interconnection structure and an MTJ bottom electrode positioned on the bottom interconnection structure are formed on the substrate;
s102, forming a magnetic tunnel junction on an MTJ bottom electrode, wherein a metal hard mask is reserved at the top of the magnetic tunnel junction;
s103, depositing a protective layer and an interlayer medium;
S104, flattening the interlayer medium;
S105, etching back the interlayer dielectric and the protective layer to expose the surface and part of the side wall of the metal hard mask;
s106, forming a top electrode metal layer on the metal hard mask;
and S107, photoetching a top electrode pattern, and etching the top electrode metal layer and an interlayer medium and a protective layer below the top electrode metal layer according to the top electrode pattern to form an MTJ top electrode.
Fig. 2 through 8 are cross-sectional structural diagrams illustrating some stages of a method of manufacturing a magnetic memory cell according to an embodiment of the present invention. The steps are discussed in detail below.
In step S101, as shown in fig. 2, a substrate 200 is provided, on which a bottom interconnection structure is formed, in this embodiment, the substrate 200 may include a semiconductor material such as silicon, germanium, silicon germanium, various types of circuit patterns such as transistors, underlying metal wirings 2001, and the like are formed in advance on the silicon substrate. An etch stop layer, typically silicon nitride (SiN), is then formed as a stop layer for the etching process when the bottom via 2002 is subsequently formed. The bottom interconnect structure includes a bottom metal layer 2001 and a bottom via 2002, with the bottom interconnect structure being followed by an MTJ bottom electrode 2003. The thickness of the bottom electrode 2003 may be between 10 and 40nm. The bottom electrode 2003 may include tantalum nitride, tantalum, titanium nitride, titanium, and the like. An interlayer medium surrounds the bottom interconnection structure and the MTJ bottom electrode.
In step S102, as shown in FIG. 3, a magnetic tunnel junction 201 is formed on the MTJ bottom electrode 2003, with a metal hard mask 202 remaining on top of the magnetic tunnel junction 201. The implementation method of the steps is generally as follows: sequentially depositing a multi-layer film and a metal hard mask of the magnetic tunnel junction, then patterning the metal hard mask, and then etching the multi-layer film of the magnetic tunnel junction by using the metal hard mask as an etching mask, for example, using an Ion Beam Etching (IBE) process, thereby obtaining the magnetic tunnel junction. The magnetic tunnel junction 201 has a laminated structure including at least a free layer, a barrier layer, and a reference layer. The metal hard mask 202 may have a single layer structure, and the material may be selected from one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and ruthenium (Ru). The metal hard mask 202 may also have a multi-layer structure, and each layer may be formed of a material selected from one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and ruthenium (Ru), and the multi-layer materials may be combined. The thickness of the metal hard mask 202 may be 30-60 nm.
In step S103, as shown in fig. 4, a protective layer 203 and an interlayer dielectric 204 are deposited. The protection layer 203 conformally covers the magnetic tunnel junction 201 and the surface of the metal hard mask 202. The protective layer 203 is used to protect the magnetic tunnel junction 201 from oxidation. The protective layer 203 may comprise silicon oxide or a low-k dielectric material having a dielectric constant less than silicon oxide (i.e., less than about 3.9), such as, for example, polyethyl silicate (TEOS). The interlayer dielectric 204 is used to fill the gap between the pillar-shaped adjacent magnetic tunnel junctions. In this embodiment, different materials are used for the interlayer dielectric 204 and the protective layer 203. For example, the material of the interlayer dielectric 204 may be silicon oxide (SiO 2), silicon nitride (Si 3N4), or silicon oxynitride (SiON). The protective layer 203 and the interlayer dielectric 204 are preferably deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD), physical Vapor Deposition (PVD), or electron beam evaporation process.
In step S104, as shown in fig. 5, planarization processing is performed on the interlayer dielectric 204. The step is just to grind the interlayer dielectric flat, and does not need to grind to the metal hard mask, and then the top of the metal hard mask is opened by etching the top of the MTJ.
In step S105, as shown in fig. 6, the interlayer dielectric 204 and the protective layer 203 are etched back so that the metal hard mask 202 exposes the surface and a portion of the sidewall thereof. The interlayer dielectric 204a and the protective layer 203a remaining after etching have a height lower than the surface of the metal hard mask 202. Preferably, the metal hard mask 202 may have a convex spherical contact surface, thereby increasing the contact area with the MTJ top electrode.
This etching is performed according to the etching selectivity of the interlayer dielectric 204, the protective layer 203 and the metal hard mask 202, and the top of the etched metal hard mask is raised, and the MTJ protective layers and the interlayer dielectric at the top and side portions are etched away, depending on the content of the etching menu. Preferably, the etching rate is slower and the condition with higher etching rate is selected, so that the process window can be increased and the HMloss can be reduced.
It is noted here that after etching back the interlayer dielectric 204 and the protective layer 203, the interlayer dielectric and the protective layer between adjacent memory cells are not etched away.
In addition, in order to make the metal hard mask 202 have a convex spherical contact surface, the etching further includes: the metal hard mask 202 is subjected to processes such as in-situ plasma cleaning, dry photoresist removal, wet cleaning and the like, and polymers or metal oxides on the surface of the metal hard mask are removed, so that lower contact resistance is obtained. CHF 3 or CF 4 is preferably used as the dry etching gas.
In step S106, as shown in fig. 7, a top electrode metal layer 205 is formed on the metal hard mask 202. The material of the top electrode metal layer 205 may be one or a combination of tantalum, tantalum nitride, titanium, and titanium nitride. The top electrode metal layer 205 is preferably formed using metal physical vapor deposition.
In step S107, as shown in fig. 8, a top electrode pattern is etched, and the MTJ top electrode 205a is formed by etching the top electrode metal layer 205 and the interlayer dielectric 204a and the protective layer 203a thereunder according to the top electrode pattern. The feature size of the top electrode 205a depends on the mask used, and in this embodiment the feature size of the MTJ top electrode 205a is larger than the feature size of the MTJ bottom electrode 2003.
Further, after forming the MTJ top electrode 205a, as shown in fig. 9, it further includes: a top interconnect structure is formed. In this embodiment, the top interconnect structure includes a top via 206 and a top metal layer 207. This step may be achieved using conventional processes, such as by a dual damascene process.
According to the manufacturing method of the magnetic memory unit, when the MTJ top electrode is formed, the interlayer dielectric is firstly ground flat through the CMP process, the metal hard mask is not required to be exposed, and then the metal hard mask at the top of the MTJ is opened through the etching process, so that the complexity of the CMP process is reduced, and the circulation speed of products is improved. And the etching speed is low and the condition of high selection is adopted for the etching of the top of the MTJ, so that the process window can be increased, and the loss of the metal hard mask can be reduced.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (9)
1. A method of manufacturing a magnetic memory cell, comprising:
providing a substrate, wherein a bottom interconnection structure and an MTJ bottom electrode positioned on the bottom interconnection structure are formed on the substrate;
Forming a magnetic tunnel junction on the MTJ bottom electrode, wherein a metal hard mask is reserved at the top of the magnetic tunnel junction;
Depositing a protective layer and an interlayer medium;
flattening the interlayer medium;
etching back the interlayer dielectric and the protective layer to expose the surface and part of the side wall of the metal hard mask;
Forming a top electrode metal layer on the metal hard mask;
And photoetching a top electrode pattern, and etching the top electrode metal layer, the interlayer medium below the top electrode metal layer and the protective layer according to the top electrode pattern to form an MTJ top electrode.
2. The method of claim 1, wherein planarizing the interlayer dielectric comprises:
And measuring a pre-thickness value before polishing, determining polishing duration according to the polishing rate and the post-thickness value, and performing timing polishing.
3. The method of claim 1, wherein after exposing the metal hard mask, prior to forming a top electrode metal layer, the method further comprises: and performing in-situ plasma cleaning, dry photoresist removal and wet cleaning processes on the metal hard mask to remove polymer or metal oxide on the surface of the metal hard mask.
4. The method of claim 1, wherein the metal hard mask is a single-layer structure or a combination of layers formed of one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and ruthenium (Ru).
5. The method of claim 1, wherein the material of the MTJ top electrode is one or more of tantalum, tantalum nitride, titanium, and titanium nitride.
6. The method of claim 1, wherein the material of the protective layer is polyethyl silicate (TEOS).
7. The method of claim 1, wherein the material of the interlayer dielectric is silicon oxide (SiO 2), silicon nitride (Si 3N4), or silicon oxynitride (SiON).
8. The method of claim 1, wherein a characteristic dimension of the MTJ top electrode is greater than a characteristic dimension of the MTJ bottom electrode.
9. The method of claim 1, further comprising, after forming the MTJ top electrode: a top interconnect structure is formed.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211700769.5A CN118265438A (en) | 2022-12-26 | 2022-12-26 | Method for manufacturing magnetic memory cell |
| PCT/CN2023/134816 WO2024139948A1 (en) | 2022-12-26 | 2023-11-28 | Manufacturing method for magnetic storage unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211700769.5A CN118265438A (en) | 2022-12-26 | 2022-12-26 | Method for manufacturing magnetic memory cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118265438A true CN118265438A (en) | 2024-06-28 |
Family
ID=91604109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211700769.5A Pending CN118265438A (en) | 2022-12-26 | 2022-12-26 | Method for manufacturing magnetic memory cell |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN118265438A (en) |
| WO (1) | WO2024139948A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109087996A (en) * | 2017-06-14 | 2018-12-25 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM top electrode groove |
| CN111668368B (en) * | 2019-03-08 | 2023-12-29 | 上海磁宇信息科技有限公司 | Preparation method of pseudo-magnetic tunnel junction unit structure |
| CN111697132A (en) * | 2019-03-12 | 2020-09-22 | 中电海康集团有限公司 | Planarization method of MRAM device |
| CN113948631A (en) * | 2020-07-17 | 2022-01-18 | 浙江驰拓科技有限公司 | Preparation method of storage bit and preparation method of MRAM |
| CN111933791A (en) * | 2020-09-07 | 2020-11-13 | 浙江驰拓科技有限公司 | Magnetic random access memory device and method of manufacturing the same |
-
2022
- 2022-12-26 CN CN202211700769.5A patent/CN118265438A/en active Pending
-
2023
- 2023-11-28 WO PCT/CN2023/134816 patent/WO2024139948A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024139948A1 (en) | 2024-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI605569B (en) | Dummy bottom electrode in interconnect to reduce cmp dishing | |
| CN109585646B (en) | Memory device and method of manufacturing the same | |
| TWI579998B (en) | Semiconductor device and method for manufacturing the same | |
| KR102295994B1 (en) | Via landing enhancement for memory device | |
| US9728540B2 (en) | Semiconductor device for reducing coupling capacitance | |
| JP2010524258A (en) | Method of manufacturing a self-aligned damascene memory structure | |
| WO2022048084A1 (en) | Magnetic random access memory device and manufacturing method therefor | |
| TWI776362B (en) | Memory cell and manufacturing method thereof | |
| CN111106237B (en) | Integrated chip and forming method thereof | |
| TWI694622B (en) | Embedded mram in interconnects and method for producing the same | |
| JP2002076142A (en) | Method for forming charge storage electrode of capacitor | |
| US8026604B2 (en) | Semiconductor devices having contact holes including protrusions exposing contact pads | |
| CN111261773A (en) | Semiconductor memory element and manufacturing method thereof | |
| WO2022048083A1 (en) | Magnetic random access memory device and method for manufacturing same | |
| CN107808882A (en) | Semiconductor integrated circuit structure and preparation method thereof | |
| US11195994B2 (en) | Method for fabricating semiconductor device including embedded magnetic resistance random access memory | |
| CN110890461B (en) | Manufacturing method of embedded magnetic resistance random access memory | |
| US9029216B1 (en) | Memory and manufacturing method thereof | |
| CN118265438A (en) | Method for manufacturing magnetic memory cell | |
| US8598677B2 (en) | Semiconductor device including metal lines | |
| US6780763B2 (en) | Method for fabricating semiconductor device capable of improving gap-fill property | |
| CN117412605B (en) | Trench semiconductor memory device and method of manufacturing the same | |
| KR100685531B1 (en) | Method of formming a metal line in semiconductor device | |
| US20220344579A1 (en) | Semiconductor memory device and fabrication method thereof | |
| CN109801938B (en) | Contact opening structure, manufacturing method and application thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |