CN117475013B - Computer equipment and video data processing method - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T9/00—Image coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
- H04N7/181—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast for receiving images from a plurality of remote sources
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Television Signal Processing For Recording (AREA)
Abstract
The embodiment of the application provides a computer device and a video data processing method, wherein a graphic acceleration card in the computer device is utilized to decode and scale multi-path video stream data, a display card only decodes part of video stream data, and as the display card renders the scaled thumbnail-image data, the thumbnail-image data and part of video stream data decoded by the display card, the resolution of the thumbnail-image data is smaller than that of the video stream data, so that the data volume of the video stream data which is required to be rendered is reduced when the display card renders under the same condition, the number of paths of the video stream data which is required to be rendered by the display card can be increased, the situation that a picture is blocked when a plurality of pictures are played is greatly reduced, and the efficiency of picture display is improved.
Description
Technical Field
The present application relates to the field of video encoding and decoding and graphics processing technologies, and in particular, to a computer device and a video data processing method.
Background
Currently, there are more and more scenes in which multiple video data are displayed on one screen at the same time, for example, a monitoring screen of a cell and a monitoring screen of a mall. That is, the multi-channel monitoring video needs to be encoded, decoded and rendered under the security scene, and finally displayed on the computer display screen. However, the current low-end common PC (Personal Computer) can only meet the common office scene, and the situation that the decoding rendering capability is weak is commonly existed, so that the playing requirement can not be met under the multi-picture video playing scene, and the multi-picture playing can be carried out, and the clamping and the stopping can occur.
Disclosure of Invention
The embodiment of the application aims to provide a computer device and a video data processing method, so as to reduce the situation of blocking when multi-picture playing is realized in a security scene. The specific technical scheme is as follows:
In a first aspect of the application, there is provided a computer device, the device comprising: the system comprises a main board, a display card, a graphic accelerator card, a display and storage equipment;
the main board comprises: a CPU, a computer expansion bus standard PCIE bus, two PCIE slots; one PCIE slot is inserted with a display card, and the other PCIE slot is inserted with a graphic acceleration card; the PCIE bus is used for realizing the electrical connection between each PCIE slot and the CPU;
The storage device is pre-stored with decoding information for representing the decoding performance of the graphic accelerator card; the CPU is used for responding to a display instruction generated by the video monitoring program for N paths of video stream data with first preset resolution, reading the decoding information from the storage device, sending M paths of video stream data to the graphic accelerator card according to the decoding information, and sending N-M paths of video stream data to the display card, wherein M is not more than N, and the decoding capability of decoding the M paths of video stream data is not more than the decoding capability corresponding to the decoding information;
The graphics accelerator card is used for receiving the M paths of video stream data and decoding the M paths of video stream data to obtain first decoded graphics data; scaling the first decoded graphic data to a second preset resolution to obtain thumbnail-shaped data, and sending the thumbnail-shaped data to the CPU so that the CPU sends the received thumbnail-shaped data to the display card; the first preset resolution is greater than the second preset resolution;
The display card is used for receiving the N-M paths of video stream data and the thumbnail image data, and decoding the N-M paths of video stream data to obtain second decoded graphic data; rendering the second decoded graphic data and the thumbnail graphic data to obtain a rendered graphic corresponding to the N paths of video stream data; splicing rendering graphics corresponding to the N paths of video stream data to obtain spliced graphics; and controlling the display to display the spliced graph.
In one possible implementation manner, the sending the M paths of video stream data to the graphics accelerator card according to the decoding information includes:
Determining the number Z of paths of video stream data which can be decoded at most and corresponds to the decoding information, and taking the number Z as M;
And sending the M paths of video stream data to the graphic accelerator card.
In one possible implementation manner, the storage device is further configured to correspondingly store a specification model of each graphics card and capability information of the graphics card, where the capability information is used to represent decoding capability and rendering capability of the graphics card;
The CPU is also used for acquiring the specification model of the display card as a target specification model; searching the capacity information stored corresponding to the target specification model in the storage equipment by taking the target specification model as an index, and taking the capacity information as target capacity information;
Determining residual rendering capability according to the rendering capability represented by the target capability information, wherein the residual rendering capability is a difference value between the rendering capability represented by the target capability information and first rendering capability, and the first rendering capability is the rendering capability required for rendering thumbnail data obtained by Z-path video stream data scaling;
determining a path number Y of second decoded graphic data which can be rendered at most by the residual rendering capability;
Determining the sum of the Y and the Z as the maximum number of paths;
the video monitoring program is used for determining N which is not more than the maximum number of paths and selecting N paths of video stream data with first preset resolution; and sending a display instruction to the CPU aiming at the selected video stream data.
In one possible implementation manner, the video monitoring program determines N not greater than the maximum number of paths, and selects N paths of video stream data with a first preset resolution, including:
Responding to a video stream selection instruction, and identifying the number T of paths of video stream data selected by the selection instruction;
if the T is not greater than the maximum number of paths, sending a display instruction to the CPU aiming at the video stream data selected by the selection instruction;
the video monitoring program is further used for alarming if the T is larger than the maximum number of paths.
In one possible implementation, the graphics accelerator card includes a plurality of processing chips therein; the graphics accelerator card maintains performance information representing the remaining performance of the plurality of processing chips and an identification of the processing chip; the CPU sends M paths of video stream data to the graphic acceleration card according to the decoding information, and the CPU comprises the following steps:
Determining a processing chip with residual performance capable of finishing decoding M paths of video data as a target processing chip according to the M, the performance information and the identification of the processing chip;
m paths of video stream data are sent to the target processing chip;
The graphic acceleration card is also used for updating the performance information of the target processing chip after receiving the video stream data;
the graphics accelerator card is configured to receive the M paths of video stream data, and decode the M paths of video stream data to obtain decoded graphics data, and includes:
And the graphic accelerator card is used for decoding the M paths of video stream data through the target processing chip to obtain decoded graphic data.
In one possible implementation manner, the sending M paths of video stream data to the target processing chip includes:
sequentially determining a processing chip with highest residual performance for each path of video stream data in the M paths of video stream data as a target processing chip;
and sending the video stream data to the target processing chip.
In a possible implementation manner, the graphics accelerator card is further configured to identify decoded graphics data of each frame obtained by decoding;
Responding to a screenshot instruction aiming at a target rendering graph, and determining an identification of decoding graph data based on which the target rendering graph is obtained by rendering by the video control program as a target identification;
The video control program controls the CPU to send the target identifier to the graphic acceleration card;
and the graphic acceleration card determines decoding graphic data represented by the target identifier, codes the decoding graphic data, obtains a screenshot file and sends the screenshot file to the CPU.
In a second aspect of the present application, a video data processing method is provided, which is applied to a computer device, a motherboard, a graphics card, a graphics accelerator card, a display, and a storage device; the main board comprises: a CPU, a computer expansion bus standard PCIE bus, two PCIE slots; one PCIE slot is inserted with a display card, and the other PCIE slot is inserted with a graphic acceleration card; the PCIE bus is used for realizing the electrical connection between each PCIE slot and the CPU; the storage device is pre-stored with decoding information for representing the decoding performance of the graphic accelerator card; the CPU is deployed with a video monitoring program; the method comprises the following steps:
The CPU responds to a display instruction input by the video monitoring program for N paths of video stream data with first preset resolution, generates a display instruction, reads the decoding information from the storage device, sends M paths of video stream data to the graphic acceleration card according to the decoding information, and sends N-M paths of video stream data to the display card, wherein M is not more than N, and the decoding capability of decoding the M paths of video stream data is not more than the decoding capability corresponding to the decoding information;
the graphics accelerator card decodes the received M paths of video stream data to obtain first decoded graphics data;
The graphic accelerator card scales the first decoded graphic data to a second preset resolution to obtain thumbnail data, and sends the thumbnail data to the CPU, wherein the second preset resolution is smaller than the first preset resolution; the first preset resolution is greater than the second preset resolution;
The CPU sends the received thumbnail-form data to the display card;
the display card decodes the received N-M paths of video stream data and the thumbnail image data to obtain second decoded graphic data; rendering the second decoded graphic data and the thumbnail graphic data to obtain a rendered graphic corresponding to the N paths of video stream data; splicing rendering graphics corresponding to the N paths of video stream data to obtain spliced graphics; and controlling the display to display the spliced graph.
In a third aspect of the present application, there is provided an electronic device comprising:
a memory for storing a computer program;
a processor configured to implement the method according to any one of the second aspect when executing the program stored in the memory.
In a fourth aspect of the application, there is provided a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the method of any of the second aspects above.
The embodiment of the application has the beneficial effects that:
The embodiment of the application provides a computer device and a video data processing method, wherein the device comprises the following steps: the system comprises a main board, a display card, a graphic accelerator card, a display and storage equipment; the main board comprises: a CPU, a computer expansion bus standard PCIE bus, two PCIE slots; one PCIE slot is inserted with a display card, and the other PCIE slot is inserted with a graphic acceleration card; and the PCIE bus is used for realizing the electric connection between each PCIE slot and the CPU. In this embodiment, the graphics accelerator card in the computer device is used to decode and scale the multiple paths of video stream data, and the graphics card only decodes part of the video stream data, because the graphics card renders the scaled thumbnail-shaped data and part of the video stream data decoded by the graphics card, and the resolution of the thumbnail-shaped data is smaller than that of the video stream data, under the same condition, the data volume of the video stream data received by the graphics card during rendering is reduced, so that the number of paths of the video stream data rendered by the graphics card can be increased, the situation that the picture is blocked when the multiple pictures are played is greatly reduced, and the efficiency of picture display is improved.
Of course, it is not necessary for any one product or method of practicing the application to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and other embodiments may be obtained according to these drawings to those skilled in the art.
Fig. 1 is a schematic view of a scenario in which a prior art PC side carries a graphics card according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a computer device according to an embodiment of the present application;
FIG. 3 is a schematic diagram of connection among a CPU, a graphics card and a graphics accelerator card according to an embodiment of the present application;
Fig. 4 is a schematic diagram of a transmission process of video stream data according to an embodiment of the present application;
fig. 5 is a schematic diagram of displaying multiple video stream data according to an embodiment of the present application;
fig. 6 is a schematic diagram of a process of splicing and displaying 16 paths of video stream data according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a processing chip in a graphics accelerator card according to an embodiment of the present application;
FIG. 8 is a diagram illustrating a process of capturing a graphic screenshot according to an embodiment of the present application;
fig. 9 is a schematic diagram of a video data processing apparatus according to an embodiment of the present application;
Fig. 10 is a schematic flow chart of a video data processing method according to an embodiment of the present application;
Fig. 11 is a schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.
PCIE: PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard originally named "3GIO", proposed by Intel in 2001, intended to replace the old PCI, PCI-X (an updated version of PERIPHERAL COMPONENTS INTERCONNECT) and AGP (ACCELERATE GRAPHICAL Port) bus standards.
RC: the Root Complex, RC equipment is used for connecting CPU/memory subsystem and I/O equipment. In the embodiment of the application, the RC equipment is a PC host.
EP: endPoint, EP device generally represents a serial or I/O device. In an embodiment of the application, the EP device is a graphics accelerator card.
SDK is a software development program package for controlling decoding of graphic acceleration card, and the program package is run on PC, and utilizes instruction to control EP coding and decoding action.
ISC: iSecureCenter, a comprehensive security protection platform, an ISC platform refers to a digital video monitoring platform, and the platform is a comprehensive security protection monitoring platform integrating functions of video monitoring, security early warning, video interaction, passenger flow analysis, intelligent analysis and the like.
In the prior art, in the scene of a video card carried on a PC end, as shown in fig. 1, video stream data is decoded and rendered by the video card and then displayed on a screen, decoding and rendering display are completed by the video card, movie watching or video watching of a traditional scene can be relatively smooth, if multi-channel video playing of a security scene is carried out, the overall performance can be influenced no matter whether decoding or rendering is carried out, and playing is blocked.
Based on this, an embodiment of the present application provides a computer apparatus, as shown in fig. 2, including: the system comprises a main board, a display card, a graphic accelerator card, a display and storage equipment; the main board comprises: the CPU, the computer expands the bus standard PCIE bus, two PCIE slot, is PCIE slot 1 and PCIE slot 2 separately; one PCIE slot is inserted with a display card, and the other PCIE slot is inserted with a graphic acceleration card; the PCIE bus is used for realizing the electrical connection between each PCIE slot and the CPU; the storage device is pre-stored with decoding information for representing the decoding performance of the graphic accelerator card; the CPU is deployed with a video monitor program.
And the CPU is used for responding to the display instruction generated by the video monitoring program for N paths of video stream data with the first preset resolution, reading the decoding information from the storage equipment, sending M paths of video stream data to the graphic accelerator card according to the decoding information, and sending N-M paths of video stream data to the display card, wherein M is not more than N, and the decoding capability of decoding the M paths of video stream data is not more than the decoding capability corresponding to the decoding information.
The graphics accelerator card is used for receiving M paths of video stream data, and decoding the M paths of video stream data to obtain first decoded graphics data; scaling the first decoded graphic data to a second preset resolution to obtain thumbnail-shaped data, and sending the thumbnail-shaped data to a CPU (central processing unit) so that the CPU sends the received thumbnail-shaped data to the display card; the first preset resolution is greater than the second preset resolution.
The display card is used for receiving the N-M paths of video stream data and the thumbnail image data, and decoding the N-M paths of video stream data to obtain second decoded graphic data; rendering the second decoded graphic data and the thumbnail graphic data to obtain a rendered graphic corresponding to the N paths of video stream data; splicing rendering graphics corresponding to the N paths of video stream data to obtain spliced graphics; and controlling the display to display the spliced graph.
In the embodiment of the application, the connection among the CPU, the display card and the graphic accelerator card is shown in fig. 3, and the transmission process of video stream data is shown in fig. 4. The main board comprises a CPU, the CPU is used for controlling the display card and the graphic acceleration card, and the CPU is used for controlling the GPU in the display card in the process of processing data of the display card, so that in the embodiment of the application, the display card is used for referring to the operation executed by the GPU. The CPU is deployed with a video monitoring program, the video monitoring program software development program package SDK is operated on the computer equipment to realize deployment, and then the video monitoring program is used for controlling the graphic acceleration card to decode, manage chips and count resources. The graphics acceleration card utilizes a linux kernel driver to ensure a PCIE communication link, performs hardware decoding according to commands issued by a video monitoring program, performs graphics analysis processing, reduces the hardware pressure of a PC end, and supports coding capture, fish eye expansion and the like besides a decoding function.
In the video stream data of the N paths of first preset resolutions, N is larger than 1, and the first preset resolutions are larger than a preset resolution threshold. That is, in the embodiment of the present application, the video stream data with multiple paths of resolutions greater than the preset resolution threshold is spliced and displayed. That is, in the embodiment of the present application, the resolution of the video stream data input into the computer device, which is referred to later, is greater than the preset resolution threshold. The preset resolution threshold is set by those skilled in the art according to the actual application scenario, and resolutions greater than the preset resolution threshold often refer to those high resolutions, such as 1080p,4k, etc.
In the application scenario shown in fig. 5, a spliced display picture is displayed, wherein the source of the spliced picture is under a main preview frame in the display interface, wherein the name of a folder can be a date, and also can be the longitude and latitude of a specific area, which is not described herein, the source of an image in the display interface is under the folder, and Camera1 and Camera2 are the sources of the image in the display picture. The display interface has other functions, and tools for realizing the other functions are in the toolbar 1, which are not described herein. If the technician or the client wants to splice and display the N paths of video stream data, a request instruction is sent to the computer equipment, and after the computer equipment receives the request instruction, the video monitoring program generates a display instruction for the N paths of video stream data with the first preset resolution, so that the CPU executes subsequent steps according to the display instruction.
The N-way video stream data are not necessarily transmitted by different photographing apparatuses, and the N-way video stream data may be transmitted from one photographing apparatus, for example, one-way video stream data is divided into 16 ways, to obtain 16-way video stream data. The N paths of video stream data can also be obtained by sending by other computer devices. The source of the N-path video stream data is not limited in the embodiment of the present application.
The decoding information of the decoding performance of the graphics accelerator card is used to characterize the decoding capability of the graphics accelerator card. The CPU can determine whether all the received N paths of video stream data with the first preset resolution are decoded by the graphics accelerator card according to the decoding information.
In the embodiment of the application, since N paths of video stream data are sent to the graphics accelerator card for decoding, M is not more than N. When M is equal to N, the decoding performance of the graphics accelerator card is described as being capable of decoding N-way video stream data. N paths of video stream data with first preset resolution are all sent to the graphic accelerator card, and all N paths of video stream data are decoded by the graphic accelerator card. And when M is smaller than N, the decoding performance of the graphic accelerator card is indicated that N paths of video stream data can not be decoded, the N paths of video stream data with the first preset resolution are sent to the graphic accelerator card, and the N-M paths of video stream data are sent to the display card. M paths of video stream data are decoded by the graphic accelerator card, and N-M paths of video stream data are decoded by the display card.
In the embodiment of the application, in order to reduce the possibility of blocking to a greater extent, the received N paths of video stream data can be preferentially sent to the graphic accelerator card for decoding. Since the video card has decoding performance and rendering performance, the video stream data needs to be rendered by using the video card before the video stream data is displayed on the display. If the graphics accelerator card decodes preferentially, the subsequent graphics accelerator card will scale the video stream data decoded by the graphics accelerator card. Therefore, for the same number of paths of decoded video stream data, the thumbnail-shaped data scaled by the graphic accelerator card is much smaller than the data size of the decoded video stream data decoded by the display card, so that the display card can render more paths of video stream data, and the possibility of blocking is greatly reduced.
The graphic accelerator card scales the decoded image data, and the second preset resolution is the resolution of each path of image corresponding to the final display instruction during display. The second preset resolution is smaller than the first preset resolution.
When the display card performs rendering, the received image data is rendered, the display card does not distinguish which is the thumbnail image data and which is not the thumbnail image data, and only the image data is received, the rendering can be directly performed. The resolution of the image data before rendering is the same as the resolution of the image after rendering.
As shown in fig. 6, for example, it is assumed that the resolution of 16-way video stream data isFinally, 16 paths of spliced videos to be presented are previewed, and the resolution of video stream data of each path of display window is/>. Let the 16-way resolution be/>All video stream data of the video stream are decoded by the graphic accelerator card, and the graphic accelerator card will/>, after decoding is completedIs scaled to/>Thus, when the display card is rendered, only rendering/>The thumbnail image data of (a) is sufficient. Whereas the graphics card in the prior art decodes/>Does not perform a scaling operation but directly decodes/>The decoded image data of (2) is directly rendered, then scaled and displayed, and the display card is also rendered/>, when renderingIs provided. Therefore, in the same situation, in the case of the graphics accelerator card, the graphics card can render more paths of image data.
The rendering image corresponding to the N paths of video stream data is an N path rendering image corresponding to the N paths of video stream data, wherein M paths of rendering images are rendering images with second preset resolution, N-M paths of rendering images with first preset resolution, and the rendering images with first preset resolution can be spliced and displayed only after being scaled to the second preset resolution after being rendered.
Exemplary, assuming N is 16, M is 10, the first predetermined resolution isThe second preset resolution is/>Then 10-way rendered image is/>The 6-way rendered image is/>When the display is spliced, the 6 paths/>, are displayedIs scaled to/>Finally, 16 paths are usedIs displayed in a spliced manner.
In one possible embodiment, since the graphics accelerator card scales the received video stream data to thumbnail image data having a resolution smaller than the resolution of the received video stream data, the graphics accelerator card may be prioritized to decode the video stream data in order to render more paths of video stream data, and the CPU may transmit M paths of video stream data to the graphics accelerator card according to the decoding information, including:
S201, determining the number Z of paths of video stream data that can be decoded at most with the decoding capability corresponding to the decoding information, as M.
In this step, the decoding information includes the information of the decoding capability of the graphics accelerator card, and the display card can determine the maximum number of paths of video stream data that the decoding card can decode according to the decoding information. Z may be equal to N, Z may be less than N, and Z may not be greater than N. And the method is specifically determined according to decoding information of the graphic accelerator card and N paths of video stream data in an actual application scene.
S202, sending M paths of video stream data to a graphic accelerator card.
In this embodiment, video stream data that can be decoded by the graphics accelerator card most is preferentially sent to the graphics accelerator card for decoding according to decoding information of the graphics accelerator card, and decoding is preferentially performed by using the graphics accelerator card, so that decoding pressure of the graphics accelerator card can be greatly reduced, and the graphics accelerator card can scale decoded image data to obtain thumbnail image data with resolution smaller than that of the decoded image data, so that the number of rendering paths can be increased when the graphics accelerator card is rendering.
Since the decoding capability and rendering capability of the graphics cards on the market are different, in order to better distribute and decode the video stream data, the rendering pressure of the graphics cards is reduced, and the storage device is further configured to correspondingly store the specification model of each graphics card and the capability information of the graphics card, where the capability information is used to indicate the decoding capability and rendering capability of the graphics card.
The capability information is recorded with decoding capability and rendering capability for representing each display card, and the CPU can determine the decoding capability and rendering capability of the display card according to the specification and model of the display card. The decoding capability of the graphics card may be quantized to the product of the number of decoding passes and the resolution of the decoded image data. For example, the decoding capability of the graphics card isIndicating that the total amount of decoding of the graphics card is not more than/>Is a digital image of the image data; the rendering capability of the graphics card may be quantified as the product of the number of rendering passes and the resolution of the rendered image data. For example, the rendering capability of the graphics card is/>Indicating that the total rendering amount of the graphics card is not more than/>Is described.
Based on this, in one possible embodiment,
The CPU is also used for acquiring the specification model of the display card as a target specification model; searching the capability information stored corresponding to the target specification model in the storage equipment by taking the target specification model as an index, and taking the capability information as target capability information;
Determining residual rendering capability according to the rendering capability represented by the target capability information, wherein the residual rendering capability is a difference value between the rendering capability represented by the target capability information and first rendering capability, and the first rendering capability is required rendering thumbnail data obtained by Z-path video stream data scaling;
In this step, the first rendering capability is the rendering capability required by the graphics accelerator card to render the maximum number of thumbnail images available to the graphics accelerator card, and, for example, assuming that the graphics accelerator card can decode 14 paths of video stream data, the first rendering capability is the rendering capability required by the graphics accelerator card to scale the 14 paths of thumbnail images obtained by the 14 paths of decoded video stream data.
Determining a path number Y of second decoded graphic data which can be rendered at most by the residual rendering capability;
In this step, assuming that the rendering capability indicated by the target capability information of the graphics card is a capability capable of rendering 12 paths 1080P video stream data, the first preset resolution is 1080P, the second preset resolution is 540P, the graphics accelerator card obtains 14 paths 540P thumbnail images, the capability of rendering 7 paths 1080P video stream data in the first rendering capability is required by calculation, and the remaining rendering capability is a capability of rendering 5 paths 1080P video stream data. The display card can decode the 5-path 1080P video stream data and render the data by the display card.
And determining the sum of Y and Z as the maximum number of paths.
In this step, the maximum number of ways is the maximum number of ways of video stream data that can be rendered on the graphics card. Wherein, Z way is the thumbnail image data scaled by the graphic accelerator card, Y way is the second decoded graphic data decoded by the graphic card.
The video monitoring program is used for determining N which is not more than the maximum number of paths and selecting N paths of video stream data with first preset resolution; and sending a display instruction to the CPU aiming at the selected video stream data.
In this step, N is not greater than the maximum number of channels, which indicates that all of the N channels of video stream data with the first preset resolution may be rendered, and then displayed in a spliced manner.
In this embodiment, through the rendering performance of the graphics card and the decoding information of the graphics accelerator card, the maximum number of ways that the graphics card can render under the conditions of the graphics card and the graphics accelerator card can be determined, so that the video monitoring program can select N not greater than the maximum number of ways subsequently, and thus determine that the number of ways displayed by splicing is smaller than the maximum number of ways of the graphics card, and further display the video stream data displayed by splicing each time, thereby improving user experience.
Further, the video monitoring program determines N not greater than the maximum number of paths, and selects N paths of video stream data with a first preset resolution, including:
A) And responding to the video stream selection instruction, and identifying the number T of paths of the video stream data selected by the selection instruction.
In this step, the video stream selection instruction is an instruction generated after the client selects the video stream data corresponding to the display instruction.
B) And if the T is not greater than the maximum number of paths, sending a display instruction to the CPU aiming at the video stream data selected by the selection instruction.
In this step, if T is not greater than the maximum number of paths, it is indicated that the video stream data of the T paths may be rendered by the graphics card and displayed in a spliced manner.
C) And the video monitoring program is also used for alarming if T is larger than the maximum number of paths.
In this step, if T is greater than the maximum number of paths, it is indicated that the video stream data display card of the T paths cannot render and display the video stream data display card in a spliced manner, and in order not to affect the user experience, the client is alerted. Therefore, the situation that the video card is selected to be incapable of rendering the video stream data of the number of paths can be avoided.
Because security scenes often have the condition that multichannel videos are opened simultaneously, and after opening, the performance of a hardware unit is directly detected, the hardware may not react, and therefore the hardware is actually opened, but the actual hardware is not completely opened when being opened, the performance of the hardware is still in a state before being opened, and further the condition that the performance of the hardware is lagged is caused. In order to better realize resource regulation and control, reduce decoding delay and improve decoding efficiency. The graphic accelerator card in the embodiment of the application comprises a plurality of processing chips; the graphics accelerator card maintains performance information representing the remaining performance of the plurality of processing chips and an identification of the processing chips.
The identification of the processing chip is used to distinguish between different processing chips.
As shown in FIG. 7, the processing chips in the graphics accelerator card are n processing chips, namely processing chip 1, processing chips 2 and … …, and processing chip n, and the illustrated processing chip can process 16 paths of 1080P video stream data initially) The number of processing chips included in each type of graphics accelerator card is variable, and is specifically determined based on the hardware capabilities of the graphics accelerator card. The number of the processing chips required can be determined according to the number of the video stream data with the first preset resolution, which can be processed, on each processing chip is different in the number of the video stream data with the first preset resolution. The number of paths of the video stream data which can be processed with the first preset resolution can be the same or different in each processing chip, and the processing chip is set according to actual application scenes.
For example, assuming that the processing chip 1 can process 3 paths of first preset resolution video stream data, the processing chip 2 can process 2 paths of first preset resolution video stream data, and the number of paths of the first preset resolution video stream data is 4, the processing chip 1 and the processing chip 2 are required to process the first preset resolution video stream data together.
The residual performance of the processing chip is the number of paths of video stream data of a first preset resolution which can be processed by the residual performance of the processing chip. For example, assuming that the processing chip 1 can process 3 paths of video stream data of the first preset resolution, it has processed 2 paths of video stream data of the first preset resolution, its remaining performance is 1, i.e. it can only process 1 path of video stream data of the first preset resolution again.
The CPU sends M paths of video stream data to a graphic accelerator card according to decoding information, and the CPU comprises:
Determining a processing chip with the residual performance capable of finishing decoding of M paths of video data as a target processing chip according to M, the performance information and the identification of the processing chip;
In this step, the number of target processing chips is at least one. And is determined according to M and performance information. The selected target processing chip is a processing chip capable of finishing decoding M paths of high-definition video data.
And sending M paths of video stream data to the target processing chip.
In the step, the CPU directly sends M paths of high-definition video stream data to the target processing chip of the graphic accelerator card, and the target processing chip decodes the M paths of high-definition video stream data.
The graphics accelerator card is also used for updating the performance information of the target processing chip after receiving the video stream data.
In the step, the graphics accelerator card updates the performance information of the target processing chip after receiving the video stream data, so that the target processing chip can be updated in real time by a subsequent CPU.
Based on this, the graphics accelerator card is configured to receive M paths of video stream data, decode the M paths of video stream data, and obtain decoded graphics data, and includes:
And the graphic acceleration card is used for decoding the M paths of video stream data through the target processing chip to obtain decoded graphic data.
In this embodiment, the graphics accelerator card maintains performance information indicating the remaining performance of the plurality of processing chips and the identification of the processing chips. And then the target processing chip can be selected according to the performance information and the identification of the processing chip, and once the target processing chip is determined, the performance information of the target processing chip is updated, so that the delay in performance detection can be reduced, and the decoding performance is improved.
Specifically, the graphics accelerator card decodes M paths of video stream data through the target processing chip to obtain decoded graphics data, and the graphics accelerator card comprises:
sequentially determining a processing chip with highest residual performance for each path of video stream data in the M paths of video stream data as a target processing chip;
and sending the video stream data to the target processing chip.
In this step, assuming that the processing chip 1 can process 3 paths of video stream data with the first preset resolution, the processing chip 2 can process 2 paths of video stream data with the first preset resolution, and the number of paths of the video stream data with the first preset resolution corresponding to the display instruction is 4, the remaining performance of the processing chip 1 is greater than the remaining performance of the processing chip 2, the target processing chip determined for the first time is the processing chip 1, and after 1 path of the first video stream data is sent to the processing chip 1, the processing chip 1 can process the video stream data into 2 paths. At this time, the remaining performance of the processing chip 1=the remaining performance of the processing chip 2, and then, one processing chip is arbitrarily selected as the target processing chip, and assuming that the target processing chip determined for the second time is the processing chip 2, after 1 path of the first video stream data is sent to the processing chip 2, the processing chip 2 can process the first video stream data into 1 path. At this time, if the remaining performance of the processing chip 1 > the remaining performance of the processing chip 2, the target processing chip determined for the third time is the processing chip 1, and after 1 path of the first video stream data is sent to the processing chip 1, the processing chip 1 can process the first video stream data into 1 path. And so on until all the 4 paths of video stream data with the first preset resolution are sent to the target processing chip.
In this embodiment, the graphics accelerator card maintains performance information indicating the remaining performance of the multiple processing chips in advance, so that a target processing chip can be selected according to the performance information of the processing chips, and then M paths of video stream data with a first preset resolution are sequentially sent to the target processing chip, so that the processing chip with the largest remaining performance can be selected as the target processing chip each time, and further, the graphics accelerator card is load-balanced when sending video stream data each time, and further, the graphics accelerator card can process data more quickly, and delay is reduced.
In some application scenarios, when the client discovers the interested detection picture, the client wants to save the screenshot, and then the interested screenshot picture can be obtained.
Based on the above, the graphics accelerator card is further configured to identify decoded graphics data of each frame obtained by decoding;
in this step, after the graphics accelerator card identifies each frame of decoded image data, each frame of decoded image data is buffered, then the identification and the decoded image data are mapped, and the mapping relation is saved and sent to the CPU, and the CPU also knows the identification of each frame of decoded image. The identification may be an ID number of the image frame or a decoded image may be numbered, and any method that may be used to identify decoded image data may be applied to the present embodiment.
In response to a screenshot instruction aiming at a target rendering graph, a video control program determines an identification of decoding graph data based on which the target rendering graph is obtained by rendering as a target identification;
in this step, the target rendered image is the current display frame on the display. The video control program determines the identification of the frame image according to the image data of the current display frame.
And the video control program controls the CPU to send the target identification to the graphic accelerator card.
The graphic accelerator card determines decoding graphic data represented by the target mark, codes the decoding graphic data, obtains a screenshot file and sends the screenshot file to the CPU.
For example, as shown in fig. 8, assuming that the current display frame needs to be captured, the identifier of the current display frame is ID-27, the CPU will respond to the capturing instruction and send the target identifier to the graphics accelerator card, and the graphics accelerator card searches the cache queue for the decoded image data with id=27, and then encodes the decoded image data to obtain the capturing file and sends the capturing file to the CPU to implement the whole capturing process.
In this embodiment, the graphics accelerator card identifies decoded image data of each frame obtained by decoding, determines a target identification of the decoded image data based on which the target rendered image is based in response to the screenshot instruction, and sends the target identification to the graphics accelerator card, so that the graphics accelerator card determines the decoded image data, and then encodes the decoded image data to obtain the screenshot file. And further, screenshot of the target rendering image is realized.
The embodiment of the application also provides a data processing device, as shown in fig. 9, which comprises: CPU, display card and graphic acceleration card.
The CPU is provided with a video monitoring program, and comprises: the system comprises middleware, a display card driver and a graphic accelerator card SDK, wherein the graphic accelerator card comprises a graphic accelerator card processing module.
Wherein,
The video monitoring program is used for controlling the CPU to read the decoding information from the storage device according to a display instruction generated by N paths of video stream data with first preset resolution, sending M paths of video stream data to the middleware according to the decoding information, and sending N-M paths of video stream data to the middleware, wherein M is not greater than N, and the decoding capability of decoding the M paths of video stream data is not greater than the decoding capability corresponding to the decoding information;
The middleware is used for receiving the M paths of high-definition video stream data and sending the M paths of high-definition video stream data to a graphic accelerator card SDK;
The graphic accelerator card SDK is used for controlling the graphic accelerator card processing module to receive the M paths of video stream data and decoding the M paths of video stream data to obtain first decoded graphic data; scaling the first decoded graphic data to a second preset resolution to obtain thumbnail-shaped data, and sending the thumbnail-shaped data to the CPU so that the CPU sends the received thumbnail-shaped data to the display card; the first preset resolution is greater than the second preset resolution; establishing communication connection between the CPU and the graphic acceleration card through PCIE and the Linux kernel driver;
the display card is used for receiving the N-M paths of video stream data and the thumbnail image data, and decoding the N-M paths of video stream data to obtain second decoded graphic data; rendering the second decoded graphic data and the thumbnail graphic data to obtain a rendered graphic corresponding to the N paths of video stream data; splicing rendering graphics corresponding to the N paths of video stream data to obtain spliced graphics; and controlling a display to display the spliced graph.
And the display card driver is used for establishing communication connection between the CPU and the display card.
The embodiment of the application also provides a video data processing method, which is applied to computer equipment, and the computer equipment comprises: the system comprises a main board, a display card, a graphic accelerator card, a display and storage equipment; the main board comprises: a CPU, a computer expansion bus standard PCIE bus, two PCIE slots; one PCIE slot is inserted with a display card, and the other PCIE slot is inserted with a graphic acceleration card; the PCIE bus is used for realizing the electrical connection between each PCIE slot and the CPU; the storage device is pre-stored with decoding information for representing the decoding performance of the graphic accelerator card; the CPU is deployed with a video monitoring program; as shown in fig. 10, the method includes:
S301, a CPU responds to a display instruction input by a video monitoring program for N paths of video stream data with first preset resolution, the generated display instruction reads decoding information from a storage device, M paths of video stream data are sent to a graphic accelerator card according to the decoding information, N-M paths of video stream data are sent to a display card, M is not more than N, and decoding capacity of decoding the M paths of video stream data is not more than decoding capacity corresponding to the decoding information.
S302, the graphic accelerator card decodes the received M paths of video stream data to obtain first decoded graphic data.
S303, the graphic accelerator card scales the first decoded graphic data to a second preset resolution to obtain thumbnail data, and sends the thumbnail data to the CPU, wherein the first preset resolution is larger than the second preset resolution;
s304, the CPU sends the received thumbnail data to a display card;
S305, the display card decodes the received N-M paths of video stream data and the thumbnail image data to obtain second decoded graphic data; and rendering the second decoded graphic data and the thumbnail graphic data to obtain a rendering graphic corresponding to the N paths of video stream data.
S306, splicing rendering graphics corresponding to the N paths of video stream data to obtain spliced graphics; and controlling the display to display the spliced graph.
The processes and manners of the steps executed by the CPU, the graphics accelerator card, and the graphics card in steps S301 to S306 are the same as those of the steps executed by the CPU, the graphics accelerator card, and the graphics card in the computer device, and are not described in detail herein.
In this embodiment, the graphics accelerator card is used to decode and scale multiple paths of video stream data, and because the graphics card renders a scaled thumbnail, the resolution of the thumbnail is smaller than that of the video stream data, so that when the graphics card renders, more paths of video stream data can be rendered, thereby greatly reducing the situation that the picture is stuck during multi-picture playing, and improving the efficiency of picture display.
The embodiment of the application also provides an electronic device, as shown in fig. 11, including:
a memory 401 for storing a computer program;
A processor 402, configured to execute a program stored in the memory 401, and implement the following steps:
The CPU responds to a display instruction input by the video monitoring program for N paths of video stream data with first preset resolution, generates a display instruction, reads the decoding information from the storage device, sends M paths of video stream data to the graphic acceleration card according to the decoding information, and sends N-M paths of video stream data to the display card, wherein M is not more than N, and the decoding capability of decoding the M paths of video stream data is not more than the decoding capability corresponding to the decoding information;
the graphics accelerator card decodes the received M paths of video stream data to obtain first decoded graphics data;
The graphic accelerator card scales the first decoded graphic data to a second preset resolution to obtain thumbnail data, and sends the thumbnail data to the CPU, wherein the second preset resolution is smaller than the first preset resolution; the first preset resolution is greater than the second preset resolution;
The CPU sends the received thumbnail-form data to the display card;
the display card decodes the received N-M paths of video stream data and the thumbnail image data to obtain second decoded graphic data; rendering the second decoded graphic data and the thumbnail graphic data to obtain a rendered graphic corresponding to the N paths of video stream data; splicing rendering graphics corresponding to the N paths of video stream data to obtain spliced graphics; and controlling the display to display the spliced graph.
And the electronic device may further comprise a communication bus and/or a communication interface, through which the processor 402, the communication interface, and the memory 401 communicate with each other.
The communication bus mentioned above for the electronic device may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.
The communication interface is used for communication between the electronic device and other devices.
The Memory may include random access Memory (Random Access Memory, RAM) or may include Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but may also be a digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components.
In yet another embodiment of the present application, there is also provided a computer readable storage medium having stored therein a computer program which when executed by a processor implements the steps of any of the video data processing methods described above.
In yet another embodiment of the present application, there is also provided a computer program product containing instructions that, when run on a computer, cause the computer to perform the video data processing method of any of the above embodiments.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), an optical medium (e.g., DVD), or a Solid state disk (Solid STATE DISK, SSD), etc.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (9)
1. A computer device, the device comprising: the system comprises a main board, a display card, a graphic accelerator card, a display and storage equipment;
the main board comprises: a CPU, a computer expansion bus standard PCIE bus, two PCIE slots; one PCIE slot is inserted with a display card, and the other PCIE slot is inserted with a graphic acceleration card; the PCIE bus is used for realizing the electrical connection between each PCIE slot and the CPU;
The storage device is pre-stored with decoding information for representing the decoding performance of the graphic accelerator card; the CPU is used for responding to a display instruction generated by the video monitoring program for N paths of video stream data with first preset resolution, reading the decoding information from the storage device, sending M paths of video stream data to the graphic accelerator card according to the decoding information, and sending N-M paths of video stream data to the display card, wherein M is not more than N, and the decoding capability of decoding the M paths of video stream data is not more than the decoding capability corresponding to the decoding information;
The graphics accelerator card is used for receiving the M paths of video stream data and decoding the M paths of video stream data to obtain first decoded graphics data; scaling the first decoded graphic data to a second preset resolution to obtain thumbnail-shaped data, and sending the thumbnail-shaped data to the CPU so that the CPU sends the received thumbnail-shaped data to the display card; the first preset resolution is greater than the second preset resolution; the data amount of the thumbnail-form data is smaller than the data amount of the first decoded graphic data; the display card is used for receiving the N-M paths of video stream data and the thumbnail image data, and decoding the N-M paths of video stream data to obtain second decoded graphic data; rendering the second decoded graphic data and the thumbnail graphic data to obtain a rendered graphic corresponding to the N paths of video stream data; splicing rendering graphics corresponding to the N paths of video stream data to obtain spliced graphics; and controlling the display to display the spliced graph;
The storage device is also used for correspondingly storing the specification model of each display card and the capability information of the display card, wherein the capability information is used for representing the decoding capability and rendering capability of the display card;
The CPU is also used for acquiring the specification model of the display card as a target specification model; searching the capacity information stored corresponding to the target specification model in the storage equipment by taking the target specification model as an index, and taking the capacity information as target capacity information;
Determining residual rendering capability according to the rendering capability represented by the target capability information, wherein the residual rendering capability is a difference value between the rendering capability represented by the target capability information and first rendering capability, and the first rendering capability is required rendering thumbnail-shaped data obtained by Z-path video stream data scaling;
determining a path number Y of second decoded graphic data which can be rendered at most by the residual rendering capability;
Determining the sum of the channel number Z of the video stream data which can be decoded at most and has the decoding capability corresponding to the decoding information as the maximum channel number;
the video monitoring program is used for determining N which is not more than the maximum number of paths and selecting N paths of video stream data with first preset resolution; and sending a display instruction to the CPU aiming at the selected video stream data.
2. The computer apparatus according to claim 1, wherein said transmitting M-way video stream data to the graphics accelerator card according to the decoding information includes:
Determining the number Z of paths of video stream data which can be decoded at most and corresponds to the decoding information, and taking the number Z as M;
And sending the M paths of video stream data to the graphic accelerator card.
3. The computer device of claim 1, wherein the video monitor determines N not greater than the maximum number of passes and selects N passes of video stream data of a first predetermined resolution, comprising:
Responding to a video stream selection instruction, and identifying the number T of paths of video stream data selected by the selection instruction;
if the T is not greater than the maximum number of paths, sending a display instruction to the CPU aiming at the video stream data selected by the selection instruction;
the video monitoring program is further used for alarming if the T is larger than the maximum number of paths.
4. The computer device of claim 1, wherein the graphics accelerator card includes a plurality of processing chips therein; the graphics accelerator card maintains performance information representing the remaining performance of the plurality of processing chips and an identification of the processing chip; the CPU sends M paths of video stream data to the graphic acceleration card according to the decoding information, and the CPU comprises the following steps:
Determining a processing chip with residual performance capable of finishing decoding M paths of video data as a target processing chip according to the M, the performance information and the identification of the processing chip;
m paths of video stream data are sent to the target processing chip;
The graphic acceleration card is also used for updating the performance information of the target processing chip after receiving the video stream data;
the graphics accelerator card is configured to receive the M paths of video stream data, and decode the M paths of video stream data to obtain decoded graphics data, and includes:
And the graphic accelerator card is used for decoding the M paths of video stream data through the target processing chip to obtain decoded graphic data.
5. The computer device of claim 4, wherein the sending M paths of video stream data to the target processing chip comprises:
sequentially determining a processing chip with highest residual performance for each path of video stream data in the M paths of video stream data as a target processing chip;
and sending the video stream data to the target processing chip.
6. The computer device of claim 1, wherein the graphics accelerator card is further configured to identify decoded graphics data for each frame decoded;
in response to a screenshot instruction aiming at a target rendering graph, a video control program determines an identification of decoding graph data based on which the target rendering graph is obtained by rendering as a target identification;
The video control program controls the CPU to send the target identifier to the graphic acceleration card;
and the graphic acceleration card determines decoding graphic data represented by the target identifier, codes the decoding graphic data, obtains a screenshot file and sends the screenshot file to the CPU.
7. A video data processing method, applied to a computer device, the device comprising: the system comprises a main board, a display card, a graphic accelerator card, a display and storage equipment; the main board comprises: a CPU, a computer expansion bus standard PCIE bus, two PCIE slots; one PCIE slot is inserted with a display card, and the other PCIE slot is inserted with a graphic acceleration card; the PCIE bus is used for realizing the electrical connection between each PCIE slot and the CPU; the storage device is pre-stored with decoding information for representing the decoding performance of the graphic accelerator card; the CPU is deployed with a video monitoring program; the method comprises the following steps:
The CPU responds to a display instruction input by the video monitoring program for N paths of video stream data with first preset resolution, generates a display instruction, reads the decoding information from the storage device, sends M paths of video stream data to the graphic acceleration card according to the decoding information, and sends N-M paths of video stream data to the display card, wherein M is not more than N, and the decoding capability of decoding the M paths of video stream data is not more than the decoding capability corresponding to the decoding information;
the graphics accelerator card decodes the received M paths of video stream data to obtain first decoded graphics data;
The graphic accelerator card scales the first decoded graphic data to a second preset resolution to obtain thumbnail data, and sends the thumbnail data to the CPU, wherein the second preset resolution is smaller than the first preset resolution; the first preset resolution is greater than the second preset resolution; the data amount of the thumbnail-form data is smaller than the data amount of the first decoded graphic data; the CPU sends the received thumbnail-form data to the display card;
The display card decodes the received N-M paths of video stream data and the thumbnail image data to obtain second decoded graphic data; rendering the second decoded graphic data and the thumbnail graphic data to obtain a rendered graphic corresponding to the N paths of video stream data; splicing rendering graphics corresponding to the N paths of video stream data to obtain spliced graphics; and controlling the display to display the spliced graph;
the storage equipment is used for correspondingly storing the specification model of each display card and the capability information of the display card, wherein the capability information is used for representing the decoding capability and rendering capability of the display card; the method further comprises the steps of:
The CPU obtains the specification model of the display card as a target specification model; searching the capacity information stored corresponding to the target specification model in the storage equipment by taking the target specification model as an index, and taking the capacity information as target capacity information; determining residual rendering capability according to the rendering capability represented by the target capability information, wherein the residual rendering capability is a difference value between the rendering capability represented by the target capability information and first rendering capability, and the first rendering capability is required rendering thumbnail-shaped data obtained by Z-path video stream data scaling; determining a path number Y of second decoded graphic data which can be rendered at most by the residual rendering capability; determining the sum of the channel number Z of the video stream data which can be decoded at most and has the decoding capability corresponding to the decoding information as the maximum channel number;
The video monitoring program determines N which is not more than the maximum number of paths, and selects N paths of video stream data with first preset resolution; and sending a display instruction to the CPU aiming at the selected video stream data.
8. An electronic device, comprising:
a memory for storing a computer program;
a processor for implementing the method of claim 7 when executing a program stored on a memory.
9. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when executed by a processor, implements the method of claim 7.
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