CN117063268A - Ferroelectric memory and method for manufacturing the same - Google Patents
Ferroelectric memory and method for manufacturing the same Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
The present disclosure relates to a method for manufacturing a ferroelectric memory. The method includes placing the ferrite layer in a weakly corrosive oxidizing solution that can react rapidly with carbon defects in the ferrite layer to remove the carbon defects and can also react with oxygen vacancies in the ferroelectric layer to fill the oxygen vacancies. The effect of regulating and controlling the ferroelectric polarization characteristic and reliability of the ferroelectric layer can be achieved by regulating and controlling the carbon defect concentration and the oxygen vacancy defect concentration in the ferroelectric layer. In addition, in the case where a plurality of wafers can be simultaneously processed while being put in an oxidizing solution, the production efficiency can be significantly improved and the manufacturing cost can be reduced.
Description
The present disclosure relates to the field of electronics, and more particularly to ferroelectric memories and methods of making the same.
The daily life of people is not separated from various electronic devices, and the times of interaction between people and various electronic devices can reach thousands of times each day. The transmission, processing and storage of the massive data generated in these interactions is the core of the information technology. Therefore, various memories are required to store these mass data.
One common memory is ferroelectric random access memory (ferroelectric randon access memory, feRAM). FeRAM can be stored quickly with very low power requirements and is expected to find wide application in consumer small devices such as personal digital assistants, cell phones, power meters, smart cards, and security systems. One common FeRAM includes a plurality of memory cells, each memory cell including at least one metal-ferroelectric layer-metal capacitor. The ferroelectric layer may include a hafnium oxide thin film, and the metal layers on both sides thereof may provide stress by thermal expansion during annealing crystallization in addition to the basic electrode contact function, thereby inducing the hafnium oxide thin film to generate a ferroelectric phase and thus ferroelectric polarization characteristics.
Some carbon impurity defects and oxygen vacancy defects exist in the hafnium oxide film. On the one hand, the ferroelectric polarization characteristic of FeRAM depends on the content of ferroelectric crystal phase in FeRAM, and the annealing crystallization process is affected by the content of impurities in FeRAM. On the other hand, a key characteristic of FeRAM is reliability, which specifically includes leakage current, breakdown characteristics, wake-up effect, repeated erasing life, data retention time, and the like. The presence of defects may affect the reliability of FeRAM. One conventional method of forming ferroelectric layers is to bombard a target of ferroelectric material with plasma by physical vapor deposition (physical vapor deposition, PVD) in a reaction chamber to sputter a layer of ferroelectric layer onto the electrode surface. Because the ferroelectric layer prepared by the PVD method has a lot of oxygen vacancy defects in general, oxygen with a certain concentration is mixed and introduced into argon sputtering gas to adjust the concentration of the oxygen vacancy defects in the ferroelectric layer, so that the effect of adjusting and controlling the oxygen vacancy defects in the ferroelectric layer is achieved. However, the PVD method itself has an ion bombardment process, which causes ion bombardment damage to the lower interface between the metal electrode and the ferroelectric layer, and which is difficult to control in the deposition process. The high ion bombardment damage can lead to high internal defect concentration of the ferroelectric layer prepared by the PVD method, and further lead to poor reliability of the ferroelectric layer prepared by the PVD method.
Disclosure of Invention
In view of the above, embodiments of the present disclosure aim to provide a method of manufacturing a ferroelectric memory for improving reliability of the ferroelectric memory.
According to a first aspect of the present disclosure, a method for manufacturing a ferroelectric memory is provided. The method comprises the following steps: a first electrode layer is formed on the substrate and a ferroelectric layer is formed on the first electrode layer. The method further comprises the steps of: placing the ferroelectric layer in an oxidizing solution for removing at least a portion of carbon defects and oxygen vacancy defects in the ferroelectric layer; and forming a second electrode layer on the ferroelectric layer to form a ferroelectric capacitor of a memory cell of the ferroelectric memory. By placing the ferrite layer in a weakly corrosive oxidizing solution, the oxidizing solution can react rapidly with carbon defects in the ferrite layer to remove the carbon defects and can also react with oxygen vacancies in the ferroelectric layer to fill the oxygen vacancies. By controlling the carbon defect concentration and the oxygen vacancy defect concentration in the ferroelectric layer without PVD sputtering, the effect of controlling the ferroelectric polarization characteristic and the reliability of the ferroelectric layer can be achieved. In addition, in the case where a plurality of wafers can be simultaneously processed while being put in an oxidizing solution, the production efficiency can be significantly improved and the manufacturing cost can be reduced.
In a possible implementation manner of the first aspect, the method further includes: after forming the second electrode layer, a rapid thermal annealing process is performed on the substrate including the first electrode layer, the ferroelectric layer, and the second electrode layer. By using rapid thermal annealing, stress can be provided in the first electrode layer, the ferroelectric layer, and the second electrode layer in a thermally expansive manner. The stress can induce the hafnium oxide film to generate more ferroelectric crystal phases, thereby improving ferroelectric polarization characteristics.
In a possible implementation manner of the first aspect, the method further includes: before placing the ferroelectric layer in the oxidizing solution: forming a sacrificial electrode layer on the ferroelectric layer; performing a rapid thermal annealing process on the substrate including the first electrode layer, the ferroelectric layer, and the sacrificial electrode layer; and removing the sacrificial electrode layer. In one aspect, stress is formed for crystallization by rapid thermal annealing before placing the ferroelectric layer in an oxidizing solution, and then the sacrificial electrode is removed and the ferroelectric layer is placed in an oxidizing solution for reducing defect concentration. The defect concentration in the ferroelectric layer during crystallization and the defect concentration in the ferroelectric layer after crystallization can be controlled respectively, so that the ferroelectric memory has stronger ferroelectric polarization characteristic and longer cycle erasing life. On the other hand, the method does not affect the deposition process of the ferroelectric layer (because in the implementation mode, the ferroelectric layer is completed before the sacrificial electrode is formed), and the manufacturing production cost of the ferroelectric layer can be effectively controlled while the ferroelectric layer is lifted.
In one possible implementation of the first aspect, the ferroelectric layer comprises a hafnium oxide layer. Forming the ferroelectric layer on the first electrode layer includes: a hafnium oxide layer is formed on the first electrode layer using atomic layer deposition (atom layer deposition, ALD). By using ALD to deposit the hafnium oxide layer, internal damage to the hafnium oxide layer caused by a conventional PVD sputtering method can be effectively avoided, and the reliability of the ferroelectric memory can be improved.
In one possible implementation of the first aspect, the hafnium oxide layer comprises or is made of a hafnium oxide based material. Hafnium oxide based materials refer to ferroelectric materials based on hafnium oxide material systems, such as silicon (Si) doped hafnium oxide (HfO) 2 ) Aluminum (Al) doped HfO 2 Lanthanum (La) -doped HfO 2 Yttrium (Y) doped HfO 2 Gadolinium (Gd) -doped HfO 2 Strontium (Sr) -doped HfO 2 Etc.; or may also be hafnium zirconium oxide (hafniumzir)coniumoxide, HZO) systems, such as hafnium zirconium oxygen HZO, lanthanum (La) -doped HZO, yttrium (Y) -doped HZO, strontium (Sr) -doped HZO, gadolinium (Gd) -doped HZO, gadolinium lanthanum (Gd/La) -co-doped HZO, yttrium lanthanum (Y/La) -co-doped HZO, and the like. HZO is HfO 2 -ZrO 2 And (3) solidifying the solute. HZO can also be expressed as Hf x Zr (1-x) O 2 Wherein x may range from 0.1 to 0.9.HZO is a ferroelectric material, and the characteristics of HZO can be improved by doping the material with elements such as La and Y.
In one possible implementation of the first aspect, forming the hafnium oxide layer on the first electrode layer using atomic layer deposition includes: ozone gas is used to react with the hafnium oxide layer within the reaction chamber for a first period of time. By allowing the ozone gas to react with the hafnium oxide layer for a first period of time, the hafnium oxide layer may be pretreated to pre-control its defect concentration to improve the reliability of the ferrite memory.
In one possible implementation manner of the first aspect, the first period of time is between 0.1s and 10 s. In another possible implementation manner of the first aspect, the first period of time is between 0.3s and 5 s. In another possible implementation manner of the first aspect, the first period of time is between 0.5s and 1 s.
In one possible implementation of the first aspect, the etching rate of the ferroelectric layer by the oxidizing solution is not higher than 0.5nm per minute. By using an oxidizing solution that is inert to the ferroelectric layer, the defect concentration can be reduced without substantially affecting the ferroelectric layer itself. On the premise of this, an appropriate oxidizing solution can be selected.
In one possible implementation of the first aspect, the oxidizing solution includes H 2 O 2 Solution, SC1 solution, H 2 SO 4 :H 2 O 2 Solution or water-soluble O 3 A solution.
In a possible implementation manner of the first aspect, H 2 O 2 H in solution 2 O 2 Is between 0.1% and 60%, 1% and 30% by massBetween or between 10% and 20%.
In a possible implementation manner of the first aspect, H 2 SO 4 :H 2 O 2 H in solution 2 O 2 The mass percentage is between 0.1% and 60%, H 2 SO 4 Is between 0.1% and 98% by mass. In other possible implementations, H 2 SO 4 :H 2 O 2 H in solution 2 O 2 The mass percentage is between 1% and 30%, H 2 SO 4 Is between 1% and 70% by mass. In still other possible implementations, H 2 SO 4 :H 2 O 2 H in solution 2 O 2 The mass percentage is between 10% and 20%, H 2 SO 4 Is between 10% and 40% by mass.
In one possible implementation of the first aspect, the water-soluble O 3 O in solution 3 Is between 0.01mg/L and 10 mg/L. In other possible implementations, water-soluble O 3 O in solution 3 Is between 0.1mg/L and 7 mg/L. In yet other possible implementations, water-soluble O 3 O in solution 3 Is between 1mg/L and 3 mg/L.
In one possible implementation of the first aspect, the SC1 solution is NH 4 OH:H 2 O 2 :H 2 O solution. In some possible implementations, NH of SC1 solution 4 OH mass percent is between 0.1% and 30%, and H 2 O 2 The mass percentage is between 0.1% and 60%. In other possible implementations, NH of SC1 solution 4 OH mass percent is between 1% and 10%, and H 2 O 2 The mass percentage is between 1% and 30%. In still other possible implementations, NH of SC1 solution 4 OH mass percent is between 3% and 5%, and H 2 O 2 The mass percentage is between 5% and 10%.
In a possible implementation manner of the first aspect, the method further includes: detecting ferroelectric polarization characteristics of the ferroelectric capacitor; and adjusting the oxidizing solution based on the ferroelectric polarization characteristic. In some possible implementations, for wafers manufactured using the same process, several wafers (as samples) may be selected to be placed in solution for processing and the ferroelectric polarization strength of the ferroelectric capacitor after the processing is measured. Based on the measurement results of the sample, parameters of the oxidizing solution, such as concentration and formulation, etc., may be adjusted accordingly. In this way, the subsequent wafer may use an adjusted oxidizing solution to obtain the desired ferroelectric polarization strength. By using sample measurements and adjusting the recipe based on the measurement results, it is possible to improve defect handling of ferroelectric capacitors in a ferroelectric memory in a low cost and efficient manner, standardize the manufacturing process and reduce the time cost of a ferroelectric memory with high ferroelectric polarization strength and high number of cyclic erasures.
In a second aspect of the present disclosure, there is provided a ferroelectric memory made by the method according to the first aspect.
In a third aspect of the present disclosure, there is provided an electronic assembly comprising a circuit board and a ferroelectric memory according to the second aspect, the ferroelectric memory being located on the circuit board.
In a fourth aspect of the present disclosure, there is provided an electronic device comprising a power supply means and a ferroelectric memory according to the second aspect, the ferroelectric memory being powered by the power supply means.
In a fifth aspect of the present disclosure, there is provided an integrated circuit chip comprising a package and a ferroelectric memory according to the second aspect, the ferroelectric memory being located in the package.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:
FIG. 1 illustrates a block diagram of an electronic device in which some embodiments of the present disclosure may be implemented;
FIG. 2 illustrates a circuit diagram of a ferroelectric memory in which some embodiments of the present disclosure may be implemented;
FIG. 3 illustrates a circuit diagram of one memory cell in a ferroelectric memory in which some embodiments of the present disclosure may be implemented;
fig. 4 shows a structural diagram of a ferroelectric capacitor in a conventional ferroelectric memory;
FIG. 5 illustrates a flow chart of a method according to some embodiments of the present disclosure;
FIG. 6 illustrates an effect schematic of a method according to some embodiments of the present disclosure;
FIG. 7 illustrates a schematic diagram of performance comparison of a ferroelectric memory resulting from a method according to some embodiments of the present disclosure with a conventional ferroelectric memory; and
fig. 8 shows a schematic diagram of performance comparison of a ferroelectric memory obtained by methods according to further embodiments of the present disclosure with a conventional ferroelectric memory.
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "this embodiment" should be understood as "an embodiment". The terms "first," "second," and the like, may refer to different or the same object. The term "and/or" means at least one of the two items associated therewith. For example, "a and/or B" means A, B, or a and B. Other explicit and implicit definitions are also possible below.
In the following description of the specific embodiments, some repetition is not described in detail, but it should be understood that the specific embodiments have mutual references and may be combined with each other.
Ferroelectric memories store data based on the ferroelectric effect of ferroelectric materials. Ferroelectric memories are expected to be a major competitor to dynamic random access memories (dynamic random access memory, DRAM) due to their ultra-high memory density, low power consumption, and high speed. The memory cell in a ferroelectric memory comprises a ferroelectric capacitor comprising two electrodes and a ferroelectric material, such as a ferroelectric film layer, arranged between the two electrodes. Due to the non-linear nature of the ferroelectric material, the dielectric constant of the ferroelectric material can be adjusted, and the difference between before and after the polarization state of the ferroelectric film layer is reversed is very large, which makes the ferroelectric capacitor have a smaller volume compared with other capacitors, for example, the capacitor for storing charges in the DRAM is much smaller.
In ferroelectric memories, the ferroelectric layer may be formed using a common ferroelectric material. When an electric field is applied to the ferroelectric layer of the memory cell, the central atoms are stopped in a low energy state along the electric field, whereas when an electric field reversal is applied to the ferroelectric layer, the central atoms move in the crystal along the direction of the electric field and are stopped in another low energy state. A large number of central atoms are mobile-coupled in the crystal unit cell to form ferroelectric domains (ferroelectric domains), which form polarized charges under the action of an electric field. The ferroelectric domain has higher polarized charge formed by inversion under the electric field, the ferroelectric domain has lower polarized charge formed by non-inversion under the electric field, and the binary stable state of the ferroelectric material enables the ferroelectric to be used as a memory.
The embodiment of the application provides an electronic device comprising a ferroelectric memory. Fig. 1 shows an electronic device 100 according to an embodiment of the present application, where the electronic device 100 may be a terminal device, such as a mobile phone, a tablet computer, a smart band, or a personal computer (personal computer, PC), a server, a workstation, etc. The electronic device 100 includes a bus 105, a System On Chip (SOC) 110 and a read-only memory (ROM) 120 connected to the bus 105. The SOC 110 may be used to process data, such as data of processing applications, process image data, and buffer temporary data. The ROM 120 may be used to hold non-volatile data such as audio files, video files, and the like. ROM 120 may be PROM (programmable read-only memory), EPROM (erasable programmable read-only memory), flash memory (erasable programmable read-only memory), or the like.
In addition, the electronic device 100 may further include a communication chip 130 and a power management chip 140. The communication chip 130 may be used for processing the protocol stack, amplifying, filtering, etc. the analog radio frequency signal, or implementing the above functions at the same time. The power management chip 140 may be used to power other chips.
In one embodiment, the SOC 110 may include an application processor (application processor, AP) 111 for processing applications, an image processing unit (graphics processing unit, GPU) 112 for processing image data, and a random access memory (random access memory, RAM) 113 for caching data. The AP 111, the GPU 112, and the RAM 113 may be integrated into one die (die), or may be integrated into a plurality of dies (die), respectively, and packaged in a package structure, for example, using 2.5D (dimension), 3D packaging, or other advanced packaging techniques. In one embodiment, the AP 111 and the GPU 112 are integrated in one die, the RAM 113 is integrated in another die, and the two die are packaged in a package structure, so as to obtain a faster inter-die data transmission rate and a higher data transmission bandwidth.
Fig. 2 is a schematic structural diagram of a ferroelectric memory 200 according to an embodiment of the present disclosure. The ferroelectric memory 200 may be a RAM 113 as shown in fig. 1, belonging to FeRAM. In one embodiment, ferroelectric memory 200 may also be a RAM disposed external to SOC 110. The present disclosure does not limit the location of ferroelectric memory 200 in the device and the positional relationship with SOC 110. Continuing with fig. 2, ferroelectric memory 200 includes memory array 210, decoder 220, driver 230, timing controller 240, buffer 250, and input-output driver 260. The memory array 210 includes a plurality of memory cells 300 arranged in an array, wherein each memory cell 300 may be used to store 1bit or more of data. The memory array 210 also includes signal lines such as Word Lines (WL), bit Lines (BL), and the like. Each memory cell 300 is electrically connected to a corresponding word line WL, bit line BL. One or more of the word lines WL and the bit lines BL are used for selecting the memory cells 300 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the polarization direction of the ferroelectric capacitor in the memory cells 300, thereby realizing the data read and write operation.
In the ferroelectric memory 200 structure shown in fig. 2, the decoder 220 is configured to decode according to the received address to determine the memory cell 300 that needs to be accessed. The driver 230 is used to control the level of the signal line according to the decoding result generated by the decoder 220, thereby realizing access to the designated memory cell 300. The buffer 250 is used for buffering the read data, and may be, for example, a first-in first-out (FIFO) buffer. The timing controller 230 is used for controlling the timing of the buffer 250 and controlling the driver 230 to drive the signal lines in the memory array 210. The input-output driver 260 is used to drive transmission signals, such as to drive received data signals and to drive data signals to be transmitted, so that the data signals can be transmitted over a long distance.
The memory array 210, the decoder 220, the driver 230, the timing controller 240, the buffer 250, and the input/output driver 260 may be integrated into one chip or may be integrated into a plurality of chips. The ferroelectric memory 200 according to the present disclosure may be a ferroelectric random access memory (ferroelectric random access memory, feRAM) or a ferroelectric field effect transistor memory (ferroelectric filed-effect-transistor, feFET). For example, fig. 3 shows a circuit configuration diagram of one of the memory cells 300 of the FeRAM, as in fig. 3, the memory cell 300 includes at least two ferroelectric capacitors C and one transistor Tr, for example, fig. 3 exemplarily shows three ferroelectric capacitors (e.g., ferroelectric capacitor C1, ferroelectric capacitor C2, and ferroelectric capacitor C3 of fig. 3), and such a memory cell may be referred to as a 1TnC memory cell. The transistor Tr here may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In addition, the memory cell 300 further includes Word Line (WL), bit Line (BL), and Plate Line (PL) signal lines, and in the memory cell 300, a first terminal of the transistor Tr is electrically connected to the bit line BL, a control terminal of the transistor Tr is electrically connected to the word line WL, a second terminal of the transistor Tr is electrically connected to a first electrode of the ferroelectric capacitor C, and a second electrode of the ferroelectric capacitor C is electrically connected to the plate line PL.
In the present disclosure, one of the drain (drain) or source (source) of the transistor Tr is referred to as a first terminal, the other is referred to as a second terminal, and the control terminal of the transistor Tr is a gate. The drain and source of the transistor Tr may be determined according to the flow direction of current, for example, in fig. 3, when the current flows from left to right, the left end is the drain, the right end is the source, and conversely, when the current flows from right to left, the right end is the drain, and the left end is the source. It will be understood that the transistor Tr herein is a transistor device having three terminals, and then the transistor Tr may be selected from NMOS (N-channel metal oxide semiconductor ) transistors, or may be selected from PMOS (P-channel metal oxide semiconductor ) transistors. One memory cell 300 shown in fig. 3 may be used to store multi-bit data to increase the storage capacity of each memory cell. In particular, the ferroelectric capacitors C share one transistor Tr, and thus, the number of transistors per memory cell 300 can also be reduced to improve the memory density.
Fig. 4 shows a structural diagram of a ferroelectric capacitor 400 in a conventional ferroelectric memory. The ferroelectric capacitor 400 may be located on a substrate, and may include a stacked first electrode 410, ferroelectric layer 420, and second electrode 430. It is to be appreciated that a wafer may generally include a plurality of ferroelectric memory dies (e.g., each die on the wafer has at least one ferroelectric memory), and that each ferroelectric memory may include a plurality of ferroelectric capacitors 400. The plurality of ferroelectric capacitors 400 may be located on the same substrate, and for example, the plurality of ferroelectric capacitors 400 may be formed on the same substrate. The substrate may also include other circuit devices, which the present disclosure is not limited to. Since the present disclosure focuses on ferroelectric capacitors in ferroelectric memories, other circuits in the wafer and other components in the ferroelectric memories will not be described in detail herein.
In some cases, the ferroelectric capacitor 400 further includes a first isolation passivation layer and a second isolation passivation layer (not shown), and the first isolation passivation layer is formed between the first electrode 410 and the ferroelectric layer 420, and the second isolation passivation layer is formed between the second electrode 430 and the ferroelectric layer 420. As shown, there are more carbon defects (shown as black solid circles) and more oxygen vacancy defects (shown as open dashed circles) in the ferroelectric layer 420. As described above, the presence of defects such as carbon defects or oxygen vacancy defects may affect the reliability of FeRAM. One conventional method of forming ferroelectric layers is to bombard a ferroelectric target having a purity of 99.9% with plasma by physical vapor deposition (physical vapor deposition, PVD) in a reaction chamber to sputter a layer of ferroelectric layer on the electrode surface. Because the ferroelectric layer prepared by the PVD method has a lot of oxygen vacancy defects in general, oxygen with a certain concentration is mixed and introduced into argon sputtering gas to adjust the oxygen vacancy defect concentration of the ferroelectric layer, so that the effect of adjusting and controlling the oxygen vacancy defects in the ferroelectric layer is achieved. However, the PVD method itself has an ion bombardment process, which causes ion bombardment damage to the lower interface between the metal electrode and the ferroelectric layer, and which is difficult to control in the deposition process. The high ion bombardment damage can lead to high internal defect concentration of the ferroelectric layer prepared by the PVD method, and further lead to poor reliability of the ferroelectric layer prepared by the PVD method.
Another conventional FeRAM fabrication method involves the use of atomic layer deposition for the deposition of ferroelectric layers and the adjustment of the oxygen content inside the thin film by controlling the aeration pulse time of the oxygen precursor. Specifically, a standard ALD single cycle includes four steps: and (3) introducing a metal precursor into the reaction cavity, purging the reaction cavity by nitrogen, introducing an oxygen precursor, and purging by nitrogen. In this scheme, O is used 3 As an oxygen precursor, the defect content in the ferroelectric layer is adjusted by modifying the time of the oxygen precursor. Although the defect content can be controlled in the above manner, a longer single cycle time of ALD will result in an extremely low overall efficiency of deposition. For example, ALD single-cycle growth of a hafnium oxide-based ferroelectric layer to a thickness of about 0.08 nanometers (nm), then this means that 120 cycles are required to grow a 10nm hafnium oxide-based ferroelectric layer. If the total time per cycle is, for example, greater than 5 seconds(s), then greater than 10 minutes is required to grow a 10nm hafnium oxide based ferroelectric layer. Thus, ALD processes will produce less than 6 wafers per hour on average, which is less efficient and costly to manufacture.
In some embodiments of the present disclosure, by placing the ferrite layer in a weakly corrosive oxidizing solution, the oxidizing solution may rapidly react with carbon defects in the ferrite layer to remove the carbon defects, and may also react with oxygen vacancies in the ferroelectric layer to fill the oxygen vacancies. The effect of regulating and controlling the ferroelectric polarization characteristic and reliability of the ferroelectric layer can be achieved by regulating and controlling the carbon defect concentration and the oxygen vacancy defect concentration in the ferroelectric layer. In addition, in the case where a plurality of wafers can be simultaneously processed while being put in an oxidizing solution, the production efficiency can be significantly improved and the manufacturing cost can be reduced.
In the present disclosure, the ferroelectric layer may be made using a hafnium oxide-based material. Compared with other ferroelectric materials, the thickness of the hafnium oxide-based ferroelectric capacitor can be reduced to ten nanometers or even subten nanometers, so that high-density integration or even three-dimensional integration can be realized, and the method has great advantages in the aspect of constructing an ultra-high density memory chip. In addition, the preparation process of the hafnium oxide-based ferroelectric capacitor can have good compatibility with the silicon-based semiconductor process, so that the ferroelectric capacitor can be prepared by using a mature manufacturing process without increasing the manufacturing cost.
In the present disclosure, the crystalline phase of the ferroelectric layer made of a material such as hafnium oxide includes: monoclinic phase (m-phase), which is an amorphous phase; a tetragonal phase (t-phase), which is also an amorphous phase; and an orthorhombic (orthorhombic phase, o-phase), also known as orthorhombic, phase, which is generally considered to be a ferroelectric phase. In the ferroelectric layer lattice structure of ferroelectric crystal phase, positive and negative charge centers are asymmetric to generate electric dipoles, a large number of electric dipoles which are random in original direction and have overall net value of 0 can become consistent in direction and have net value of non-0 under the drive of an external electric field, certain tropism can be still maintained after the electric field is removed, so that the net value of the total charge of the film is non-0, and the effect is called ferroelectric spontaneous polarization characteristic. The net value of the total charge of the ferroelectric layer is also called ferroelectric polarization (polarization). The net value of the total electric charge of the film after the electric field is removed is the remnant polarization (remnant polarization, pr), which is a quantization parameter commonly used to measure the ferroelectric polarization characteristics of ferroelectric films.
The hafnium oxide-based material referred to by the ferroelectric layer of the present disclosure refers to a ferroelectric material based on a hafnium oxide material system, for example, may be silicon (Si) doped hafnium dioxide (HfO) 2 ) Aluminum (Al) doped HfO 2 Lanthanum (La) -doped HfO 2 Yttrium (Y) doped HfO 2 Gadolinium (Gd) -doped HfO 2 Strontium (Sr) -doped HfO 2 Etc.; or may be a Hafnium Zirconium Oxide (HZO) system, for example, hafnium zirconium oxide HZO, lanthanum (La) -doped HZO, yttrium (Y) -doped HZO, strontium (Sr) -doped HZO, gadolinium (Gd) -doped HZO, gadolinium lanthanum (Gd/La) -co-doped HZO, yttrium lanthanum (Y/La) -co-doped HZO, and the like. In this disclosure, a hafnium oxide layer refers to a layer formed using a hafnium oxide-based material.
In some embodiments, the materials of the first electrode layer and the second electrode layer on both sides of the ferroelectric layer may be selected from metals, for example, but not limited to, the following metals. By way of example, titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), hafnium nitride (HfN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), tungsten (W), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), ruthenium oxide (RuO), iridium oxide (IrO), indium TiN Oxide (ITO), and the like may be selected. The materials of the first electrode layer and the second electrode layer may be the same or different.
In some designs, the thickness of the first electrode layer and the second electrode layer in the stacking direction may be, but is not limited to, 2.5nm to 100nm. The thickness of the first electrode layer and the thickness of the second electrode layer may be equal or unequal. In some scenarios, tiN may be selected to make the first electrode layer and the second electrode, and HZO may be used to make the ferroelectric layer. Because the HZO layer provides tensile stress to facilitate formation of the ferroelectric phase, and TiN materials may be compatible with semiconductor CMOS processes. Further, the thickness of the ferroelectric layer in the stacking direction may be, but is not limited to, 1nm to 100nm.
Fig. 5 illustrates a flow chart of a method 500 according to some embodiments of the present disclosure. It will be appreciated that the various aspects described above with respect to ferroelectric memories may be selectively applied to the method 500 and are not described in detail herein. The manufacturing process of the ferroelectric memory may include numerous steps, however, the present disclosure focuses on the manufacturing process of the ferroelectric capacitor in the ferroelectric memory, and thus the manufacturing process of the parts other than the ferroelectric capacitor of the ferroelectric memory is not described herein. At 502, a first electrode layer is formed on a substrate. At 504, a ferroelectric layer is formed on the first electrode layer. In one embodiment, the ferroelectric layer may be a hafnium oxide layer. For example, a ferroelectric layer may be formed on the first electrode layer by ALD. For example, in the reaction chamber, in the presence of O 3 ALD was used to deposit HZO layers with a gas of up to 5 s. In another embodiment, a first isolation passivation layer may be formed on the first electrode layer first, and then a ferroelectric layer may be formed on the first isolation passivation layer. The present disclosure is not limited in this regard.
At 506, the ferroelectric layer may be placed for removal of carbon defects and oxygen vacancy defects in the ferroelectric layerAt least a portion of which is an oxidizing solution. In the present disclosure, the oxidizing solution is inert or weakly corrosive to the ferrite layer, or has an etching rate of not more than 0.5nm per minute for the ferroelectric layer. In another aspect, the oxidizing solution may react with at least a portion of the carbon defects and oxygen vacancy defects in the ferrite layer to remove at least a portion of the carbon defects and oxygen vacancy defects. In some embodiments, the oxidizing solution includes H 2 O 2 Solution, SC1 solution, H 2 SO 4 :H 2 O 2 Solution or water-soluble O 3 A solution. In some embodiments, H 2 O 2 H in solution 2 O 2 Is between 0.1% and 60%, between 1% and 30% or between 10% and 20% by mass. In some embodiments, H 2 SO 4 :H 2 O 2 H in solution 2 O 2 The mass percentage is between 0.1% and 60%, H 2 SO 4 Is between 0.1% and 98% by mass. In other embodiments, H 2 SO 4 :H 2 O 2 H in solution 2 O 2 The mass percentage is between 1% and 30%, H 2 SO 4 Is between 1% and 70% by mass. In still other embodiments, H 2 SO 4 :H 2 O 2 H in solution 2 O 2 The mass percentage is between 10% and 20%, H 2 SO 4 Is between 10% and 40% by mass. In some embodiments, water-soluble O 3 O in solution 3 Is between 0.01mg/L and 10 mg/L. In other embodiments, water-soluble O 3 O in solution 3 Is between 0.1mg/L and 7 mg/L. In still other embodiments, water-soluble O 3 O in solution 3 Is between 1mg/L and 3 mg/L. In some embodiments, the SC1 solution is NH 4 OH:H 2 O 2 :H 2 O solution. In some embodiments, NH of SC1 solution 4 OH mass percent is between 0.1% and 30%, and H 2 O 2 The mass percentage is between 0.1% and 60%. In other of said, NH of SC1 solution 4 OH mass percent is between 1% and 10%, and H 2 O 2 The mass percentage is between 1% and 30%. In still other embodiments, the NH of the SC1 solution 4 OH mass percent is between 3% and 5%, and H 2 O 2 The mass percentage is between 5% and 10%.
At 508, a second electrode layer is formed on the ferroelectric layer to form a ferroelectric capacitor of a memory cell of the ferroelectric memory. In some embodiments, a second isolation passivation layer may be formed on the ferroelectric layer before the second electrode layer is formed, and the second electrode layer is formed on the second isolation passivation layer after that, without limitation of the present disclosure. In one embodiment, a rapid thermal annealing process may be performed on the substrate including the first electrode layer, the ferroelectric layer, and the second electrode layer after the second electrode layer is formed. By performing rapid thermal annealing, stress can be provided by thermal expansion, thereby inducing the ferrite layer to produce a ferroelectric phase, and thus ferroelectric polarization properties.
Fig. 6 illustrates an effect schematic of a method 500 according to some embodiments of the present disclosure. As shown in fig. 6, reference numeral 620 indicates a distribution schematic of carbon defects and oxygen vacancy defects in the ferrite layer before the ferrite layer is not put into the above-described oxidizing solution, wherein a black solid circle indicates carbon defects and a hollow dotted circle indicates oxygen vacancy defects. Reference numeral 640 denotes a distribution schematic of carbon defects and oxygen vacancy defects after the above-described oxidizing solution treatment. It can be seen that both carbon defects and oxygen vacancy defects in the ferrite layer are significantly reduced after treatment with the oxidizing solution. In some embodiments of the present disclosure, the concentration of carbon defects and oxygen vacancy defects in the ferrite layer may be controlled by adjusting the oxidizing solution. For example, for wafers manufactured using the same process, it is possible to choose to put several wafers (as samples) into solution for processing and measure the ferroelectric polarization intensity of the ferroelectric capacitor after the processing. Based on the measurement results of the sample, parameters of the oxidizing solution, such as the oxidizing solution concentration and formulation, or the time the wafer is placed in the oxidizing solution, etc., may be adjusted accordingly. In this way, the subsequent wafer may use an adjusted oxidizing solution to obtain the desired ferroelectric polarization strength.
Fig. 7 illustrates a schematic diagram of performance comparison of a ferroelectric memory resulting from a method 500 according to some embodiments of the present disclosure with a conventional ferroelectric memory. Reference numeral 710 indicates the application of 0.5s O in each cycle 3 Ferroelectric polarization of the ferrite layer obtained by pulsed ALD, reference numeral 720 designates the application of 5s O in each cycle 3 The ferroelectric polarization of the ferrite layer obtained by pulsed ALD is shown at 730, where 0.5s O is applied in each cycle 3 The ferroelectric polarization intensity of the ferroelectric layer obtained by pulsed ALD after being treated by an oxidizing solution. It can be seen that the ferroelectric polarization as indicated by reference numeral 730 is significantly better than the ferroelectric polarization as indicated by reference numeral 710 and is substantially comparable to the ferroelectric polarization as indicated by reference numeral 720. Therefore, by using the method according to the present disclosure, for example, as shown in fig. 5, the production efficiency of the ferroelectric memory can be significantly improved. Furthermore, since the method 500 does not involve sputtering, the reliability of the ferroelectric memory can also be significantly improved compared to ferroelectric memories formed by using PVD sputtering methods.
In another embodiment, a sacrificial electrode layer may be formed over the ferroelectric layer formed by, for example, ALD, prior to 506. Subsequently, a rapid thermal annealing process is performed on the substrate including the first electrode layer, the ferroelectric layer, and the sacrificial electrode layer, and thereafter, the sacrificial electrode layer is removed to continue performing the method 500 from 506.
Fig. 8 shows a schematic diagram of performance comparison of a ferroelectric memory obtained by the method according to this embodiment with a conventional ferroelectric memory. For defects in the ferroelectric layer, when the defects are proper, the polarization characteristics of the ferroelectric layer are strong, for example, 10. Mu.C/cm can be reached 2 As indicated above by reference numeral 810, but the cycle erase life is low, for example, below 1E8, as indicated by reference numeral 820. While when the defects are smaller, the ferroelectric layer has weaker polarization characteristics, for example, at 10. Mu.C/cm 2 Hereinafter, as indicated by reference numeral 830, the cycle erase life may be high, for example, may reach 1E8 or more, as indicated by reference numeral 840. In this embodiment, HZO film may be deposited by ALD, for example, by adjusting O 3 The pulse time control has proper amount of defects, and the combination of the stress provided by the sacrificial electrode in the thermal annealing process can assist HZO crystallization to obtain more ferroelectric crystal phases so as to enhance the ferroelectric polarization characteristics, for example, the ferroelectric polarization characteristics can reach 10 mu C/cm 2 As indicated above by reference numeral 850. For reliability improvement, it is desirable to minimize the defect concentration in the ferroelectric layer, and then re-etch the sacrificial electrode and use it with a material such as H 2 O 2 An oxidizing solution, such as a solution, treats the ferroelectric layer to reduce the defect concentration in the ferroelectric layer to increase its cyclic erase life, which may be, for example, above 1E8, as indicated by reference numeral 860.
In this embodiment, on the one hand, the defect concentration in the ferroelectric layer during crystallization and the defect concentration in the ferroelectric layer after crystallization are controlled separately, so that the ferroelectric memory has stronger ferroelectric polarization characteristic and longer cycle erasing life. On the other hand, the deposition process of the ferroelectric layer is not influenced, and the manufacturing and production cost of the ferroelectric layer can be effectively controlled while the ferroelectric layer is lifted.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
Claims (10)
- A method for fabricating a ferroelectric memory, comprising:forming a first electrode layer on a substrate;forming a ferroelectric layer on the first electrode layer;placing the ferroelectric layer in an oxidizing solution for removing at least a portion of carbon defects and oxygen vacancy defects in the ferroelectric layer; anda second electrode layer is formed on the ferroelectric layer to form a ferroelectric capacitor of a memory cell of the ferroelectric memory.
- The method of claim 1, further comprising:after forming the second electrode layer, a rapid thermal annealing process is performed on the substrate including the first electrode layer, the ferroelectric layer, and the second electrode layer.
- The method of claim 1, further comprising:before placing the ferroelectric layer into the oxidizing solution:forming a sacrificial electrode layer on the ferroelectric layer;performing a rapid thermal annealing process on the substrate including the first electrode layer, the ferroelectric layer, and the sacrificial electrode layer; andand removing the sacrificial electrode layer.
- The method of any of claims 1-3, wherein the ferroelectric layer comprises a hafnium oxide layer, forming the ferroelectric layer on the first electrode layer comprising:the hafnium oxide layer is formed on the first electrode layer using atomic layer deposition.
- The method of claim 4, wherein forming the hafnium oxide layer on the first electrode layer using atomic layer deposition comprises:ozone gas is used to react with the hafnium oxide layer within the reaction chamber for a first period of time.
- The method of any of claims 1-5, wherein an etch rate of the oxidizing solution for the ferroelectric layer is no higher than 0.5nm per minute.
- The method of any one of claims 1-5, wherein the oxidizing solution comprises H 2 O 2 Solution, SC1 solution, H 2 SO 4 :H 2 O 2 Solution or water-soluble O 3 A solution.
- The method of claim 6, wherein the H 2 O 2 H in solution 2 O 2 Is between 0.1% and 60% by mass;the H is 2 SO 4 :H 2 O 2 H in solution 2 O 2 The mass percentage is between 0.1% and 60%, H 2 SO 4 Is between 0.1% and 98% by mass; andthe water-soluble O 3 O in solution 3 Is between 0.01mg/L and 10 mg/L.
- The method of any of claims 1-8, further comprising:detecting ferroelectric polarization characteristics of the ferroelectric capacitor; andthe oxidizing solution is adjusted based on the ferroelectric polarization characteristic.
- A ferroelectric memory made by the method of any one of claims 1-9.
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