CN116544182A - Ultrathin wafer manufacturing process capable of uniformly releasing stress - Google Patents

Ultrathin wafer manufacturing process capable of uniformly releasing stress Download PDF

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Publication number
CN116544182A
CN116544182A CN202211730416.XA CN202211730416A CN116544182A CN 116544182 A CN116544182 A CN 116544182A CN 202211730416 A CN202211730416 A CN 202211730416A CN 116544182 A CN116544182 A CN 116544182A
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CN
China
Prior art keywords
wafer
carrier plate
glass carrier
back surface
cutting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211730416.XA
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Chinese (zh)
Inventor
严立巍
朱亦峰
刘文杰
马晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Tongxinqi Technology Co ltd
Zhongsheng Kunpeng Optoelectronic Semiconductor Co ltd
Original Assignee
Zhejiang Tongxinqi Technology Co ltd
Zhongsheng Kunpeng Optoelectronic Semiconductor Co ltd
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Application filed by Zhejiang Tongxinqi Technology Co ltd, Zhongsheng Kunpeng Optoelectronic Semiconductor Co ltd filed Critical Zhejiang Tongxinqi Technology Co ltd
Priority to CN202211730416.XA priority Critical patent/CN116544182A/en
Publication of CN116544182A publication Critical patent/CN116544182A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/38—Removing material by boring or cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Dicing (AREA)

Abstract

The invention relates to the technical field of ultrathin wafer manufacturing, in particular to an ultrathin wafer manufacturing process capable of uniformly releasing stress, which comprises the following steps of: s1, taking a wafer with the front surface capable of resisting a high-temperature process, bonding the front surface of the wafer on a glass carrier plate, thinning the back surface of the wafer, cutting the back surface of the wafer by adopting laser after thinning the back surface of the wafer, forming a cutting channel on the back surface of the wafer, and performing invisible laser cutting on the rest wafer at the cutting channel; before the high-temperature tempering of the wafer and the related processes of depositing Ti, ni, ag metals and the like, the surface of the wafer is cut by laser to form groove-shaped cutting channels, so that when the wafer is processed later, the wafer can be bent at a small angle due to the existence of the cutting channels, so that the stress generated by the processing of the wafer is eliminated, and the wafer is not easy to be damaged due to the stress when the wafer with the thickness of less than 60 mu m is manufactured.

Description

Ultrathin wafer manufacturing process capable of uniformly releasing stress
Technical Field
The invention relates to the technical field of ultrathin wafer manufacturing, in particular to an ultrathin wafer manufacturing process capable of uniformly releasing stress.
Background
The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, the original material of the wafer is silicon, and a silicon wafer, namely the wafer, is formed after grinding, polishing and slicing a silicon crystal bar.
The manufacturing method of the wafer is as a processing technology of the IGBT wafer proposed in patent application No. CN202110273974.7, and can process the ultra-thin IGBT wafer.
When the wafer is required to be cut into grains after being manufactured, the manufactured wafer is often directly cut, and the method for cutting the wafer for preparing the sensor chip into the grains has the characteristic of high yield of the cut grains as proposed in patent application number CN 201110106835.1.
In the prior art, as the processing technology proposed in the patent application number CN202110273974.7 and the method proposed in the patent application number CN201110106835.1 divide the wafer fabrication and dicing into two independent parts, and along with the reduction of the requirements for the fabrication consumables and the product size, the wafer fabrication has the original thinner requirement, and when the ultra-thin wafer with the thickness of less than 60 μm is fabricated, the wafer is easy to be damaged due to stress in the process of performing the wafer fabrication technology and dicing.
Disclosure of Invention
The present invention is directed to a process for manufacturing an ultra-thin wafer capable of uniformly releasing stress, so as to solve the problems set forth in the background art.
The aim of the invention can be achieved by the following technical scheme:
a manufacturing process of an ultrathin wafer capable of uniformly releasing stress comprises the following steps:
s1, taking a wafer with the front surface capable of resisting a high-temperature process, bonding the front surface of the wafer on a glass carrier plate, thinning the back surface of the wafer, cutting the back surface of the wafer by adopting laser after thinning the back surface of the wafer, forming a cutting channel on the back surface of the wafer, and performing invisible laser cutting on the rest wafer at the cutting channel;
s2, debonding the glass carrier plate, taking down the glass carrier plate, turning over the wafer, attaching the back surface of the wafer to a quartz carrier plate, coating SOG on the back surface of the wafer, fixing the wafer in the quartz carrier plate, tempering the wafer at high temperature, manufacturing a metal layer on the front surface of the wafer after tempering at high temperature, cutting SOG on the edge of the wafer by adopting laser, removing the quartz carrier plate, turning over the wafer, and fixing the front surface of the wafer to the glass carrier plate;
s3, depositing Ti, ni and Ag on the back of the wafer obtained in the step S2, and then cutting Ti, ni and Ag at the bottom of the inner wall of the cutting channel by using laser;
s4, turning the wafer obtained in the step S3, attaching the back surface of the wafer to the dicing film frame, removing the glass carrier disc, and finally expanding the wafer to crack the wafer into grains along dicing channels and invisible laser dicing positions formed in the step S1.
Preferably, in the step S1, bonding is performed on the wafer and the glass carrier by using an adhesive, in the step S2, bonding is performed on the glass carrier by using UV light Jie Jian, and after the glass carrier is removed, the adhesive remaining on the surface of the wafer is removed by using a solvent for cleaning.
Preferably, in the step S2, the glass carrier plate is provided with a small hole, and air is extracted from the bottom of the glass carrier plate, and the wafer is fixed on the glass carrier plate through the small hole in an adsorption manner, and in the step S4, when the glass carrier plate is removed, the air extraction of the air extraction device is stopped, and the glass carrier plate and the wafer are directly separated, so that the glass carrier plate can be removed.
Preferably, in the step S2, the maximum temperature is 1000 ° when the wafer is tempered at a high temperature.
Preferably, in the step S3, a chemical vapor deposition method is used to deposit Ti, ni, and Ag on the back surface of the wafer, and the Ti, ni, and Ag are sequentially deposited, so that the deposited Ti, ni, and Ag partially fall into the scribe line.
Preferably, in the step S2, SOG may be removed by solvent etching, and then the quartz carrier plate is removed.
Preferably, in the step S3, after depositing Ti, ni, ag on the back surface of the wafer, ti, ni, ag at the bottom of the scribe line may be removed by solvent etching.
Preferably, in the step S1, the depth of the scribe line formed on the back surface of the wafer is not more than half the thickness of the wafer, and the invisible laser scribe position is located below the scribe line, so as to form an easily separable modified layer on the wafer.
The invention has the beneficial effects that:
before the high-temperature tempering of the wafer and the related processes of depositing Ti, ni, ag metals and the like, the surface of the wafer is cut by laser to form a groove-shaped cutting channel, so that when the wafer is processed later, the wafer can be bent at a small angle due to the existence of the cutting channel, so that the stress generated by processing the wafer is eliminated, the wafer is not easy to damage due to the stress when the wafer with the thickness of less than 60 mu m is manufactured, the wafer can be directly transferred without using equipment such as a glass carrier plate and the like when the wafer is transferred, the process steps are simplified, and finally, the wafer is cracked along the direction of the cutting channel, so that the redundant loss of the wafer is not generated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to those skilled in the art that other drawings can be obtained according to these drawings without inventive effort;
FIG. 1 is a schematic flow chart of step S1 of the present invention;
FIG. 2 is a flow chart of step S2 of the present invention;
FIG. 3 is a flow chart of step S3 of the present invention;
fig. 4 is a schematic flow chart of step S4 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A manufacturing process of an ultrathin wafer capable of uniformly releasing stress comprises the following steps:
s1, taking a wafer with the front surface capable of resisting a high-temperature process, bonding the front surface of the wafer on a glass carrier plate, thinning the back surface of the wafer, cutting the back surface of the wafer by adopting laser after thinning the back surface of the wafer, forming a cutting channel on the back surface of the wafer, and performing invisible laser cutting on the rest wafer at the cutting channel;
s2, debonding the glass carrier plate, taking down the glass carrier plate, turning over the wafer, attaching the back surface of the wafer to a quartz carrier plate, coating SOG on the back surface of the wafer, fixing the wafer in the quartz carrier plate, tempering the wafer at high temperature, manufacturing a metal layer on the front surface of the wafer after tempering at high temperature, cutting SOG on the edge of the wafer by adopting laser, removing the quartz carrier plate, turning over the wafer, and fixing the front surface of the wafer to the glass carrier plate;
s3, depositing Ti, ni and Ag on the back of the wafer obtained in the step S2, and then cutting Ti, ni and Ag at the bottom of the inner wall of the cutting channel by using laser;
s4, turning the wafer obtained in the step S3, attaching the back surface of the wafer to the dicing film frame, removing the glass carrier disc, and finally expanding the wafer to crack the wafer into grains along dicing channels and invisible laser dicing positions formed in the step S1.
In step S1, the thinned wafer has a thickness of no more than 60 μm, and when dicing the wafer into streets, the wafer is not cut, and only groove-shaped streets and modified layers below the streets are formed on the wafer surface
In the step S1, bonding is performed on the wafer and the glass carrier plate by using an adhesive, in the step S2, bonding is performed on the glass carrier plate by using UV light Jie Jian, and after the glass carrier plate is removed, the adhesive remained on the surface of the wafer is removed by using a solvent for cleaning.
The adhesive is UV glue, loses viscosity after UV illumination, so that the glass carrier plate can be directly taken down after the bonding is released by the UV illumination.
In the step S2, the glass carrier plate is provided with a small hole, and air is extracted from the bottom of the glass carrier plate, and the wafer is adsorbed and fixed on the glass carrier plate through the small hole, and in the step S4, when the glass carrier plate is removed, the air extraction of the air extraction device is stopped, and the glass carrier plate and the wafer are directly separated, so that the glass carrier plate can be removed.
In the step S2, the maximum temperature is 1000 ℃ when the wafer is tempered at a high temperature.
When the high-temperature tempering is carried out, the high temperature resistance of the graphite carrying disc and the SOG exceeds 1000 ℃, so that the graphite carrying disc is used for carrying the wafer, the SOG is used for fixing, the property of the wafer can be more stable through the high-temperature tempering, and the internal stress of the wafer is reduced.
In the step S3, a chemical vapor deposition method is adopted when Ti, ni, ag are deposited on the back surface of the wafer, and Ti, ni, ag are sequentially deposited, and the deposited Ti, ni, ag portion falls into the scribe line.
In the step S2, SOG may also be removed by means of solvent etching, and then the quartz carrier plate is removed.
In the step S3, after depositing Ti, ni, ag on the back surface of the wafer, ti, ni, ag at the bottom of the scribe line may be removed by solvent etching.
In the step S1, the depth of the scribe line formed on the back surface of the wafer is not more than half the thickness of the wafer, and the invisible laser scribe position is located below the scribe line, so as to form an easily separable modified layer on the wafer.
Compared with the related art, the manufacturing process of the ultrathin wafer capable of uniformly releasing stress has the following beneficial effects:
before the high-temperature tempering of the wafer and the related processes of depositing Ti, ni, ag metals and the like, the surface of the wafer is cut by laser to form a groove-shaped cutting channel, so that when the wafer is processed later, the wafer can be bent at a small angle due to the existence of the cutting channel, so that the stress generated by processing the wafer is eliminated, the wafer is not easy to damage due to the stress when the wafer with the thickness of less than 60 mu m is manufactured, the wafer can be directly transferred without using equipment such as a glass carrier plate and the like when the wafer is transferred, the process steps are simplified, and finally, the wafer is cracked along the direction of the cutting channel, so that the redundant loss of the wafer is not generated.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims.

Claims (8)

1. The process for manufacturing the ultrathin wafer capable of uniformly releasing stress is characterized by comprising the following steps of:
s1, taking a wafer with the front surface capable of resisting a high-temperature process, bonding the front surface of the wafer on a glass carrier plate, thinning the back surface of the wafer, cutting the back surface of the wafer by adopting laser after thinning the back surface of the wafer, forming a cutting channel on the back surface of the wafer, and performing invisible laser cutting on the rest wafer at the cutting channel;
s2, debonding the glass carrier plate, taking down the glass carrier plate, turning over the wafer, attaching the back surface of the wafer to a quartz carrier plate, coating SOG on the back surface of the wafer, fixing the wafer in the quartz carrier plate, tempering the wafer at high temperature, manufacturing a metal layer on the front surface of the wafer after tempering at high temperature, cutting SOG on the edge of the wafer by adopting laser, removing the quartz carrier plate, turning over the wafer, and fixing the front surface of the wafer to the glass carrier plate;
s3, depositing Ti, ni and Ag on the back of the wafer obtained in the step S2, and then cutting Ti, ni and Ag at the bottom of the inner wall of the cutting channel by using laser;
s4, turning the wafer obtained in the step S3, attaching the back surface of the wafer to the dicing film frame, removing the glass carrier disc, and finally expanding the wafer to crack the wafer into grains along dicing channels and invisible laser dicing positions formed in the step S1.
2. The process for manufacturing an ultra-thin wafer capable of uniformly releasing stress according to claim 1, wherein in the step S1, bonding is performed on the wafer and the glass carrier by using an adhesive, in the step S2, bonding is performed on the glass carrier by using UV light Jie Jian, and after the glass carrier is removed, the residual adhesive on the surface of the wafer is removed by using a solvent.
3. The process of claim 1, wherein in step S2, the glass carrier plate is provided with holes, and suction is performed from the bottom of the glass carrier plate, and the wafer is fixed to the glass carrier plate through the suction holes, and in step S4, the suction of the suction device is stopped when the glass carrier plate is removed, and the removal of the glass carrier plate is completed by directly separating the glass carrier plate from the wafer.
4. The process according to claim 1, wherein in the step S2, the maximum temperature is 1000 ° when the wafer is tempered at high temperature.
5. The process of claim 1, wherein in step S3, a chemical vapor deposition method is used to deposit Ti, ni, and Ag on the back of the wafer, and the Ti, ni, and Ag are sequentially deposited, so that the deposited Ti, ni, and Ag partially falls into the scribe line.
6. The process of claim 5, wherein in step S2, SOG is removed by solvent etching, and then the quartz carrier is removed.
7. The process of claim 6, wherein in the step S3, after depositing Ti, ni, ag on the back surface of the wafer, the solvent etching may be used to remove Ti, ni, ag at the bottom of the scribe line.
8. The process of claim 1, wherein in the step S1, the depth of the scribe line formed on the back surface of the wafer is not more than half the thickness of the wafer, and the invisible laser scribe position is located below the scribe line to form an easily separable modified layer on the wafer.
CN202211730416.XA 2022-12-30 2022-12-30 Ultrathin wafer manufacturing process capable of uniformly releasing stress Pending CN116544182A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211730416.XA CN116544182A (en) 2022-12-30 2022-12-30 Ultrathin wafer manufacturing process capable of uniformly releasing stress

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211730416.XA CN116544182A (en) 2022-12-30 2022-12-30 Ultrathin wafer manufacturing process capable of uniformly releasing stress

Publications (1)

Publication Number Publication Date
CN116544182A true CN116544182A (en) 2023-08-04

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Family Applications (1)

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Country Status (1)

Country Link
CN (1) CN116544182A (en)

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