CN115701687A - Calibration device and method for pipelined analog-to-digital conversion circuit and radar - Google Patents

Abstract

The calibration device, the calibration method and the radar for the pipelined analog-to-digital conversion circuit are characterized in that the pipelined analog-to-digital conversion circuit comprises a first-stage conversion module and a rear-end conversion module which is cascaded with the first-stage conversion module and is provided with at least one stage of conversion module, wherein the first-stage conversion module comprises a sub analog-to-digital conversion unit which is composed of at least one comparator; the calibration method comprises the following steps: inputting a test analog signal to the first-stage conversion module; acquiring a jump output voltage which is output by the first-stage conversion module and corresponds to a jump signal at the output end of the comparator; judging whether a preset reference threshold of the comparator has deviation relative to a theoretical reference threshold or not according to the skip output voltage; and when the preset reference threshold value of the comparator is determined to have deviation relative to the theoretical reference threshold value, adjusting the preset comparison threshold value of the comparator. The method can realize aperture error calibration of the pipelined analog-to-digital conversion circuit without the sampling hold structure and improve conversion precision.

Description

Calibration device and method for pipelined analog-to-digital conversion circuit and radar

Technical Field

The embodiments of the present disclosure relate to the field of integrated circuits, and in particular, to a calibration apparatus and method for a pipelined analog-to-digital conversion circuit, and a radar.

Background

Many physical quantities in nature (such as speed, pressure, temperature, sound, etc.) vary continuously in time and also continuously in amplitude, such continuously varying physical quantities are called analog quantities, and signals representing the analog quantities are called analog signals.

Another type of physical quantity corresponding to an analog quantity is called a digital quantity, which is a numerical value obtained at a series of discrete time instants, and the magnitude and increase and decrease of the numerical value are integer multiples of quantization, that is, they are a series of time-discrete, numerical-discrete signals. A Signal representing a Digital quantity is called a Digital Signal (Digital Signal).

With the widespread use of computers, most electronic systems employ computers to process signals, and the computers cannot directly process Analog signals but only Digital signals, so that Analog/Digital (a/D) conversion technology is required to convert Analog signals into Digital signals, and a circuit for converting Analog signals into Digital signals can be referred to as an Analog-to-Digital conversion circuit.

The analog-to-digital conversion process mainly comprises the following steps: 1) In the sampling stage, sampling is carried out on the analog signal to obtain an analog sampling signal which is discrete in time and continuous in amplitude, wherein the continuous amplitude means that the amplitude is not quantized and is still the same as the amplitude of the analog signal; 2) In the holding stage, the amplitude (namely sampling value) of the analog signal is held when the sampling stage is switched to the holding stage, the analog holding signal which is discrete in time and takes the sampling value as the amplitude is obtained, a quantization unit is selected, the sampling value is divided by the quantization unit and an integer is taken, the signal quantization (digitization) is realized, and the digital quantity which is discrete in time and also discrete in numerical value is obtained; 3) And coding the digital quantity to obtain a corresponding digital code to form a digital signal.

For the convenience of computer use, a binary coding method is generally adopted to obtain a digital code with a certain number of bits, and the number of bits of the digital code is usually used to represent the number of bits of a digital signal, such as a 10-bit (bit) digital signal. The more bits a digital signal takes, the more accurately an analog signal can be reflected.

In the quantization process of the analog-to-digital conversion, a plurality of comparators are usually used to compare the analog hold signals to obtain the quantization result. Therefore, the more the number of comparators is, the higher the quantization precision is, and the more accurate the output digital signal is, without changing other parameters. However, due to the limitation of some indexes such as space layout, cost, performance and the like, a digital signal with more bits cannot be obtained by simply and roughly adding comparators.

For example, to convert an analog signal into a 10-bit digital signal, in principle, 1023 comparators may be used to output 1024 digital quantities, and the obtained digital quantities are encoded to obtain a 10-bit digital signal. A 10bit digital signal would require thousands of comparators and it is thought that this is not possible in practice.

In order to obtain digital signals with more digits under a certain number of comparators, the structure of the analog-to-digital conversion circuit is optimized, and analog-to-digital conversion circuits such as a successive approximation type, an integral type, a pressure-frequency conversion type, a hierarchical type and a pipeline type appear, and the analog-to-digital conversion circuits of the successive approximation type, the integral type and the pressure-frequency conversion type are mainly applied to analog-to-digital conversion scenes with medium-low speed and low precision. The hierarchical and pipelined analog-to-digital conversion circuits can be applied to analog-to-digital conversion scenes with higher speed and higher precision, for example, transient signal processing under the condition of high speed.

A hierarchical quantization structure exists in the pipelined analog-to-digital conversion circuit, and conversion work such as sampling, quantization, coding and the like is carried out through a multi-level low-precision conversion module. For each stage of conversion module, the rapid analog-to-digital conversion of the stage can be realized by adopting a small number of comparators, and the method is the mainstream choice for realizing the high-speed high-precision analog-to-digital conversion circuit at present.

In some pipelined analog-to-digital conversion circuits, sampling is usually performed by a Sample-and-hold Amplifier (SHA) to obtain a Sample-and-hold signal, and then the Sample-and-hold signal is input to each stage of conversion module for analog-to-digital conversion. Wherein except the last conversion module, the conversion modules of other grades all include: a Sub-stage Analog-to-Digital conversion unit (Sub-ADC) and a gain Digital-to-Analog Converter (MDAC). However, SHA usually consumes more power, and in order to save power consumption, SHA is eliminated in some pipelined analog-to-digital conversion circuits, and the analog signal is directly input to the conversion module of the first stage.

However, a major problem of such pipelined ADCs that do not include SHA is that, because the analog signal may fluctuate over time, there is bandwidth mismatch in the sampling paths of both the Sub-ADC and the MDAC within the first stage conversion module, resulting in aperture error. The aperture error may cause the position of the transmission curve jump level to shift, and the corresponding output voltage range may become large, which affects the precision of the pipelined analog-to-digital conversion circuit.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a calibration apparatus and method for a pipelined analog-to-digital conversion circuit, and a radar, which can implement aperture error calibration for a pipelined analog-to-digital conversion circuit without a sample-and-hold structure, and further can improve the precision of the pipelined analog-to-digital conversion circuit.

Firstly, an embodiment of the present invention provides a calibration method for a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a first-stage conversion module and a back-end conversion module cascaded thereto and having at least one stage of conversion module, and the first-stage conversion module includes a sub-analog-to-digital conversion unit formed by at least one comparator; the calibration method comprises the following steps:

inputting a test analog signal to the first-stage conversion module;

acquiring a skip output voltage which is output by the first-stage conversion module and corresponds to a skip signal at the output end of the comparator;

judging whether a preset reference threshold of the comparator has deviation relative to a theoretical reference threshold or not according to the skip output voltage;

and when the preset reference threshold value of the comparator is determined to have deviation relative to the theoretical reference threshold value, adjusting the preset comparison threshold value of the comparator.

Optionally, the determining, according to the skip output voltage, whether a preset reference threshold of the comparator has a deviation with respect to a theoretical reference threshold further includes:

determining jump digital information corresponding to the first-stage conversion module according to the jump output voltage;

and determining whether the measurement output interval of the first-stage conversion module is consistent with a theoretical output interval or not according to the jump digital information, and determining that the preset reference threshold of the comparator has deviation relative to the theoretical reference threshold when the measurement output interval of the first-stage conversion module is inconsistent with the theoretical output interval.

The determining skip digital information corresponding to the first-stage conversion module according to the skip output voltage further includes:

acquiring digital residual error information corresponding to the jump output voltage and test digital information corresponding to the test analog signal and output by the rear-end conversion module;

and determining jump digital information corresponding to the first-stage conversion module according to the digital residual error information and the test digital information.

Optionally, the determining whether there is a deviation in a preset threshold of the comparator according to the skip output voltage further includes:

and comparing the jump output voltage with a preset output voltage threshold, and determining that the preset reference threshold of the comparator has deviation relative to a theoretical reference threshold when the jump output voltage and the preset output voltage are inconsistent.

Optionally, when it is determined that the preset reference threshold of the comparator is deviated from the theoretical reference threshold, adjusting the preset comparison threshold of the comparator includes:

when the preset reference threshold value of the comparator is determined to be smaller than the corresponding theoretical reference threshold value, controlling to increase the preset comparison threshold value of the comparator;

and when the preset reference threshold value of the comparator is determined to be larger than the corresponding theoretical reference threshold value, controlling to reduce the preset comparison threshold value of the comparator.

The embodiment of the invention also provides a calibration device for the pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit comprises a first-stage conversion module and a cascaded back-end conversion module with at least one stage of conversion module, and the first-stage conversion module comprises a sub analog-to-digital conversion unit consisting of at least one comparator; the calibration device includes:

the signal generating module is suitable for generating a test analog signal and inputting the test analog signal to the first-stage conversion module in the pipelined analog-to-digital conversion circuit;

the deviation determining module is suitable for acquiring a jump output voltage which is output by the first-stage conversion module and corresponds to a jump signal at the output end of the comparator; judging whether a preset reference threshold of the comparator has deviation relative to a theoretical reference threshold or not according to the skip output voltage;

and the deviation adjusting module is suitable for adjusting the preset comparison threshold value of the comparator when the deviation determining module determines that the preset reference threshold value of the comparator has deviation relative to the theoretical reference threshold value.

Optionally, the deviation determining module includes:

the digital information acquisition unit is suitable for determining jump digital information corresponding to the first-stage conversion module according to the jump output voltage;

and the deviation calculation unit is suitable for determining whether the measurement output interval of the first-stage conversion module is consistent with the theoretical output interval or not according to the jump digital information acquired by the digital information acquisition unit, and determining that the preset reference threshold of the comparator has deviation relative to the theoretical reference threshold when the measurement output interval of the first-stage conversion module is inconsistent with the theoretical output interval.

Optionally, the digital information obtaining unit includes: the digital calculation subunit is suitable for acquiring digital residual error information corresponding to the jump output voltage and test digital information corresponding to the test analog signal and output by the rear-end conversion module; and determining jump digital information corresponding to the first-stage conversion module according to the digital residual error information and the test digital information.

Optionally, the deviation determining module comprises: and the comparison unit is suitable for comparing the jump output voltage with a preset output voltage threshold value and outputting a corresponding feedback signal based on a comparison result, wherein when the jump output voltage and the preset output voltage threshold value are inconsistent, the preset reference threshold value of the comparator is determined to have deviation relative to a theoretical reference threshold value.

Optionally, the deviation adjusting module is adapted to control to increase the preset comparison threshold of the comparator when it is determined that the preset reference threshold of the comparator is smaller than the corresponding theoretical reference threshold; and controlling to reduce the preset comparison reference threshold value of the comparator when the preset reference threshold value of the comparator is determined to be larger than the corresponding theoretical reference threshold value.

Optionally, the comparator comprises:

the pre-amplification part is suitable for inputting a corresponding preset reference threshold value at a first input end, inputting the test analog signal at a second input end, outputting an amplified signal corresponding to the preset reference threshold value at a first output end and outputting an amplified signal corresponding to the test analog signal at a second output end;

a latch component having a first input coupled to the first output of the pre-amplification component; a second input thereof is coupled to the second output of the pre-amplifying means, and an output thereof is adapted to output a comparison result based on a magnitude relation of the first input and the second input.

Optionally, the offset adjustment module comprises:

a charge storage unit group comprising a plurality of first charge storage units and a plurality of second charge storage units, wherein: each first charge energy storage unit is coupled between the first output end of the pre-amplification part and the ground, and each second charge energy storage unit is coupled between the second output end of the pre-amplification part and the ground;

a switch unit group including a plurality of first switches and a plurality of second switches, wherein: each first switch is coupled between the corresponding first charge energy storage unit and the ground, and each second switch is coupled between the corresponding second charge energy storage unit and the ground;

the switch control unit is suitable for turning on a first switch between a part of or all first charge energy storage units coupled with the first output end of the pre-amplification part and the ground when the preset reference threshold value of the comparator is determined to be smaller than the theoretical reference threshold value of the comparator; and when the preset reference threshold value of the comparator is determined to be smaller than the theoretical reference threshold value of the corresponding comparator, turning on a second switch between part or all of the second charge energy storage units coupled to the first output end of the pre-amplification part and the ground.

An embodiment of the present invention further provides a radar, including: the detection device, the analog-to-digital conversion circuit and the calibration device of any of the previous embodiments; wherein:

the detection device is suitable for collecting echo signals and outputting analog signals to be processed to the analog-to-digital conversion circuit;

the analog-to-digital conversion circuit is suitable for performing analog-to-digital conversion on the analog signal to be processed of the detection device or the test analog signal of the calibration device; the device comprises a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit comprises a first-stage conversion module, a rear-end conversion module and a digital calculation module, wherein the rear-end conversion module is cascaded with the first-stage conversion module and is provided with at least one stage of conversion module;

the calibration device is suitable for calibrating the aperture error of the pipelined analog-to-digital conversion circuit by inputting a test analog signal to the pipelined analog-to-digital conversion circuit.

Optionally, the radar further comprises: and the control device is suitable for controlling the calibration device to calibrate the pipelined analog-to-digital conversion circuit after the radar is powered on, controlling the calibration device to finish calibration after the calibration finishing condition is met, and enabling the analog-to-digital conversion circuit to perform analog-to-digital conversion processing on the analog signal to be processed.

For the pipelined analog-to-digital conversion circuit without the sampling and holding structure, by adopting the calibration scheme of the embodiment of the invention, a test analog signal is input into a first-stage conversion module, a jump output voltage which is output by the first-stage conversion module and corresponds to a jump signal at the output end of a comparator of a sub analog-to-digital conversion unit in the first-stage conversion module is obtained, whether a preset reference threshold of the comparator has deviation relative to a theoretical reference threshold is judged according to the jump output voltage, and when the preset reference threshold of the comparator is determined to have deviation relative to the theoretical reference threshold, the preset comparison threshold of the comparator is adjusted.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings needed to be used in the embodiments of the present specification or in the description of the prior art will be briefly described below, it is obvious that the drawings described below are only some embodiments of the present specification, and it is also possible for a person skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a schematic diagram of a prior art framework of a pipelined analog-to-digital conversion circuit.

Fig. 2 is a schematic diagram showing a frame structure of another pipeline analog-to-digital conversion circuit in the prior art.

Fig. 3 shows a schematic diagram of a sub-analog-to-digital conversion unit used in fig. 1 and 2.

Fig. 4 shows a schematic representation of a transmission characteristic curve of a conversion module in an embodiment of the invention.

Fig. 5 is a schematic structural diagram illustrating a calibration apparatus for a pipeline analog-to-digital conversion circuit according to an embodiment of the present invention.

Fig. 6a shows a schematic circuit diagram of a ramp generator applied in the embodiment of the present invention.

Fig. 6b is a waveform diagram of an analog signal output by the ramp generator circuit shown in fig. 6 a.

Fig. 7a shows a schematic structural diagram of an offset determining module in an embodiment of the present invention.

Fig. 7b shows a schematic structural diagram of another deviation determination module in an embodiment of the present invention.

Fig. 8 is a schematic diagram illustrating a calibration scenario for a pipelined analog-to-digital conversion circuit according to an embodiment of the present invention.

Fig. 9 shows a schematic structural diagram of an offset adjustment module in an embodiment of the present invention.

Fig. 10 is a flowchart illustrating a calibration method for a pipelined analog-to-digital conversion circuit according to an embodiment of the present invention.

Fig. 11 shows a flowchart of determining whether there is a deviation of the preset reference threshold of the comparator in the embodiment of the present invention.

Fig. 12 shows a schematic structure of a seven-stage pipelined analog-to-digital conversion circuit.

Fig. 13 shows a schematic structural diagram of a radar in an embodiment of the present invention.

Detailed Description

In order to make the solution provided by the present disclosure more clearly understood and implemented by those skilled in the art, a schematic description is first given below with reference to the accompanying drawings and specific application scenarios.

Referring to fig. 1, in a schematic structural diagram of a pipeline analog-to-digital conversion circuit in the prior art, in practical application, as shown in fig. 1, a pipeline analog-to-digital conversion circuit P0 includes: the digital signal processing circuit comprises a clock generation sub-circuit 01, a band-gap reference sub-circuit 02, a sample-hold amplification module 03, N cascaded conversion modules Stage1 to Stage N and a digital calculation module 04. The respective components thereof will be briefly described below.

The clock generating sub-circuit 01, as a clock source of the pipelined analog-to-digital converting circuit P0, is adapted to generate a plurality of clock signals whose phases are not overlapped, and respectively provide the plurality of clock signals whose phases are not overlapped to the sample-hold amplifying module 03 and the converting modules Stage1 to Stage n at each Stage, so as to control the devices in the sample-hold amplifying module 03 and the converting modules at each Stage to alternately operate by using different time sequences.

The bandgap reference sub-circuit 02 is used as a reference signal source of the pipelined analog-to-digital conversion circuit P0, and is adapted to generate a reference current and a reference voltage, and provide the generated reference current and reference voltage to the sample-hold amplifying module 03 and the conversion modules Stage1 to Stage n, respectively.

Specifically, in an alternative example, as shown in fig. 1, the bandgap reference sub-circuit 02 may include: a band gap generating module 021, a reference current generating module 022, and a reference voltage generating module 023. Wherein:

the Bandgap generation module 021, serving as a Bandgap reference source (Bandgap) of the pipelined analog-to-digital conversion circuit P0, is adapted to provide temperature-insensitive reference electrical signals, such as a reference voltage signal and a reference current signal.

The reference current generating module 022, as a reference current source of the pipelined analog-to-digital conversion circuit P0, is adapted to generate a reference current according to the reference electrical signal, and provide the generated reference current to the sample-hold amplifying module 03 and the conversion modules Stage1 to Stage n, respectively.

The reference voltage generating module 023 is used as a reference voltage source of the pipelined analog-to-digital converting circuit P0, and is adapted to generate a reference voltage according to the reference electrical signal, and provide the generated reference voltage to the sample-hold amplifying module 03 and the Stage converting modules Stage1 to Stage n, respectively.

Further, since the reference voltage is generally used to drive the capacitor, and the capacitor has a charging time and a discharging time, in order to enable the capacitor to perform efficient charging and discharging operations and provide a precise setup time for the reference voltage generation module 023, the bandgap reference sub-circuit 02 may further include a reference voltage buffering module 024 adapted to buffer the reference voltage output by the reference voltage generation module 023. The Reference voltage Buffer module 024 may specifically include a Buffer (Reference Buffer).

In addition, since a pipelined analog-to-digital conversion circuit generally requires two reference voltages of different levels, for example, a reference voltage of a positive level and a reference voltage of a negative level, for this purpose, the reference voltage generation module 023 may generate the reference voltages of two different levels by level shifting, and thus, the precision and the setup time of the reference voltage output by the reference voltage generation module 023 may be ensured by the reference voltage buffer module 024.

The sample-hold amplifying module 03 is adapted to sample the analog signal input to the pipelined analog-to-digital conversion circuit P0 to obtain an analog hold signal VC, and stably hold the amplitude of the analog hold signal VC until the next sampling stage comes, and perform the next sampling. Therefore, time deviation can be avoided when the conversion modules Stage1 to StageN of the subsequent cascade are processed. The Sample-Hold amplifying module 03 may include a Sample/Hold Amplifier (SHA).

It is to be understood that the above sampling embodiments may be set according to specific scenarios and requirements, and the present specification is not limited thereto.

The N cascaded conversion modules Stage1 to Stage N may specifically set the level of each conversion module according to the cascade order of each conversion module, for example, in fig. 1, the conversion module Stage1 is a first level, and the conversion module Stage2 is a second level, and the like. In each of the conversion modules Stage1 to Stage N, the conversion modules Stage1 of the first Stage to Stage N-1 of the conversion module Stage1 of the N-1 th Stage have the same internal structure. Taking the first Stage of the conversion module Stage1 as an example, as shown in fig. 1, the conversion module Stage1 may include: a Sub Analog to Digital conversion unit (Sub-ADC) 11 and a gain Digital to Analog Converter (MDAC) 12.

The sub-adc 11 may sample, quantize, and encode the received input signal to obtain a first-stage thermometer code DS1, and output the first-stage thermometer code DS1 to the gain dac 12 and the digital computation module 04, respectively. The number of thermometer codes that the sub-analog-to-digital conversion unit 11 can generate is related to the precision of the sub-analog-to-digital conversion unit. If the precision of the sub-ADC 11 is x bits, the sub-ADC 11 can generate 2 ^x -a 1-bit thermometer code.

The gain digital-to-analog conversion unit 12 may specifically include: an arithmetic unit 121, a Sub-digital-to-analog conversion unit (Sub-DAC) 122, and an amplification unit 123. Here, the accuracy of the gain digital-to-analog conversion unit 12 is generally equal to the accuracy of the sub analog-to-digital conversion unit 11. If the sub-adc 11 has an accuracy of x bits, the gain adc 12 also has an accuracy of x bits.

Specifically, the sub digital-to-analog converting unit 122 is adapted to receive the first-stage thermometer code DS1 output by the sub analog-to-digital converting unit 11, convert the first-stage thermometer code DS1 into a corresponding first-stage analog component, and output the first-stage analog component to the arithmetic unit 121. The operation unit 121 is adapted to receive the analog hold signal VC output by the sample-and-hold amplifying module and the first-stage analog component output by the sub analog-to-digital conversion unit 11, subtract the first-stage analog component from the analog hold signal VC to obtain an operation result, and output the operation result to the amplifying unit 123. The amplifying unit 123 is adapted to receive the operation result output by the operation unit 121, amplify the operation result to obtain a first-Stage analog residual error signal VR1 with the analog residual error amount as an amplitude, and output the first-Stage analog residual error signal VR1 to the second-Stage conversion module Stage2. The amplifying unit may be an Operational Transconductance Amplifier (OTA).

The conversion modules Stage2 to Stage n-1 also include a sub-analog-to-digital conversion unit and a gain digital-to-analog conversion unit, and specific structures, functions, working principles, and the like can refer to the related description of the conversion module Stage1, and are not described herein again.

Therefore, the conversion modules Stage2 to Stage N-1 can obtain the thermometer codes and the analog residual signals of the corresponding levels according to the received input signals (i.e. the signals output by the previous conversion module), output the thermometer codes of the corresponding levels to the digital calculation module 04, and output the analog residual signals of the corresponding levels to the next conversion module, specifically referring to fig. 1, the conversion module Stage2 outputs the second-level thermometer codes DS2 to the digital calculation module 04, and outputs the second-level analog residual signals VR2 to the next conversion module (not shown in fig. 1), and so on, the conversion module Stage N-1 outputs the N-1-level thermometer codes DSN-1 to the digital calculation module 04, and outputs the N-1-level analog residual signals VRN-1 to the next conversion module Stage.

As for the conversion module StageN of the nth stage, since it is the last one of the N cascaded conversion modules, the conversion module StageN may include only a sub analog-to-digital conversion unit (not shown in fig. 1), and outputs the nth stage thermometer code DSN to the digital calculation module 04 according to the analog residual signal output from the nth-1 stage conversion module StageN-1.

It should be noted that the digits of the thermometer codes respectively output by the conversion modules Stage1 to StageN at each level may be set according to specific scenes and requirements, and the conversion modules at each level may output thermometer codes with the same digits or thermometer codes with different digits, which is not limited in this specification.

The digital computation module 04 is adapted to perform staggered addition on the thermometer codes output by the conversion modules at different levels according to the levels, so as to perform time alignment on the thermometer codes obtained by the conversion modules at different levels at different moments, and perform binary conversion to obtain binary output codes. Wherein the number of output codes generated by the digital computation module 04 is related to the accuracy of the digital computation module 04. If the precision of the digital computation module 04 is m bits, the digital computation module 04 may generate 2 ^m -1 output code. In addition, the precision of the digital computation module 04 may represent the precision of the pipeline analog-to-digital conversion circuit P0.

However, since the sample-and-hold module usually occupies a larger power consumption of the circuit, in order to save power consumption, some pipelined analog-to-digital conversion circuits omit the sample-and-hold module and directly input the analog signal to the conversion module of the first stage. As shown in fig. 2, a schematic structure of a pipelined analog-to-digital conversion circuit without a sample-and-hold module, including the pipelined analog-to-digital conversion circuit P1, except that the sample-and-hold amplification module 03 is not included, other structures, connection relationships of the modules, and operation principles can be introduced with reference to the pipelined analog-to-digital conversion circuit P0 shown in fig. 1, and are not described one by one here.

After a framework of the existing pipeline analog-to-digital conversion circuit is introduced, a specific hardware structure, a connection relationship, and the like of the sub analog-to-digital conversion unit and the gain digital-to-analog conversion unit are described below through a specific embodiment.

It should be noted that the sub-analog-to-digital conversion unit and the gain analog-to-digital conversion unit in the following examples are only used to illustrate the problems in the prior art. In practical applications, the conversion modules Stage1 to Stage n may include the following types of sub-analog-to-digital conversion units and gain analog-to-digital conversion units, or may adopt sub-analog-to-digital conversion units and gain analog-to-digital conversion units with similar structures or different structures, which is not limited in this embodiment of the present specification.

Under ideal conditions, the input and output of each conversion module in the pipelined analog-to-digital conversion circuit are in a linear relationship, and the slope is the theoretical gain. Wherein, each submodule conversion unit is responsible for carrying out comparison operation.

In an ideal ADC, the input and output of each stage should be less than full scale, so that the output signal range of the stage does not exceed the input range of the next stage, because after the input signal exceeds scale, the portion beyond scale cannot be quantized, which results in partial signal loss.

In practical applications, due to various irrational factors, the analog output signal of the present stage of MDAC may exceed the input range of the lower stage, so that the lower stage of MDAC cannot correctly process the output signal of the upper stage, resulting in a loss of the digital output of the analog-to-digital conversion circuit and a reduction in the performance of the pipeline ADC.

To ensure that the output of the MDAC of this stage does not exceed the maximum range of the output of the next stage, a method of reducing the inter-stage gain and applying a redundant bit digital correction can be generally adopted.

For example, in the schematic diagram of the transmission characteristic curve of the conversion module shown in fig. 4, if the conversion module adopts a full-scale gain (corresponding to a magnification factor of 8 times), that is, the maximum output value of the theoretical input/output curve is located on the boundary of the theoretical analog domain output range; if the amplification of each level is reduced, for example, the amplification of the second-level MDAC is changed to 4 times, as shown by the solid line in fig. 4, and the cascade is added, the measurement margin of each level is left, so that the measurement can be measured even if the reference threshold of the comparator is changed.

For example, a 3-bit Sub-ADC output range is 0 to 7, while a 4-bit Sub-ADC output range is 0 to 15, so that when a 4-bit Sub-ADC is used to output the output of the original 3-bit range, it occupies only half the range of 4 bits. Even though the output may be somewhat large in some cases, e.g., fluctuating to 8-9, it can still be measured and read out, since it is still within the output range of the Sub-ADC.

In an alternative example, a schematic diagram of a Sub-ADC 11 with K-1 bit accuracy is shown in fig. 3, which includes K resistors R ₁ 、R ₂ To R _K-2 ，R _K-1 And R _K K-1 comparators C ₁ 、C ₂ To C _K-2 And C _K-1 。

Referring to fig. 1, 2 and 3 in combination, in the Sub-ADC 11, a resistor R _k One end of the resistor is connected to a first reference voltage Vref1 and a resistor R ₁ One end of the resistor is connected to a second reference voltage Vref2, K resistors R ₁ To R _K Sequentially connected in series, wherein the first reference voltage Vref1 is greater than the second reference voltage Vref2. Thus, the K resistors divide a voltage difference formed by the first reference voltage Vref1 and the second reference voltage Vref2.

The K-1 comparators C ₁ To C _K-1 One input end of the voltage-regulating circuit is respectively coupled between two different resistors so as to be respectively connected with a comparative reference voltage with sequentially increased voltage values, and the other input end of the voltage-regulating circuit is connected with an input signal V _in Wherein the input signal V _in The analog holding signal output by the sample-hold amplifying circuit or the signal output by the conversion module of the previous stage can be used. Each comparator C ₁ To C _K-1 A comparison reference voltage and an input signal V respectively connected thereto _in The amplitudes are compared to obtain comparison results d 1-dk-1, and the comparison results d 1-dk-1 are output to the digital computation module 04 as thermometer codes.

Wherein, according to K-1 comparators C ₁ To C _K-1 Magnitude order of the comparative reference voltages switched in, comparators C ₁ To C _K-1 The output comparison results d 1-dk-1 are arranged from low to high, i.e. comparator C ₁ The output comparison result d1 is the least effective of the thermometer codeBit, comparator C _k-1 The output comparison result dk-1 is the most significant bit. And, due to each comparator C ₁ To C _K-1 The comparison reference voltages respectively connected are increased in turn, so that they are dependent on the input signal V _in The thermometer code changes from the least significant bit, and the input signal V is characterized only when the logic value of the lower significant bit of the thermometer code (e.g., the logic value is "1") is lower than the threshold value _in Is greater than the corresponding comparison reference voltage, the logic value of the first significant bit in the thermometer code may change, e.g., in response to the input signal V _in The amplitude of the thermometer code is increased, and the thermometer code can be changed from 00 \8230 \ 8230: '00 \8230'; '823011 ″, but not' 00 \8230; '823010;'.

For example, for an ADC with 10-bit accuracy, the measurement range is 0 to 1023. In the case of only grading, for example, the first Stage conversion module Stage1 uses a 3-bit Sub-ADC 11 to perform measurement, and includes 7 comparators, that is, the numbers 0 to 1023 can be equally divided into eight intervals, which can be numbered as 000, 001, 010, and up to 111, respectively. When the current signal sampling value is determined to fall into a certain interval, for example, a corresponding interval of 010 (corresponding to a 256-383 section of 0-1023), in order to facilitate Sub-ADC sampling in the subsequent conversion module, the OTA may be adopted to amplify the signal in the interval by 8 times, and a 3-bit Sub-ADC is still adopted to sample the amplified interval, assuming that the current signal sampling value falls into the second-stage coding interval of 001, and then the first-stage 4-bit Sub-ADC is used to determine a specific corresponding value, for example, the current signal sampling value is determined to be 273 in the interval of 0001.

For a pipelined analog-to-digital conversion circuit without a sample-and-hold module as illustrated in fig. 2, an aperture error may be generated due to a bandwidth mismatch of a sampling path between the Sub-ADC and the MDAC in a first stage conversion module due to a fluctuating conversion of an analog signal with time.

The aperture error may cause a shift in the position of the transition level of the transfer characteristic curve of the conversion module, and the corresponding output voltage range may be increased. In other words, it can be equivalent to that the reference threshold of the comparator in the Sub-ADC becomes larger or smaller. As shown in fig. 4, a solid line is a transmission characteristic curve of the Sub-ADC, and an input voltage value corresponding to the output voltage signal Vout when the transition occurs is a preset comparison threshold of the corresponding comparator in the transmission characteristic curve. Wherein, the Sub-ADC transmission characteristic curve can be determined based on theoretical design or determined according to recorded information of previous calibration.

From the perspective of signal transmission, when the value of the input voltage signal Vin is Va, the reference threshold V preset by the corresponding comparator is exceeded at this time ₃ As shown in fig. 4, if the output value Vout is still above the horizontal axis, it can be considered that the actual comparison threshold of the comparator is shifted to the right at this time and the measurement range is increased. At this time, the comparison threshold V of the comparator is set ₃ And (5) adjusting the measurement range to be consistent with the solid line.

Specifically, based on the transmission characteristics of the conversion module, a test analog signal is input to the first-stage conversion module, and then whether a preset reference threshold of a corresponding comparator in a sub analog-to-digital conversion unit of the first-stage conversion module has a deviation relative to a theoretical reference threshold is determined according to the skip output voltage output by the first-stage conversion module, and when the deviation exists, the preset comparison threshold of the comparator is adjusted. Therefore, the influence of aperture error is reduced, and the precision of the pipelined analog-to-digital conversion circuit is improved.

For better understanding of the inventive concepts, technical solutions, principles and advantages of the embodiments of the present invention, those skilled in the art will now make detailed descriptions of specific application scenarios with reference to the accompanying drawings.

First, the pipelined analog-to-digital conversion circuit applicable to the embodiment of the present invention may include a first-stage conversion module and a back-end conversion module having at least one stage of conversion module cascaded thereto, where the first-stage conversion module may include a sub-analog-to-digital conversion unit composed of at least one comparator.

As described above, due to the aperture error, the transmission characteristic curve of the pipeline analog-to-digital conversion circuit may be shifted, and the accuracy thereof may be affected. To this end, an embodiment of the present invention provides a calibration apparatus for a pipelined analog-to-digital conversion circuit, as shown in fig. 5, a calibration apparatus A0 may be coupled to the pipelined analog-to-digital conversion circuit ADC0 to be calibrated, where the pipelined analog-to-digital conversion circuit ADC0 includes a first-Stage conversion module Stage1 and a cascaded back-end conversion module Stage b having at least one Stage of conversion modules (e.g., including second-Stage to nth-Stage conversion modules Stage2 to Stage N, N ≧ 2), the first-Stage conversion module Stage1 includes a Sub analog-to-digital conversion unit Sub-ADC composed of at least one comparator (not shown), and a structure of a specific pipelined analog-to-digital conversion circuit applied in an embodiment of the present invention may refer to specific application examples such as fig. 2, fig. 8, and fig. 12, where only some modules and components related to aperture error calibration are shown.

With continued reference to fig. 5, the calibration device A0 may include: the device comprises a signal generation module A1, a deviation determination module A2 and a deviation adjustment module A3, wherein:

the signal generating module A1 is adapted to generate a test analog signal and input the test analog signal to the first Stage conversion module Stage1 in the pipelined analog-to-digital conversion circuit ADC 0;

the deviation determining module A2 is suitable for acquiring a jump output voltage which is output by the first-Stage conversion module Stage1 and corresponds to a jump signal at the output end of the comparator; judging whether a preset reference threshold of the comparator has deviation relative to a theoretical reference threshold or not according to the skip output voltage;

the deviation adjusting module A3 is adapted to adjust the preset comparison threshold of the comparator when the deviation determining module A2 determines that the preset reference threshold of the comparator has a deviation with respect to the theoretical reference threshold.

By adopting the calibrating device A0, the test analog signal is generated by the signal generating module A1 and then directly input into the first-Stage conversion module Stage1, then the deviation determining module A2 acquires the jump output voltage output by the first-Stage conversion module Stage1 and corresponding to the jump signal at the output end of the comparator, whether the deviation exists in the preset reference threshold value of the comparator is further judged according to the jump output voltage, and the preset comparison threshold value of the comparator is adjusted by the deviation adjusting module A3 when the deviation exists.

Some specific application examples of the respective modules are shown below for better understanding and implementation by those skilled in the art.

First, the signal generating module A1 may specifically be a signal generator. As described above, the test analog signal may be a linear analog signal varying in a single direction, a nonlinear analog signal varying in a single direction, a linear analog signal varying in multiple directions, a nonlinear analog signal varying in multiple directions, or the like.

In an alternative example, the signal generating module A1 may specifically generate the test analog signal through a Ramp Generator (Ramp Generator), as shown in fig. 6a, the constant current source S1 supplies a current I to the capacitor C1, so that the capacitor C1 integrates to generate a voltage vt, and provides voltages to the gate of the transistor M1, one input terminal of the driver AMP1, and one input terminal of the hysteresis comparator AMP 2; the source electrode of the transistor M1 is connected with another constant current source S2, and the constant current source S2 outputs current 2I; the gate of the transistor M1 is connected to the output terminal of the hysteresis comparator AMP 2; the other input end of the hysteresis comparator AMP2 is connected with a reference voltage VCM; the output end of the driver AMP1 outputs an analog signal VOUT; the output end of the driver APM1 is grounded through a capacitor C2, and noise reduction is achieved.

The transistor M1 is controlled to be turned off and on by the hysteresis comparator AMP2, so that the capacitor C1 is charged and discharged, thereby forming a linearly increasing and decreasing analog signal VOUT at the output terminal of the driver AMP 1. Referring to fig. 6b, which is a waveform diagram of the analog signal output by the ramp generator circuit shown in fig. 6a, wherein V0+ and V0-represent the peak values of the analog signal, the slope of the linear change of the analog signal VOUT is I/C.

According to the linear relation between the analog signal generated by the ramp generator and time, the output end of the ramp generator can be connected with the input end of the pipeline type analog-to-digital conversion circuit in a specified time period, so that the analog signal generated by the ramp generator in the time period is used as a test analog signal to be input into the pipeline type analog-to-digital conversion circuit. The specified time period may correspond to a time period in which the ramp generator generates an analog signal changing in a single direction (e.g., a part of the analog signal in the region (1) in fig. 6b, a part of the analog signal in the region (2), etc.), or may correspond to a time period in which the ramp generator generates an analog signal changing in multiple directions (e.g., a part of the analog signal in the region (1) and the region (2) in fig. 6b, etc.).

In some embodiments of the present invention, referring to fig. 7a, the deviation determining module A2 may include: a digital information acquisition unit a21 and a deviation calculation unit a22, wherein:

the digital information acquisition unit A21 is suitable for determining jump digital information corresponding to the first-Stage conversion module Stage1 according to the jump output voltage;

the deviation calculating unit a22 is adapted to determine whether a measurement output interval of the first-Stage conversion module Stage1 is consistent with a theoretical output interval according to the jump digital information acquired by the digital information acquiring unit a21, and determine that a preset reference threshold of the comparator has a deviation relative to the theoretical reference threshold when the measurement output interval is inconsistent with the theoretical output interval.

As a specific example, the digital information acquisition unit a21 may include: a digital calculation subunit (not shown) adapted to obtain digital residual error information corresponding to the skip output voltage and test digital information corresponding to the test analog signal output by the back-end conversion module StageB; and determining jump digital information corresponding to the Stage1 according to the digital residual error information and the test digital information.

In other embodiments of the present invention, as shown in fig. 7b, the deviation determining module A2 may include: and the comparison unit A23 is suitable for comparing the jump output voltage with a preset output voltage threshold value and outputting a corresponding feedback signal based on a comparison result, wherein when the jump output voltage and the preset output voltage threshold value are inconsistent, the preset reference threshold value of the comparator is determined to have deviation relative to a theoretical reference threshold value.

In a specific implementation, the comparing unit a23 is a circuit or a device that compares the skip output voltage (i.e. the analog voltage signal output by the first converting module Stage 1) with the preset output voltage threshold, and two inputs of the comparing unit are both analog signals, and a binary digital signal with 0 or 1 is output as the feedback signal. For example, if the output level is 1, it is determined that the preset reference threshold of the corresponding comparator in the sub analog-to-digital conversion unit of the first conversion module Stage1 is deviated from the theoretical reference threshold.

Referring to fig. 8, a calibration scenario for a pipeline analog-to-digital conversion circuit includes a seven-STAGE pipeline analog-to-digital conversion circuit 8A, and a dual-input differential structure is shown here, which includes a first-STAGE conversion module STAGE1 and a back-end conversion module Backend-ADC composed of second-to-fifth-STAGE conversion modules STAGE 2-5 and a last-STAGE conversion module FLASH ADC. The first-STAGE conversion module STAGE1 is a conversion module SHA-LESS having a structure without a sample-and-hold module, wherein the sub-analog-to-digital conversion unit may be, for example, a FLASH analog-to-digital converter FLASH ADC, the gain digital-to-analog conversion unit MDAC0 includes an operator ALU, a sub-analog-to-digital converter DAC, and an operational amplifier OTA, and the gain digital-to-analog conversion unit MDAC0 is not described in detail herein, which may be referred to in the foregoing embodiments.

The FLASH analog-to-digital converter FLASH ADC may include a reference voltage generating circuit (which may be divided by a string of resistors), a comparator array, and a coding circuit, where specific implementations of the reference voltage generating circuit and the comparator array may be as shown in fig. 3, and the coding circuit is not shown. Taking an N-bit FLASH analog-to-digital converter as an example, 2N-1 reference voltages are generated by resistor voltage division, and the full-scale range of the analog-to-digital converter FLASH ADC is equally divided into 2N-1 intervals. The input signal of the analog-to-digital converter FLASH ADC is compared with the reference voltages through a comparator, and the thermometer codes output after comparison are subjected to binary encoder to obtain the final N-bit binary digital output.

For the seven-stage pipelined analog-to-digital conversion circuit 8A, in some embodiments of the present invention, a calibration apparatus is adopted that includes: a signal generating device RAMP GENERATOR, a comparator CMP and an offset adjusting module (not shown) arranged inside said FLASH analog-to-digital converter FLASH ADC.

The signal generating device RAMP GENERATOR generates a test Analog Input to the first-STAGE conversion module STAGE1, and the test Analog Input is Input to the seven-STAGE pipelined Analog-to-digital conversion circuit 8A, processed by the first-STAGE conversion module STAGE1, and output to the back-end conversion module Backend-ADC coupled thereto.

As a specific example of the comparison unit a23, as shown In fig. 8, the comparator CMP may be a 4-input 1-output analog device for an analog-to-digital conversion circuit 8A with a dual-input differential structure, where two input signals In1 and In2 are from the first-STAGE analog-to-digital conversion module STAGE1, the other two input signals are reference signals Vref1 and Vref2, and an output of the comparator CMP can be used as a control signal of the deviation adjustment module. More specifically, the signal of the first input terminal In1 may be compared with the reference signal Vref1, and a feedback signal corresponding to the first input signal may be input from the output terminal out0 based on the comparison result; and comparing the signal of the second input end In2 with the reference signal Vref2, and inputting a feedback signal corresponding to the second input signal from the output end out0 based on the comparison result. It is understood that, in a specific implementation, the deviation determining module A2 may also include the comparing unit a23, the digital information acquiring unit a21 and the deviation calculating unit a22, and a user may select to use the comparing unit a23 or select to use the digital information acquiring unit a21 and the deviation calculating unit a22 according to a configuration as required.

In a specific implementation, the deviation adjusting module A3 is adapted to control to increase the preset comparison threshold of the comparator when it is determined that the preset reference threshold of the comparator is smaller than the corresponding theoretical reference threshold; and when the preset reference threshold value of the comparator is determined to be larger than the corresponding theoretical reference threshold value, controlling to reduce the preset comparison reference threshold value of the comparator.

In a specific implementation, the comparator in the sub-analog-to-digital conversion unit in each conversion module including the first conversion module stage may specifically adopt the following structure, such as a schematic structural diagram of a comparator shown in fig. 9, where the comparator CMP0 includes a Pre-amplification part Pre-amp0 and a Latch part Latch0, where:

the Pre-amplifying part Pre-amp0 has a first input end adapted to input a corresponding preset reference threshold, a second input end adapted to input the test analog signal, a first output end adapted to output an amplified signal corresponding to the preset reference threshold, and a second output end adapted to output an amplified signal corresponding to the test analog signal;

the Latch component Latch0 has a first input end coupled to the first output end of the pre-amplification component; a second input terminal of the pre-amplifying part is coupled to the second output terminal of the pre-amplifying part, and an output terminal of the pre-amplifying part is suitable for outputting a comparison result based on the magnitude relation between the first input terminal and the second input terminal.

Based on the structure of the comparator CMP0, a specific circuit structure of the adjustment module is shown below, and the offset adjustment module may specifically include: a specific circuit structure of a deviation adjusting module is shown below, referring to a deviation adjusting module A3 shown in fig. 9, wherein the charge storing unit group may be specifically implemented by a plurality of charge storing units such as capacitors in addition to the switch control unit A3 c. The switch unit group may be implemented by a plurality of switches, such as transistors or other types of devices capable of implementing a switching function.

As shown in fig. 9, the charge energy storage unit group specifically includes a plurality of first charge energy storage units C1N to CkN and a plurality of second charge energy storage units C1P to CkP, where: each of the first charge storage cells C1N to CkN is coupled between the first output terminal of the Pre-amplifying part Pre-amp0 and ground, and each of the second charge storage cells is coupled between the second output terminal of the Pre-amplifying part and ground.

As shown in fig. 9, the switch unit group specifically includes a plurality of first switches S1N to SkN and a plurality of second switches S1P to SkP, where: each of the first switches S1N to SkN is coupled between the corresponding first charge storage unit C1N to CkN and ground GND, and each of the second switches SW1P to SWkP is coupled between the corresponding second charge storage unit C1P to CkP and ground.

The switch control unit A3C is adapted to turn on the first switches S1N to SkN between the ground GND and part or all of the first charge energy storage units C1N to CkN to which the first output terminal of the Pre-amplification component Pre-amp0 is coupled when it is determined that the preset reference threshold of the comparator CMP0 is smaller than the theoretical reference threshold of the comparator CMP 0; and when the preset reference threshold value of the comparator CMP0 is determined to be larger than the theoretical reference threshold value of the corresponding comparator CMP0, turning on second switches S1P-SkP between part or all of the second charge energy storage units C1P-CkP coupled to the first output end of the Pre-amplification part Pre-amp0 and the ground.

It should be noted that, the first charge storage units and the second charge storage units shown in fig. 9 are the same in number, and the first switches and the second switches are also the same in number. It is to be understood that, in an implementation, the number of the first charge storage unit and the second charge storage unit may also be different, and the number of the first switch and the second switch may also be different.

As described above, the pipeline analog-to-digital conversion circuit shown in fig. 2 can be used as a pipeline analog-to-digital conversion circuit structure to which the calibration scheme according to the embodiment of the invention is applied. It should be understood that the pipelined analog-to-digital conversion circuit applicable to the embodiment of the present invention is not limited to the above structure, and may have some components, and may also include circuit modules or devices that are expanded or optimized according to actual needs, as long as the circuit modules or components that implement the sample-and-hold function are not included therein.

Referring to the flowchart of the calibration method shown in fig. 10, the following describes a method for calibrating the aperture error according to an embodiment of the present invention, and the specific steps are as follows:

and S11, inputting the test analog signal to the first-stage conversion module.

In a specific implementation, the method in the embodiment of the present invention may be used for calibration before the pipelined analog-to-digital conversion circuit is used for analog-to-digital conversion, or the calibration may be performed according to a preset period or frequency, or the calibration method in the embodiment of the present invention may be manually started as needed. After calibration is started, a test analog signal may be first input to the pipeline analog-to-digital conversion circuit, and more specifically, to the first stage conversion module.

The test analog signal can be an analog signal which changes in a single direction or an analog signal which changes in multiple directions; the test analog signal may be a linearly changing analog signal or a nonlinearly changing analog signal. For example, the test analog signal may be a linear analog signal varying in a single direction, a nonlinear analog signal varying in a single direction, a linear analog signal varying in multiple directions, a nonlinear analog signal varying in multiple directions, and the like, which is not particularly limited in this specification.

Wherein the test analog signal may be generated by a signal generator. In addition, the linear analog signal is convenient to generate and control, and is more beneficial to implementing the calibration method provided by the embodiment of the specification. As a preferable scheme of the invention, a linear analog signal with single direction change is adopted as the test analog signal for aperture error calibration.

And S12, acquiring a jump output voltage which is output by the first-stage conversion module and corresponds to the jump signal at the output end of the comparator.

In a specific implementation, the sub analog-to-digital conversion unit of each conversion module including the first conversion module may include at least one comparator, and referring to fig. 3 and 5, when an input voltage signal Vin reaches a comparison threshold of the corresponding comparator, an output end signal of the comparator jumps, and accordingly, an output voltage Vout of the conversion module also jumps, for convenience of description, an output voltage output by the conversion module and corresponding to the output end jump signal of the corresponding comparator is referred to as a jump output voltage, and as shown in fig. 4, the jump output voltage corresponding to a transmission characteristic curve described by a solid line is ± 0.5Vref.

In specific implementation, a change curve of the first conversion module along with the test analog signal can be monitored in real time through a sensor, and when the signal at the output end of the first-stage conversion module is detected to jump, the jump output voltage at the jump moment of the voltage at the output end is detected to be used as the jump output voltage which is output by the first-stage conversion module and corresponds to the jump signal of the comparator.

In the specific calibration process, for convenience of implementation and improvement of calibration efficiency, in step S11, according to the process that the input voltage Vin gradually changes from-Vref to + Vref, the skip output voltage corresponding to the skip signal at the output end of each comparator in the sub analog-to-digital conversion unit of the first-stage conversion module may be obtained one by one, and subsequent steps are adopted to calibrate one by one.

As a preferred example, when the input voltage Vin is close to the threshold point voltage of each comparator (specifically, may be slightly lower or/and slightly higher than the corresponding threshold point voltage of each comparator, for example, may be a measurement interval centered on the threshold point voltage), the corresponding trip output voltage may be obtained to determine whether the current threshold point voltage needs to be adjusted.

And S13, judging whether the preset reference threshold of the comparator has deviation relative to a theoretical reference threshold or not according to the jump output voltage.

S14, when the preset reference threshold of the comparator is determined to have deviation relative to the theoretical reference threshold, the preset comparison threshold of the comparator is adjusted.

As mentioned above, due to the aperture error, the jump output voltage outputted by the first stage conversion module may deviate from the theoretical jump output voltage, for example, the transmission characteristic curve shown by the dashed line segment in fig. 4, which may actually be larger than the theoretical reference threshold. According to the transmission characteristic curves of the conversion modules, in an ideal state, the input and the output of each conversion module in the pipelined analog-to-digital conversion circuit are in a linear relationship, and the slope is theoretical gain, so that when the jump output voltage output by the first-stage conversion module is inconsistent with the preset reference threshold corresponding to the corresponding comparator, the deviation of the preset comparison threshold of the comparator relative to the theoretical comparison threshold can be equivalently achieved, and therefore the preset comparison threshold of the comparator can be adjusted accordingly, the position of the jump level of the conversion module caused by the aperture error is reduced from being translated, and the precision of the pipelined analog-to-digital conversion circuit can be improved.

Specifically, referring to the transmission characteristic curve shown in fig. 4, if the theoretical reference threshold corresponding to each stage of the comparator in the corresponding first-stage conversion module is ± 0.5Vref, the theoretical reference threshold may actually be the actually obtained skip output voltage, such as Vr.

Specifically, the method comprises the following steps: for example, when the voltage value of the input test analog signal is Va, the output voltage of the first conversion module jumps, and the corresponding output voltage value is Vr, which indicates that the current actual comparison threshold Va of the corresponding comparator is greater than the current preset comparison threshold V ₃ 。

As can be known from the transmission characteristic curve of the conversion module shown in fig. 4, for the first-stage conversion module, under the condition that the slope of the transmission characteristic curve is not changed, it may be equivalent that the preset comparison threshold of the comparator corresponding to the skip output voltage of the first-stage conversion module is deviated from the theoretical comparison threshold, if the skip output voltage of the first-stage conversion module is not equal to ± 0.5Vref, for example, if the skip output voltage obtained by the first-stage conversion module is Vr, the preset reference threshold of the comparator corresponding to the skip output voltage may be equivalent to Va, as can be seen from fig. 4, the theoretical reference threshold of the comparator corresponding to the preset reference threshold Va is V3, and there is a deviation between the two. Therefore, by adjusting the comparison threshold corresponding to each comparator, the output of the first-stage conversion module can better conform to an ideal or theoretical transmission characteristic curve, and the offset generated due to aperture error is reduced or even eliminated, so that the conversion accuracy of the pipelined analog-to-digital conversion circuit can be improved.

Some alternative exemplary ways of implementing the steps are given below for a better understanding and implementation of the steps by a person skilled in the art. It is to be understood that in particular implementations, the steps are not limited to the specific examples below.

After the skip output voltage is acquired through step S12, it may be determined through step S13 whether a preset reference threshold of the comparator is deviated from a theoretical reference threshold. In a specific implementation of step S13, there may be multiple determination manners, and two exemplary manners are given below. One may be referred to as a digital signal-based determination scheme for short, and the other may be referred to as an analog signal-based determination scheme for short.

For the digital signal-based determination method, that is, determining skip digital information corresponding to the first-stage conversion module based on the obtained skip output voltage, and then determining, as shown in a flowchart of fig. 11, that whether a preset reference threshold of a comparator has a deviation may specifically include the following steps:

s131, determining jump digital information corresponding to the first-stage conversion module according to the jump output voltage.

In a specific implementation, referring to fig. 2, the test analog signal is input to the pipeline analog-to-digital conversion circuit P1, and a sub analog-to-digital conversion unit and a gain digital-to-analog conversion unit of the first-stage conversion module perform operations to obtain a corresponding analog residual signal and transmit the analog residual signal to a rear-end conversion module including at least one stage of conversion module step by step, and then an output code corresponding to the test analog signal can be obtained according to a thermometer code output by each stage of conversion module to the sub analog-to-digital conversion unit, and can be used as test digital information corresponding to the test analog signal. On the other hand, the jump output voltage output by the first-stage conversion module corresponds to the digital signal of a rear-end conversion module except the first-stage conversion module, so that the digital signal of the rear-end conversion module can be used as digital residual error information corresponding to the jump data voltage, and the jump digital information corresponding to the first-stage conversion module can be further determined according to the digital residual error information and the test digital information.

Referring to fig. 2, in step S13, on one hand, digital signals output by the rear-end conversion modules including the conversion modules Stage2 to Stage n, that is, digital residual error information corresponding to the skip output voltage, may be acquired, and on the other hand, digital signals output by the conversion modules Stage1 to Stage n, that is, test digital information corresponding to the skip output voltage, may be acquired, so that skip digital information corresponding to the first-Stage conversion module may be determined according to the digital residual error information and the test digital information.

S132, determining whether the measurement output interval of the first-stage conversion module is consistent with the theoretical output interval according to the jump digital information, and executing the step S133 when the measurement output interval of the first-stage conversion module is inconsistent with the theoretical output interval.

Referring to fig. 4, for example, the skip digit information may be compared with the theoretical output interval of the first-stage conversion module to determine whether the skip digit information and the theoretical output interval of the first-stage conversion module are consistent, in a specific implementation, the skip digit information may be directly compared with the threshold of the theoretical output interval of the first-stage conversion module to determine whether the skip digit information and the theoretical output interval of the first-stage conversion module are consistent, and if the skip digit information and the theoretical output interval of the first-stage conversion module are not consistent, step S133 may be executed.

S133, determining that the preset reference threshold of the comparator has deviation relative to the theoretical reference threshold.

The following is a detailed description of an example in a particular application scenario.

Referring to the structural schematic diagram of the seven-Stage pipeline analog-to-digital conversion circuit shown in fig. 12, the precision of the pipeline analog-to-digital conversion circuit P3 is 12bits, and the pipeline analog-to-digital conversion circuit includes seven stages of conversion modules, that is, a first Stage conversion module Stage11 and a back-end conversion module 102 composed of second to seventh Stage conversion modules Stage2 to Stage 7. More specifically, the first Stage conversion module Stage11 and the second Stage conversion module Stage12 respectively output a first Stage thermometer code DS11 and a second Stage DS12 of 3 bits; the third-Stage conversion module Stage13 to the sixth-Stage conversion module Stage16 respectively output third-Stage thermometer codes DS13 to DS16 of 2 bits; the seventh Stage conversion module Stage17 outputs a seventh Stage thermometer code DS17 of 4 bits.

Comparative Table 1

When the numerical value calculation module 103 carries out dislocation on thermometer codes DS 11-DS 12 from the first-Stage conversion module Stage12 to the seventh-Stage conversion module Stage17, partial bit coincidence exists between thermometer codes at all stages, and thus an output code of 12bits is obtained. Specifically, the following comparative table 1 can be referred to. Wherein d 12-d 10 represent the most significant bit to the least significant bit of the first-stage thermometer code DS11, and so on, and d 20-d 73 represent the bits specifically contained in the second-stage thermometer code DS12 to the seventh-stage thermometer code DS17, respectively. In addition, the comparison table 1 also shows that the digital domain weights corresponding to the first-Stage conversion module Stage12 to the seventh-Stage conversion module Stage17 are 512, 128, 64, 32, 16, 8 and 1 respectively.

According to the comparison table 1, the least significant bit of the previous thermometer code and the most significant bit of the next thermometer code coincide, and the numerical calculation module 103 performs the staggered addition according to the coincidence relation shown in the comparison table 1, so as to obtain the 12-bits output code DSC.

And according to the current digital domain weights of the first-Stage conversion module Stage12 to the seventh-Stage conversion module Stage17, digital output information DOUT corresponding to the 12bits output code can be obtained through calculation by the following formula:

DOUT＝(d12*4+d11*2+d10*1)*512+

(d22*4+d21*2+d20*1)*128+

(d31*2+d30*1)*64+

(d41*2+d40*1)*32+

(d51*2+d50*1)*16+

(d61*2+d60*1)*8+

(d73*8+d72*4+d71*2+d70*1)*1。

and the digital output information DOUT corresponding to the test analog signal is the test digital information.

Acquiring thermometer codes (namely, second-stage thermometer codes DS12 to seventh-stage thermometer codes DS 17) respectively output by each stage of conversion module in the rear-end conversion module 102 and corresponding digital domain weights (namely, 128 to 1), and acquiring digital residual error information reset 1:

Residue1＝(d22*4+d21*2+d20*1)*128+

(d31*2+d30*1)*64+

(d41*2+d40*1)*32+

(d51*2+d50*1)*16+

(d61*2+d60*1)*8+

(d73*8+d72*4+d71*2+d70*1)*1。

through the formula, digital residual error information corresponding to the jump output voltage of the first-Stage conversion module Stage11 when the test analog signal is input can be obtained.

According to the relation, the digital residual error information corresponding to the jump output voltage is subtracted from the test digital information corresponding to the test analog signal, so that the difference between the test digital information and the jump output voltage is obtained, and the jump digital information corresponding to the first-stage conversion module can be obtained.

For the scheme based on the analog signal determination mode, referring to a calibration scenario diagram for the pipelined analog-to-digital conversion circuit shown in fig. 8, that is, the skip output voltage output by the first-stage conversion module may be directly measured by a comparator CMP and compared with a preset output voltage threshold, and when the skip output voltage and the preset output voltage threshold are not consistent, it may be determined that the preset reference threshold of the comparator has a deviation with respect to the theoretical reference threshold.

The specific working principle of the comparator CMP is explained in connection with the transmission characteristic curve shown in fig. 4: assuming that Vref1= +0.5Vref and vref2= -0.5Vref, if the first conversion module STAGE1 is monitored to obtain that the output voltage jumps when the Input test Analog Input is Va, where Vr > +0.5Vref is detected by the first Input terminal In1 of the comparator CMP, when the voltage of the test Analog Input is Va, the voltage is not within the range of the corresponding comparator, which means that the output voltage range of the first STAGE conversion module STAGE1 is enlarged, and it can be determined that the preset reference threshold of the corresponding comparator is deviated from the theoretical reference threshold. Similarly, the jump output voltage detected at the second input terminal In2 of the comparator CMP may be compared with the reference signal Vref2, i.e., -0.5Vref, and it is determined whether the preset reference threshold of the corresponding comparator is deviated from the theoretical reference threshold based on the comparison result.

It should be understood that the present invention is not limited to the above-described determination method, and in a specific implementation, the present invention may be further optimized or extended as needed, or other types of determination methods may be adopted, as long as it can be determined whether the prediction reference threshold of the comparator has a deviation from the theoretical threshold, and the embodiment of the present invention does not limit the specific determination method.

In a specific implementation, for step S14, a corresponding adjustment strategy may be adopted to perform adjustment according to a size relationship between a preset reference threshold of the comparator and a corresponding theoretical reference threshold. Specifically, when it is determined that the preset reference threshold of the comparator is smaller than the corresponding theoretical reference threshold, the preset comparison threshold of the comparator may be controlled to be increased; and when the preset reference threshold value of the comparator is determined to be greater than the corresponding theoretical reference threshold value, the preset comparison threshold value of the comparator can be controlled to be reduced.

In a specific application example, referring to fig. 4 in combination with fig. 8, it is assumed that the FLASH analog-to-digital converter FLASH ADC in the first-STAGE conversion module STAGE1 in fig. 8 includes a comparator array composed of 8 comparators, and it is assumed that the comparator thresholds corresponding to the first 6 comparators are all adjusted. For the sake of convenience of description, the seventh comparator is referred to as comparator a. If the preset reference threshold of comparator A is Vr, because Vr > +0.5Vref, the corresponding comparator threshold can be reduced by a predetermined step size, for example, the preset comparator threshold is gradually adjusted from Va to the left until V is adjusted to ₃ . More specifically, with reference to the specific structural diagram of the deviation adjustment module shown In fig. 9, for example, the structure of the comparator a is the structure of CMP0 shown In fig. 9, when the comparator CMP detects that the signal of the first input terminal In1 is greater than the reference signal Vref1 (e.g., +0.5 Vref), the deviation adjustment module A3 shown In fig. 9 may be adopted to perform step-by-step adjustment, for example, the switch control unit A3C outputs a switch control signal to first trigger the first switch S1N to be closed, so as to turn on the path between the first charge storage unit C1N and the ground. If the comparator CMP detects that the signal of the first input terminal In1 is still greater than the reference signal Vref1, the switch control unit A3C triggers the first switch S2N to close again based on the feedback signal output by the CMP1, and a path between the first charge energy storage unit C2N and the ground is turned on. Such asAnd repeating the above steps until the comparator CMP detects that the signal of the first input terminal In1 does not deviate from the reference signal Vref1, and determining that the comparison threshold of the comparator a is completely adjusted. Then, whether the preset reference threshold of the next comparator is deviated from the theoretical reference threshold or not can be detected in the same way, and the deviation adjustment mode is adopted for adjustment.

Similarly, referring to fig. 8 and 9, the comparison threshold of the corresponding comparator may be calibrated based on the other output signal output by the first stage conversion module to reduce or eliminate the aperture error of the pipelined analog-to-digital conversion circuit, thereby improving the accuracy of the pipelined analog-to-digital conversion circuit.

The calibration apparatus and the calibration method suitable for calibrating a pipelined analog-to-digital conversion circuit are described above by specific examples, and it should be noted that the working principle, the working mechanism, the application examples and the advantages related to the calibration apparatus and the calibration method in the foregoing embodiments may be understood by referring to each other.

In particular implementations, analog-to-digital conversion circuits are widely used and are described below as an example of a particular application in radar.

Referring to the schematic structural diagram of the radar shown in fig. 13, in the embodiment of the present invention, as shown in fig. 13, a radar RD0 includes a detection device DT0, an analog-to-digital conversion circuit ADC0, and a calibration device CB0; wherein:

the detection device DT0 is suitable for collecting echo signals and outputting analog signals to be processed to the analog-to-digital conversion circuit ADC0 x;

the analog-to-digital conversion circuit ADC0x is adapted to perform analog-to-digital conversion on the analog signal to be processed of the detection device DT0 or the test analog signal of the calibration device CB0; the device comprises a pipelined analog-to-digital conversion circuit PL-ADC0, wherein the pipelined analog-to-digital conversion circuit PL-ADC0 comprises a first-Stage conversion module Stage01, a rear-end conversion module stageB which is cascaded with the first-Stage conversion module and is provided with at least one Stage of conversion module, and a digital calculation module CA0;

the calibration device CB0 is adapted to calibrate an aperture error of the pipelined analog-to-digital conversion circuit PL-ADC0 by inputting a test analog signal to the pipelined analog-to-digital conversion circuit PL-ADC 0.

The analog-to-digital conversion circuit ADC0, more specifically, the specific implementation of the pipelined analog-to-digital conversion circuit PL-ADC0 may refer to the descriptions in the foregoing embodiments, and the specific implementation of the calibration apparatus CB0 may also refer to the detailed descriptions in the foregoing embodiments, which are not described herein again.

In a specific implementation, the radar RD may further include a control device CT0, adapted to control the calibration device CB0 to calibrate the pipelined analog-to-digital conversion circuit PL-ADC0 after the radar RD0 is powered on, and control the calibration device CB0 to end calibration after a calibration end condition is met, and enable the analog-to-digital conversion circuit ADC0x to perform analog-to-digital conversion on the analog signal to be processed.

In a specific implementation, the radar may be a laser radar, a millimeter wave radar, or the like, and the specific type is not limited in the embodiments of the present specification.

It should be noted that reference throughout this specification to "an example," "an embodiment," or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present specification. Also, in the description of the present specification, the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the specification described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.

Although the embodiments of the present specification are disclosed above, the embodiments of the present specification are not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the embodiments herein disclosed, and it is intended that the scope of the embodiments herein disclosed be limited only by the scope of the appended claims.

Claims (14)

1. A calibration method for a pipeline type analog-to-digital conversion circuit is disclosed, wherein the pipeline type analog-to-digital conversion circuit comprises a first stage conversion module and a rear end conversion module which is cascaded with the first stage conversion module and is provided with at least one stage conversion module, and the first stage conversion module comprises a sub analog-to-digital conversion unit which is composed of at least one comparator; characterized in that the calibration method comprises:

inputting a test analog signal to the first-stage conversion module;

acquiring a jump output voltage which is output by the first-stage conversion module and corresponds to a jump signal at the output end of the comparator;

judging whether a preset reference threshold of the comparator has deviation relative to a theoretical reference threshold or not according to the skip output voltage;

and when the preset reference threshold value of the comparator is determined to have deviation relative to the theoretical reference threshold value, adjusting the preset comparison threshold value of the comparator.

2. The calibration method according to claim 1, wherein said determining whether the preset reference threshold of the comparator is deviated from a theoretical reference threshold according to the skip output voltage further comprises:

determining jump digital information corresponding to the first-stage conversion module according to the jump output voltage;

and determining whether the measurement output interval of the first-stage conversion module is consistent with a theoretical output interval or not according to the jump digital information, and determining that the preset reference threshold of the comparator has deviation relative to the theoretical reference threshold when the measurement output interval of the first-stage conversion module is inconsistent with the theoretical output interval.

3. The calibration method of claim 2, wherein determining skip number information corresponding to the first stage conversion module according to the skip output voltage further comprises:

acquiring digital residual error information corresponding to the jump output voltage and test digital information corresponding to the test analog signal and output by the rear-end conversion module;

and determining jump digital information corresponding to the first-stage conversion module according to the digital residual error information and the test digital information.

4. The calibration method according to claim 1, wherein said determining whether there is a deviation of the preset threshold of the comparator according to the skip output voltage further comprises:

and comparing the jump output voltage with a preset output voltage threshold, and determining that the preset reference threshold of the comparator has deviation relative to a theoretical reference threshold when the jump output voltage and the preset output voltage are inconsistent.

5. The calibration method according to any one of claims 1 to 4, wherein the adjusting the preset comparison threshold value of the comparator when it is determined that the preset reference threshold value of the comparator deviates from the theoretical reference threshold value comprises:

when the preset reference threshold value of the comparator is determined to be smaller than the corresponding theoretical reference threshold value, the preset comparison threshold value of the comparator is controlled to be increased;

and when the preset reference threshold value of the comparator is determined to be larger than the corresponding theoretical reference threshold value, controlling to reduce the preset comparison threshold value of the comparator.

6. A calibration device for a pipelined analog-to-digital conversion circuit is disclosed, wherein the pipelined analog-to-digital conversion circuit comprises a first-stage conversion module and a cascaded back-end conversion module with at least one stage of conversion module, wherein the first-stage conversion module comprises a sub-analog-to-digital conversion unit consisting of at least one comparator; characterized in that the calibration device comprises:

the signal generating module is suitable for generating a test analog signal and inputting the test analog signal to the first-stage conversion module in the pipelined analog-to-digital conversion circuit;

the deviation determining module is suitable for acquiring a jump output voltage which is output by the first-stage conversion module and corresponds to a jump signal at the output end of the comparator; judging whether a preset reference threshold of the comparator has deviation relative to a theoretical reference threshold or not according to the skip output voltage;

and the deviation adjusting module is suitable for adjusting the preset comparison threshold value of the comparator when the deviation determining module determines that the preset reference threshold value of the comparator has deviation relative to the theoretical reference threshold value.

7. The calibration device of claim 6, wherein the deviation determination module comprises:

the digital information acquisition unit is suitable for determining jump digital information corresponding to the first-stage conversion module according to the jump output voltage;

and the deviation calculation unit is suitable for determining whether the measurement output interval of the first-stage conversion module is consistent with the theoretical output interval according to the jump digital information acquired by the digital information acquisition unit, and determining that the preset reference threshold of the comparator has deviation relative to the theoretical reference threshold when the measurement output interval of the first-stage conversion module is inconsistent with the theoretical output interval.

8. The calibration device according to claim 7, wherein the digital information acquisition unit comprises:

the digital calculation subunit is suitable for acquiring digital residual error information corresponding to the jump output voltage and test digital information which is output by the rear-end conversion module and corresponds to the test analog signal; and determining jump digital information corresponding to the first-stage conversion module according to the digital residual error information and the test digital information.

9. The calibration device of claim 6, wherein the deviation determination module comprises: and the comparison unit is suitable for comparing the jump output voltage with a preset output voltage threshold value and outputting a corresponding feedback signal based on a comparison result, wherein when the jump output voltage and the preset output voltage threshold value are inconsistent, the preset reference threshold value of the comparator is determined to have deviation relative to a theoretical reference threshold value.

10. The calibration device according to any one of claims 6 to 9, wherein the deviation adjustment module is adapted to control the increase of the preset comparison threshold of the comparator when it is determined that the preset reference threshold of the comparator is smaller than the corresponding theoretical reference threshold; and when the preset reference threshold value of the comparator is determined to be larger than the corresponding theoretical reference threshold value, controlling to reduce the preset comparison reference threshold value of the comparator.

11. The calibration device of claim 10, wherein the comparator comprises:

the pre-amplification part is suitable for inputting a corresponding preset reference threshold value at a first input end, inputting the test analog signal at a second input end, outputting an amplified signal corresponding to the preset reference threshold value at a first output end and outputting an amplified signal corresponding to the test analog signal at a second output end;

a latch component having a first input coupled to the first output of the pre-amplification component; a second input thereof is coupled to the second output of the pre-amplifying means, and an output thereof is adapted to output a comparison result based on a magnitude relation of the first input and the second input.

12. The calibration device of claim 11, wherein the offset adjustment module comprises:

a charge storage unit group comprising a plurality of first charge storage units and a plurality of second charge storage units, wherein: each first charge energy storage unit is coupled between the first output end of the pre-amplification part and the ground, and each second charge energy storage unit is coupled between the second output end of the pre-amplification part and the ground;

a switch unit group including a plurality of first switches and a plurality of second switches, wherein: each first switch is coupled between the corresponding first charge energy storage unit and the ground, and each second switch is coupled between the corresponding second charge energy storage unit and the ground;

the switch control unit is suitable for turning on a first switch between a part of or all first charge energy storage units coupled with the first output end of the pre-amplification part and the ground when the preset reference threshold value of the comparator is determined to be smaller than the theoretical reference threshold value of the comparator; and when the preset reference threshold value of the comparator is determined to be smaller than the theoretical reference threshold value of the corresponding comparator, turning on a second switch between part or all of the second charge energy storage units coupled to the first output end of the pre-amplification part and the ground.

13. A radar, comprising: a detection device, an analog-to-digital conversion circuit and a calibration device according to any one of claims 6 to 12; wherein:

the detection device is suitable for collecting echo signals and outputting analog signals to be processed to the analog-to-digital conversion circuit;

the analog-to-digital conversion circuit is suitable for performing analog-to-digital conversion on the analog signal to be processed of the detection device or the test analog signal of the calibration device; the device comprises a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit comprises a first-stage conversion module, a rear-end conversion module and a digital calculation module, wherein the rear-end conversion module is cascaded with the first-stage conversion module and is provided with at least one stage of conversion module;

the calibration device is suitable for calibrating the aperture error of the pipelined analog-to-digital conversion circuit by inputting a test analog signal to the pipelined analog-to-digital conversion circuit.

14. The radar of claim 13, further comprising:

and the control device is suitable for controlling the calibration device to calibrate the pipelined analog-to-digital conversion circuit after the radar is powered on, controlling the calibration device to finish calibration after the calibration finishing condition is met, and enabling the analog-to-digital conversion circuit to perform analog-to-digital conversion processing on the analog signal to be processed.

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