CN115421864B - Universal PowerPC architecture processor instruction set virtualization simulation method - Google Patents
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Abstract
The invention relates to a general PowerPC architecture processor instruction set virtualization simulation method, and belongs to the field of virtual simulation. The invention designs a general processor simulation framework aiming at 32-bit microprocessor cores e300, e500 and e600 based on Power Architecture of Feishaper (Freescale), and simultaneously supports the simulation operation of processors with various architectures. The method and the device provide an operating environment of the embedded processor software of the PowerPC processor and support for development of the embedded processor software of the PowerPC processor. The scheme provided by the invention can realize the instruction set simulation of the PowerPC instruction architecture processor, and has high simulation precision; the invention adopts the array, the linked list and the like to realize the simulation of the register and the memory, and can complete the simulation of the PowerPC instruction architecture processor.
Description
Technical Field
The invention belongs to the field of virtual simulation, and particularly relates to a general PowerPC architecture processor instruction set virtualization simulation method.
Background
Instruction set emulation is the most important support technology for processor virtualization technology, and allows software on a particular instruction set to run on another heterogeneous instruction set. Virtualization is implemented at the instruction set level, which is the fact that binary code on one hardware platform is converted into binary code on another hardware platform, so that compatibility between different instruction sets is achieved, and this technique is also called binary translation. Virtualization technology is implemented in 2 main ways: interpretation execution, dynamic binary translation.
The interpreter analyzes the source binary codes one by one, and decomposes corresponding interpretation routine execution according to the decoding result, namely the instruction type. The interpretation routine simulates the execution of a source instruction with an equivalent one or more target instructions on a source architecture maintained by software (including various architectural registers, memory states, etc.), resulting in the same execution result as the source instruction. The interpreter work process mainly includes the steps of fetching instructions, analyzing the operations needed by instructions, modifying the processor state, and so on.
The simulator based on interpretation and execution maintains an accurate processor data structure in the host, has high simulation precision, can realize accurate registers, memories and pipelines, and can obtain accurate performance indexes such as clock cycles of each instruction in the pipeline, stack simulation and the like besides the function of simulating a source program.
PowerPC (English: performance Optimization With Enhanced RISC-Performance Computing, sometimes abbreviated as PPC) is a Central Processing Unit (CPU) of Reduced Instruction Set (RISC) architecture, whose basic design is derived from IBM's POWER (Performance Optimized With Enhanced RISC; international Business machines corporation in Emotion) architecture, translated as "enhanced RISC performance optimization" at 8 in 2007.
The PowerPC processor has a very strong embedded performance because it has excellent performance, low energy consumption, and low heat dissipation. In addition to integrated I/O like serial and Ethernet controllers, the embedded processor is very significantly different from the desktop CPU. The PowerPC processor has 32 (32-bit or 64-bit) GPRs (general purpose registers), various other registers such as PC (program counter, also known as IAR/instruction address register or NIP/next instruction pointer), LR (link register), CR (condition register), and the like.
Disclosure of Invention
First, the technical problem to be solved
The invention provides a general PowerPC architecture processor instruction set virtualization simulation method, which aims to solve the problem of PowerPC architecture processor instruction set virtualization simulation.
(II) technical scheme
In order to solve the above technical problems, the present invention provides a general PowerPC architecture processor instruction set virtualization emulation method, which includes the following steps:
s1, powerPC instruction architecture target file analysis
Opening an executable file compiled by a PowerPC instruction architecture, and acquiring a code segment corresponding to a Program Header;
s2, powerPC instruction architecture memory emulation and code loading
Simulating the memory of the processor of the PowerPC instruction architecture by adopting a linked list structure, marking the memory as PowerPC-VMemory, loading a code segment corresponding to a Program Header, and simulating the memory read-write operation of the PowerPC instruction architecture;
s3, powerPC instruction architecture register emulation
The register is simulated through an array simulation register and through read-write operation of an array operation simulation register;
s4, powerPC instruction architecture instruction description
Each instruction has a unique representation, and each instruction is divided into different segments; the method comprises the steps of describing an Instruction in a segmentation mode, obtaining operation code information of Instruction construction, constructing an Instruction operation code information array PowerPC-InstructionDesp [425], describing 425 instructions of a POWERPC architecture Instruction set architecture, and storing the 425 instructions into the Instruction operation code information array PowerPC-InstructionDesp [425 ];
s5, powerPC instruction architecture read instruction
Reading an Instruction from the simulated memory PowerPC-VMemail according to the value of the program counter PC, and obtaining an Instruction PC-Instruction corresponding to the current PC;
s6, powerPC instruction architecture instruction decoding
According to the Instruction description of the PowerPC Instruction architecture, calculating whether corresponding bit positions of the PC-Instruction and the PowerPC-Instruction Desp [425] are the same one by one, if the corresponding positions of the kth Instruction description in the PC-Instruction and the PowerPC-Instruction Desp [425] are the same, finishing Instruction decoding, and marking as instruction_k;
s7, powerPC instruction architecture instruction translation
Performing functional translation on a PowerPC instruction architecture instruction set, designing a function which is operated in a virtual simulation processor and simulates the operation of each instruction, and ensuring that after each instruction and the function are processed, the memories and registers of a hardware processor and the virtual simulation processor are kept consistent; storing the function pointer into a PowerPC-InstructionInterp 425 array, wherein the storage sequence is consistent with the instruction sequence of PowerPC-InstructionDesp 425;
s8, powerPC instruction architecture Linux system call realization
Analyzing the system call, carrying out corresponding processing on the system call according to the type of the system call, and carrying out setting operation on a corresponding register;
s9, powerPC instruction architecture instruction execution
According to the number of instructions, performing cyclic instruction fetching, decoding and instruction translation, and executing instruction operation according to the function pointer; and continuously simulating until all instruction execution is completed, and processing system call to realize processor instruction set simulation aiming at the PowerPC instruction architecture.
Further, the step S1 specifically includes:
s11, opening an executable file compiled by a PowerPC instruction architecture;
s12, reading File Header, section Header and Program Header information in File information according to the format of the executable File compiled by the PowerPC instruction architecture, and obtaining a code segment corresponding to the Program Header.
Further, the step S2 specifically includes:
s21, simulating a PowerPC instruction architecture processor memory by adopting a linked list structure, wherein the size of a linked list structure PowerPC-memory Page is 256 words;
s22, marking the PowerPC instruction architecture memory as PowerPC-VMemory; writing the code segment corresponding to the Program Header acquired in the S1 into a PowerPC instruction architecture chip simulation memory PowerPC-VMemail, and maintaining the whole simulation memory structure according to the size of the code segment.
Further, the linked list structure body includes: the start virtual address memmorypagebeginaldddress, the end virtual address memmorypageendddress, the memory block memmorypage, the NEXT memory node pointer NEXT, and the previous memory node pointer PRE.
Further, in the step S22, if the code segment is not greater than the size 256 of one memory page, creating one memory page, and writing the code segment into the memory page array for use; if the code segment is larger than 256, creating a plurality of memory pages, writing the code segments into the corresponding memory page array in sequence, maintaining MemoryPageBeginAddress, memoryPageEndAddress information of each node, and ensuring the correctness of the linked list structure information.
Further, the step S3 specifically includes:
s31, simulating 197 registers in total of PowerPC instruction architecture e300, e500 and e600 chips, and realizing the simulation of the registers through an array PowerPC-Register simulation Register;
s32, by accessing the PowerPC-Register, performing operation simulation on the elements in the corresponding array to simulate the Register operation of the PowerPC instruction architecture, and realizing the Register simulation on the PowerPC instruction architecture.
Further, the step S4 specifically includes: the structure of the instruction operation code information array PowerPC-InstructInDesp comprises: name, contentNumber and content, where name is the instruction name, content number instruction fragment number, content is used to store opcode instruction decoding information.
Further, the step S5 specifically includes:
s51, reading an instruction from the PowerPC-VMemory maintained in the S2 according to the value of the program counter PC;
s52, according to the MemoryPageBeginAddress, memoryPageEndAddress value in the PowerPC-MemoryPage, the PC belongs to the PowerPC-MemoryPage, the PowerPC-MemoryPage-i is marked as PowerPC-MemoryPage-i, the address offset is PC-MemoryPageBeginadddress, the Instruction content is MemoryPage [ PC-MemoryPageBeginadddress ] corresponding to the PowerPC-MemoryPage-i, and the PC-Instruction is marked as PC-Instruction.
Further, the step S7 specifically includes:
s71, performing functional translation on instructions in a PowerPC instruction architecture instruction set, designing a function which is operated in a virtual simulation processor and simulates the operation of each instruction, and ensuring that after each instruction and the function are processed, the hardware processor is consistent with the memory and the register of the virtual simulation processor;
s72: translating 425 instructions of the PowerPC instruction architecture, and storing function pointers into an instruction translation decoding array PowerPC-InstructionInterp [425] array, wherein the storage sequence is consistent with the instruction sequence of PowerPC-InstructionDesp [425 ];
s73, acquiring a pointer in a function corresponding to the Instruction according to the instruction_k calculated in the S6.
Further, the step S9 specifically includes:
s91, constructing a simulation framework of a PowerPC instruction framework, performing cyclic instruction fetching, decoding and instruction translation according to the number of instructions, and executing instruction operation according to a function pointer;
s92, continuous simulation is carried out until all instructions are executed, system call is processed, and processor instruction set simulation aiming at the PowerPC instruction architecture is achieved.
(III) beneficial effects
The invention provides a general PowerPC architecture processor instruction set virtualization simulation method, which provides a virtualized operating environment for embedded processing software. The method and the device provide an operating environment of the embedded processor software of the PowerPC processor and support for development of the embedded processor software of the PowerPC processor.
The scheme provided by the invention can realize the instruction set simulation of the PowerPC instruction architecture processor, and has high simulation precision; the invention adopts the array, the linked list and the like to realize the simulation of the register and the memory, and can complete the simulation of the PowerPC instruction architecture processor.
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FIG. 1 is a schematic diagram for explaining an implementation technique;
fig. 2 is a schematic diagram of instruction information.
Detailed Description
To make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be given with reference to the accompanying drawings and examples.
The invention provides a virtualized running environment for embedded processing software, and provides a PowerPC instruction architecture processor virtualized simulation technical scheme based on interpretation execution. The method and the device provide an operating environment of the embedded processor software of the PowerPC processor and support for development of the embedded processor software of the PowerPC processor.
S1, powerPC instruction architecture target file analysis
Opening an executable file compiled by a PowerPC instruction architecture, and acquiring a code segment corresponding to a Program Header;
the PowerPC processor File format is ELF, and information such as a File Header, a Section Header, a Program Header and the like in the File information is read according to the ELF File format File information to obtain a code segment corresponding to the Program Header;
s2, powerPC instruction architecture memory emulation and code loading
In order to improve the expandability of the memory simulation, a linked list structure is adopted to simulate the memory of the processor of the PowerPC instruction architecture, the memory is marked as PowerPC-VMemory, a code segment corresponding to a Program Header is loaded, and the memory read-write operation of the PowerPC instruction architecture is simulated.
S3, powerPC instruction architecture register emulation
The simulation is carried out on 197 registers in total of PowerPC instruction architecture e300, e500 and e600 chips, and the simulation is divided into 32 GPR general registers, 32 FPR floating point processing registers, 51 special registers, 41 e600 special registers and 41 e500 special registers, and 197 registers in total.
S4, powerPC instruction architecture instruction description
Each instruction has a unique representation, and each instruction is divided into different segments; in order to accurately describe an Instruction structure, the invention adopts a mode of segmenting an Instruction to describe, acquires operation code information of Instruction, constructs an Instruction operation code information array PowerPC-InstructionDesp [425], describes 425 instructions of a POWERPC architecture Instruction set architecture, and stores the 425 instructions into the Instruction operation code information array PowerPC-InstructionDesp [425 ].
S5, powerPC instruction architecture read instruction
Reading an Instruction from the simulated memory PowerPC-VMemail according to the value of the program counter PC (Program Count), and obtaining an Instruction PC-Instruction corresponding to the current PC;
s6, powerPC instruction architecture instruction decoding
The POWERPC architecture Instruction architecture contains 425 Instruction sets, according to the Instruction description of the PowerPC Instruction architecture, whether the corresponding bit of PC-Instruction and PowerPC-Instruction Desp [425] is the same or not is calculated one by one, if the corresponding position of the kth Instruction description in PC-Instruction and PowerPC-Instruction Desp [425] is the same, instruction decoding is completed, and the Instruction decoding is recorded as instruction_k.
S7, powerPC instruction architecture instruction translation
Performing functional translation on a PowerPC instruction architecture instruction set, designing a function which is operated in a virtual simulation processor and simulates the operation of each instruction, and ensuring that after each instruction and the function are processed, the memories and registers of a hardware processor and the virtual simulation processor are kept consistent; storing the function pointer into a PowerPC-InstructionInterp 425 array, wherein the storage sequence is consistent with the instruction sequence of PowerPC-InstructionDesp 425;
s8, powerPC instruction architecture Linux system call realization
Analyzing the system call, carrying out corresponding processing on the system call according to the type of the system call, and carrying out setting operation on a corresponding register;
s9, powerPC instruction architecture instruction execution
According to the number of instructions, performing cyclic instruction fetching, decoding and instruction translation, and executing instruction operation according to the function pointer; and continuously simulating until all instruction execution is completed, and processing system call to realize processor instruction set simulation aiming at the PowerPC instruction architecture.
Example 1:
the invention provides a PowerPC instruction architecture processor virtualization simulation technical scheme based on interpretation and execution, which simulates by an instruction set
S1, powerPC instruction architecture target file analysis
S11, opening an executable file compiled by a PowerPC instruction architecture;
s12, reading information such as a File Header, a Section Header, a Program Header and the like in File information according to the format of an executable File compiled by a PowerPC instruction architecture, and obtaining a code segment corresponding to the Program Header;
s2, powerPC instruction architecture memory emulation and code loading
S21, in order to improve the expandability of the memory simulation, a linked list structure is adopted to simulate the memory of the PowerPC instruction architecture processor, wherein the size of a linked list structure PowerPC-memory page is 256 words, and the linked list structure comprises: the method comprises the steps of starting a virtual address memory PageBeginaddress, ending the virtual address memory PageEndAdddress, a memory block memory Page, a NEXT memory node pointer NEXT and a previous memory node pointer PRE;
s22, marking the PowerPC instruction architecture memory as PowerPC-VMemory; writing the code segment corresponding to the Program Header acquired in the S1 into a PowerPC instruction architecture chip simulation memory PowerPC-VMemail, and maintaining the whole simulation memory structure according to the size of the code segment
If the code segment is not greater than 256 (the size of one memory page), creating one memory page, and writing the code segment into the memory page array for use;
if the code segment is larger than 256 (the size of one memory page), creating a plurality of memory pages, writing the code segments into the corresponding memory page array in sequence, maintaining MemoryPageBeginAddress, memoryPageEndAddress and other information of each node, and ensuring the correctness of the linked list structure information.
S3, powerPC instruction architecture register emulation
S31, simulating 197 registers in the PowerPC instruction architecture e300, e500 and e600 chips, wherein the registers are divided into 32 GPR general registers, 32 FPR floating point processing registers, 51 special registers, 41 e600 special registers and 41 e500 special registers, and 197 registers in total.
S32, by accessing the PowerPC-Register, performing operation simulation on the elements in the corresponding array to simulate the Register operation of the PowerPC instruction architecture, and realizing the Register simulation on the PowerPC instruction architecture.
S4, powerPC instruction architecture instruction description
S41, all 425 instructions of the PowerPC instruction architecture e300, e500 and e600 processors, wherein each instruction has a unique representation and is divided into different segments; in order to accurately describe an Instruction structure, the invention adopts a mode of segmenting an Instruction to describe, obtains operation code opcode information of Instruction, designs a structure of an Instruction operation code information array PowerPC-Instruction Desp, and comprises the following steps: name, contentNumber and content. The description structure is as follows:
wherein, name is instruction name, contentNumber instruction segmentation number, content is used for storing opcode instruction decoding information.
Taking the addx instruction as an example, the instruction structure is described, wherein the ABS instruction information is as shown in FIG. 2 (from instruction set reference Manual)
Name is "addx"; the instruction opcode (fixed bit in the instruction) is divided into two sections, wherein the first section is bit0-bit5, the second section is bit22-bit30, and the contentNumber is '2'; the content [21] stores opcode information, and the content [21] is "0, 5, 0x1f, 22, 30, 0x10A". Three digits represent a segment, (2, 11, 0x 05) represent bits 0-bit5, with a value of 0x1f; (22, 30, 0x 10A) represents bit22-bit30 bits, and the value is 0x10A.
S42, constructing an instruction operation code information array PowerPC-InstructionDesp [425], describing 425 instructions of the POWERPC architecture instruction set architecture, and storing the 425 instructions into the instruction operation code information array PowerPC-InstructionDesp [425 ].
S5, powerPC instruction architecture read instruction
S51, reading an instruction from the PowerPC-VMemory maintained in the S2 according to the value of the program counter PC (Program Count);
s52, according to the MemoryPageBeginAddress, memoryPageEndAddress value in the PowerPC-MemoryPage, the PC belongs to the PowerPC-MemoryPage, the PowerPC-MemoryPage-i is marked as PowerPC-MemoryPage-i, the address offset is PC-MemoryPageBeginadddress, the Instruction content is MemoryPage [ PC-MemoryPageBeginadddress ] corresponding to the PowerPC-MemoryPage-i, and the PC-Instruction is marked as PC-Instruction.
S6, powerPC instruction architecture instruction decoding
And S61, according to the PC-Instruction read in the S5, calculating whether corresponding bit positions of the PC-Instruction and the PowerPC-Instruction Desp [425] are the same one by one, and if the corresponding positions of the kth Instruction description in the PC-Instruction and the PowerPC-Instruction Desp [425] are the same, recording the Instruction as instruction_k.
S7, powerPC instruction architecture instruction translation
S71, performing functional translation on instructions in a PowerPC instruction architecture instruction set, designing a function which is operated in a virtual simulation processor and simulates the operation of each instruction, and ensuring that after each instruction and the function are processed, the hardware processor is consistent with the memory and the register of the virtual simulation processor;
s72: translating 425 instructions of the PowerPC instruction architecture, and storing function pointers into an instruction translation decoding array PowerPC-InstructionInterp [425] array, wherein the storage sequence is consistent with the instruction sequence of PowerPC-InstructionDesp [425 ];
s73, acquiring a pointer in a function corresponding to the Instruction according to the instruction_k calculated in the S6;
s8, powerPC instruction architecture Linux system call realization
S81, defining 318 system calls of a Linux system, and marking names of the system calls according to the sequence of the Linux system calls, wherein the definition is as follows:
#define SYSCALL_restart_system 0
……
#define SYSCALL_dup2 63
……
#define SYSCALL_inotify_init1 318
s82, analyzing the system call, carrying out corresponding processing on the system call according to the type of the system call, and carrying out setting operation on a corresponding register.
S9, powerPC instruction architecture instruction execution
S91, constructing a simulation framework of a PowerPC instruction framework, performing cyclic instruction fetching, decoding and instruction translation according to the number of instructions, and executing instruction operation according to a function pointer;
s92, continuous simulation is carried out until all instructions are executed, system call is processed, and processor instruction set simulation aiming at the PowerPC instruction architecture is achieved.
The scheme provided by the invention can realize the instruction set simulation of the PowerPC instruction architecture processor, and has high simulation precision; the invention adopts the array, the linked list and the like to realize the simulation of the register and the memory, and can complete the simulation of the PowerPC instruction architecture processor.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (10)
1. A method for virtualized emulation of a general PowerPC architecture processor instruction set, the method comprising the steps of:
s1, powerPC instruction architecture target file analysis
Opening an executable file compiled by a PowerPC instruction architecture, and acquiring a code segment corresponding to a Program Header;
s2, powerPC instruction architecture memory emulation and code loading
Simulating the memory of the processor of the PowerPC instruction architecture by adopting a linked list structure, marking the memory as PowerPC-VMemory, loading a code segment corresponding to a Program Header, and simulating the memory read-write operation of the PowerPC instruction architecture;
s3, powerPC instruction architecture register emulation
The register is simulated through an array simulation register and through read-write operation of an array operation simulation register;
s4, powerPC instruction architecture instruction description
Each instruction has a unique representation, and each instruction is divided into different segments; the method comprises the steps of describing an Instruction in a segmentation mode, obtaining operation code information of Instruction construction, constructing an Instruction operation code information array PowerPC-InstructionDesp [425], describing 425 instructions of a POWERPC architecture Instruction set architecture, and storing the 425 instructions into the Instruction operation code information array PowerPC-InstructionDesp [425 ];
s5, powerPC instruction architecture read instruction
Reading an Instruction from the simulated memory PowerPC-VMemail according to the value of the program counter PC, and obtaining an Instruction PC-Instruction corresponding to the current PC;
s6, powerPC instruction architecture instruction decoding
According to the Instruction description of the PowerPC Instruction architecture, calculating whether corresponding bit positions of the PC-Instruction and the PowerPC-Instruction Desp [425] are the same one by one, if the corresponding positions of the kth Instruction description in the PC-Instruction and the PowerPC-Instruction Desp [425] are the same, finishing Instruction decoding, and marking as instruction_k;
s7, powerPC instruction architecture instruction translation
Performing functional translation on a PowerPC instruction architecture instruction set, designing a function which is operated in a virtual simulation processor and simulates the operation of each instruction, and ensuring that after each instruction and the function are processed, the memories and registers of a hardware processor and the virtual simulation processor are kept consistent; storing the function pointer into a PowerPC-InstructionInterp 425 array, wherein the storage sequence is consistent with the instruction sequence of PowerPC-InstructionDesp 425;
s8, powerPC instruction architecture Linux system call realization
Analyzing the system call, carrying out corresponding processing on the system call according to the type of the system call, and carrying out setting operation on a corresponding register;
s9, powerPC instruction architecture instruction execution
According to the number of instructions, performing cyclic instruction fetching, decoding and instruction translation, and executing instruction operation according to the function pointer; and continuously simulating until all instruction execution is completed, and processing system call to realize processor instruction set simulation aiming at the PowerPC instruction architecture.
2. The method for virtualized emulation of a general purpose PowerPC architecture processor instruction set of claim 1, wherein step S1 specifically comprises:
s11, opening an executable file compiled by a PowerPC instruction architecture;
s12, reading File Header, section Header and Program Header information in File information according to the format of the executable File compiled by the PowerPC instruction architecture, and obtaining a code segment corresponding to the Program Header.
3. The method for virtualized emulation of a general purpose PowerPC architecture processor instruction set of claim 2, wherein step S2 specifically comprises:
s21, simulating a PowerPC instruction architecture processor memory by adopting a linked list structure, wherein the size of a linked list structure PowerPC-memory Page is 256 words;
s22, marking the PowerPC instruction architecture memory as PowerPC-VMemory; writing the code segment corresponding to the Program Header acquired in the S1 into a PowerPC instruction architecture chip simulation memory PowerPC-VMemail, and maintaining the whole simulation memory structure according to the size of the code segment.
4. The universal PowerPC architecture processor instruction set virtualization emulation method of claim 3, wherein the linked list structure comprises: the start virtual address memmorypagebeginaldddress, the end virtual address memmorypageendddress, the memory block memmorypage, the NEXT memory node pointer NEXT, and the previous memory node pointer PRE.
5. The method of claim 3, wherein in step S22, if the code segment is not larger than a memory page size 256, a memory page is created and the code segment is written into the memory page array for use; if the code segment is larger than 256, creating a plurality of memory pages, writing the code segments into the corresponding memory page array in sequence, maintaining MemoryPageBeginAddress, memoryPageEndAddress information of each node, and ensuring the correctness of the linked list structure information.
6. The method for virtualized emulation of a general purpose PowerPC architecture processor instruction set of any one of claims 2-5, wherein step S3 comprises:
s31, simulating 197 registers in total of PowerPC instruction architecture e300, e500 and e600 chips, and realizing the simulation of the registers through an array PowerPC-Register simulation Register;
s32, by accessing the PowerPC-Register, performing operation simulation on the elements in the corresponding array to simulate the Register operation of the PowerPC instruction architecture, and realizing the Register simulation on the PowerPC instruction architecture.
7. The method for virtualized emulation of a general purpose PowerPC architecture processor instruction set of claim 6, wherein step S4 comprises: the structure of the instruction operation code information array PowerPC-InstructInDesp comprises: name, contentNumber and content, where name is the instruction name, content number instruction fragment number, content is used to store opcode instruction decoding information.
8. The method for virtualized emulation of a general purpose PowerPC architecture processor instruction set of claim 7, wherein step S5 comprises:
s51, reading an instruction from the PowerPC-VMemory maintained in the S2 according to the value of the program counter PC;
s52, according to the MemoryPageBeginAddress, memoryPageEndAddress value in the PowerPC-MemoryPage, the PC belongs to the PowerPC-MemoryPage, the PowerPC-MemoryPage-i is marked as PowerPC-MemoryPage-i, the address offset is PC-MemoryPageBeginadddress, the Instruction content is MemoryPage [ PC-MemoryPageBeginadddress ] corresponding to the PowerPC-MemoryPage-i, and the PC-Instruction is marked as PC-Instruction.
9. The method for virtualized emulation of a general purpose PowerPC architecture processor instruction set of claim 1, wherein step S7 specifically comprises:
s71, performing functional translation on instructions in a PowerPC instruction architecture instruction set, designing a function which is operated in a virtual simulation processor and simulates the operation of each instruction, and ensuring that after each instruction and the function are processed, the hardware processor is consistent with the memory and the register of the virtual simulation processor;
s72: translating 425 instructions of the PowerPC instruction architecture, and storing function pointers into an instruction translation decoding array PowerPC-InstructionInterp [425] array, wherein the storage sequence is consistent with the instruction sequence of PowerPC-InstructionDesp [425 ];
s73, acquiring a pointer in a function corresponding to the Instruction according to the instruction_k calculated in the S6.
10. The method for virtualized emulation of a general purpose PowerPC architecture processor instruction set of claim 9, wherein step S9 specifically comprises:
s91, constructing a simulation framework of a PowerPC instruction framework, performing cyclic instruction fetching, decoding and instruction translation according to the number of instructions, and executing instruction operation according to a function pointer;
s92, continuous simulation is carried out until all instructions are executed, system call is processed, and processor instruction set simulation aiming at the PowerPC instruction architecture is achieved.
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| CN111026504A (en) * | 2019-12-06 | 2020-04-17 | 海光信息技术有限公司 | Processing method and device for configuring instruction for acquiring processor information in virtual machine, CPU chip, system on chip and computer |
| WO2021249193A1 (en) * | 2020-06-12 | 2021-12-16 | 华为技术有限公司 | Method and apparatus for processing exception or interrupt under heterogeneous instruction set architecture |
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| US20050076186A1 (en) * | 2003-10-03 | 2005-04-07 | Microsoft Corporation | Systems and methods for improving the x86 architecture for processor virtualization, and software systems and methods for utilizing the improvements |
| EP1622009A1 (en) * | 2004-07-27 | 2006-02-01 | Texas Instruments Incorporated | JSM architecture and systems |
| CN101246452B (en) * | 2007-02-12 | 2010-12-15 | 国际商业机器公司 | Method and apparatus for fast performing MMU analog, and total system simulator |
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| CN111026504A (en) * | 2019-12-06 | 2020-04-17 | 海光信息技术有限公司 | Processing method and device for configuring instruction for acquiring processor information in virtual machine, CPU chip, system on chip and computer |
| WO2021249193A1 (en) * | 2020-06-12 | 2021-12-16 | 华为技术有限公司 | Method and apparatus for processing exception or interrupt under heterogeneous instruction set architecture |
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