CN115276944B - Method and system for compensating signal IQ path clock deviation by comprehensive tester - Google Patents
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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Abstract
The invention provides a method and a system for compensating signal IQ path clock deviation by a comprehensive tester, and belongs to the technical field of comprehensive tester detection. The comprehensive tester is internally provided with a clock deviation compensation module which performs clock compensation on the received IQ signal, and the compensation method of the clock deviation compensation module comprises the following steps: reading a signal source and a preset IQ path clock deviation value; constructing a compensation coefficient according to the duration deviation value; reconstructing a signal of clock deviation according to the compensation coefficient; the output signal source compensates the compensation signal after the clock imbalance. The invention also provides a method and a system for realizing calibration of the comprehensive tester and compensating signal IQ path clock deviation by adopting the comprehensive tester. The method and the device correct the influence of the clock deviation of the comprehensive tester on the vector signal, and effectively improve the accuracy and stability of the signal performance of the equipment to be tested.
Description
Technical Field
The invention relates to a comprehensive tester detection technology, in particular to an improved comprehensive tester, and a method and a system for calibrating and compensating signal IQ path clock deviation by the comprehensive tester.
Background
A comprehensive tester is a device for analyzing the performance of vector signals, and a receiver thereof is shown in fig. 1, and comprises the following components: ADC: (Analog Detection Circuit) analog detection circuitry for converting the analog signal to a digital signal; BPF: (Band PASS FILTER) Band pass filters; LPF: (Low PASS FILTER) Low pass Filter; LNA: (Low Noise Amplifier) a low noise power amplifier for amplifying the signal power; LO: (Local Oscillator) Local Oscillator for generating quadrature I, Q signals; AGC: (Automatic Gain Control) automatic gain control for adjusting the signal to a bit width suitable for the ADC; clk: the reference clock uses a filter. The components such as the mixer, the amplifier and the like convert the radio frequency signals back to baseband signals to complete signal reception. Since components distort the signal and most of the impairments cannot be removed in the analog domain, it is very necessary for the design to compensate for the directional impairments in the digital domain in order to achieve high performance and low cost.
Clock skew refers to the difference in clock delays of the same clock to different register clock terminals within the clock domain. In the process from the radio frequency signal to the baseband signal, the I path signal and the Q path signal are demodulated by a mixer, and I, Q paths of signals pass through different filters and ADCs. Fig. 1 also includes a basic clock skew model in a synchronous circuit, where clock signals clk1 and clk2 belong to the same clock source clk, driving adc_i and adc_q, respectively. The clock end delays t clk1 and t clk2 from clk to adc_i and adc_q are different, i.e., the clock offset value between the two ADCs is t skew＝tclk1-tclk2, due to the difference in the distance between adc_i and adc_q from the clock source. Clock skew can cause signal distortions that affect the analytical capabilities of the meter. In order to improve the detection performance of the receiving end of the comprehensive tester, I, Q paths of signals need to be correspondingly compensated, so that the detection precision of the comprehensive tester is improved.
Assuming that the received analog signal is s (t), after the ideal local oscillation, the I path analog signal and the Q path analog signal are respectivelyWherein omega s is the radio frequency at which the signal is located,For the initial phase introduced after passing through the transceiver, when the ADC sampling rate is Fs, the sampling period ts=1/Fs. The mathematical principle of ADC sampling process is that analog signal and unit impulse function delta (t-nTs) are sampled, i.e. baseband signal I path and Q path are respectivelyAnd
Assuming that the clock bias is Δt, the Q-way reception becomes based on the I-way At this time, the Q-way signal affected by the clock skew at isBecause the clock deviation of the comprehensive tester itself causes loss of acquisition actual signals, namely, the accuracy of test signals is damaged due to the clock deviation of the comprehensive tester, the method and the system must be found to compensate the clock deviation of the comprehensive tester.
From the reasons, the clock deviation of the comprehensive tester is caused by the reasons of circuit devices and the like, the clock deviation is far smaller than the sampling rate in the practical device design, and once the device is shaped, the clock deviation value is fixed, so that the clock deviation of the comprehensive tester can be eliminated to the extent that the signal quality is hardly influenced by the comprehensive tester by designing a reasonable compensation mode.
Disclosure of Invention
In order to solve the technical problem that in the prior art, in a comprehensive tester applied to analyzing vector signal performance, clock deviation exists in an I circuit and a Q circuit due to different clocks of components used by the comprehensive tester, the invention provides the comprehensive tester, wherein a clock deviation compensation module is designed in the comprehensive tester and used for compensating adverse effects of different clocks of an IQ two ADC on a baseband signal, and a method and a system for compensating the clock deviation of the IQ circuit of the signal by the comprehensive tester are provided, so that the accuracy and the stability of analyzing the signal performance are improved.
The comprehensive tester is internally provided with a clock deviation compensation module which performs clock compensation on the received IQ signal, and the compensation method of the clock deviation compensation module comprises the following steps:
S1: reading a signal source and a preset clock deviation value;
S2: constructing a compensation coefficient according to the duration deviation value;
s3: reconstructing a signal of clock deviation according to the compensation coefficient;
s4: the output signal source compensates the compensation signal after the clock imbalance.
In step S1, the baseband signal acquired by the heald meter is denoted as y (k) =i (k) +q (k) ×i, k=1, …, M, I is an imaginary unit, where the baseband signal duration is τ, the sampling rate is Fs, m=τ×fs is the total number of sampling points, k is the sampling point, I-path signal is I (k), Q-path signal is Q (k), and the clock bias of I, Q paths is a known Δt.
In step S2, L points near the sampling point within a certain period of time are set, L is an even number, and then a compensation coefficient sequence is obtained according to the L points, where the compensation coefficient sequence is as follows:
the invention is further improved, the number of samples L near the sampling point is selected to be 6, in the step S3, the Q paths of signals are reconstructed, and the signals after the Q paths of signals are reconstructed according to the compensation coefficient are as follows:
when k+ -M <1 or k+ -M > M (m.epsilon.0, L/2 ]), Q (k+ -M) in the formula takes a value of 0.
In step S4, the baseband compensated for Q signals is output, and the output baseband signals are: y *(k)＝I(k)+Q* (k) i.
The invention also provides a method for compensating signal IQ path clock deviation by the comprehensive tester, which comprises the following steps:
A1: acquiring a test signal of a DUT (device under test);
A2: reading a clock deviation compensation value according to the frequency point;
a3: adopting a clock deviation compensation module to compensate;
A4: and (5) signal analysis and demodulation.
In step A2, the method for calibrating the clock offset value is as follows:
B1: the signal source selects the frequency point to send the standard signal;
B2: traversing the clock imbalance compensation value;
B3: the clock deviation compensation module compensates;
B4: signal analysis and demodulation;
b5: and selecting the clock deviation corresponding to the optimal EVM combination as a final clock deviation compensation value.
The invention is further improved, and the specific treatment method of the step B2 is as follows:
The comprehensive tester continuously receives standard signals sent by a signal source in the step A201, and the baseband signals collected and combined by I, Q paths of ADC (analog to digital converter) are recorded as y (k) =I (k) +Q (k) I, and the signals are traversed by time granularity tau=0.01 x Ts, namely clock deviation Where τ is the baseband signal duration, ts is the sampling period, fs is the sampling rate, m=τ×fs is the total number of sampling points, and k=1, …, M in the range of [ -Ts/2, …, ts/2 ].
In step B4, the processing method of signal analysis and demodulation is as follows:
Analyzing the baseband signal compensated by the clock deviation compensation module, analyzing a signal error vector EVM, and after signal demodulation, analyzing the distance between the receiving position and the defined position of the signal, namely obtaining the EVM, wherein the calculating mode is as follows:
Wherein S meas,r is the signal receiving position, S std,r is the ideal position after demodulation in S meas,r, and N is the number of points of all effective signals.
In step B5, the EVM obtained based on the signal analysis after the different Δt compensation is compared, and Δt with the smallest EVM correlation is selected as the clock bias compensation value of the current frequency point.
The invention also provides a system for realizing the method for compensating signal IQ path clock deviation by the comprehensive tester, which comprises the following steps:
And a receiving module: the method comprises the steps of obtaining a test signal of a device under test DUT;
And a reading module: the clock bias compensation value is used for reading the clock bias compensation value according to the frequency point;
and the compensation module is used for: the clock deviation compensation module is used for compensating;
demodulation module: for analysis and demodulation of the compensated signal.
The invention further improves, also includes the clock deviation compensation value calibration module: for calibrating a clock skew compensation value, the clock skew compensation value calibration module comprising:
A signal transmitting unit: for selecting a frequency point to transmit a standard signal;
traversing unit: for traversing the clock imbalance compensation values;
And a compensation unit: the clock deviation compensation module is used for compensating;
and a selection module: and the clock deviation compensation module is used for acquiring the optimal EVM combination processed by the compensation module and the demodulation module, and then selecting the clock deviation corresponding to the optimal EVM combination as a final clock deviation compensation value.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the clock deviation compensation module is designed in the comprehensive tester and is used for compensating adverse effects caused by different clocks of the IQ two paths of ADC on the baseband signal, the clock deviation compensation module realizes the determination of the compensation coefficient through the calibration means, and then the compensation is carried out according to the compensation coefficient when the vector signal is analyzed, so that the influence caused by the clock deviation of the comprehensive tester on the vector signal to be analyzed is corrected, and the accuracy and stability of the DUT signal performance are improved.
Drawings
FIG. 1 is a schematic diagram of a receiving model of a comprehensive tester and a clock deviation model thereof;
FIG. 2 is a flow chart of a method for processing a clock skew compensation module;
FIG. 3 is a flow chart of a method for calibrating clock bias values using a compensation system for a comprehensive tester;
FIG. 4 is a flow chart of a method for compensating signals of equipment to be measured by a comprehensive tester;
fig. 5 is a schematic diagram of defining a signal error vector EVM.
Detailed Description
It should be noted that the invention is applied to the compensation function of the test equipment component influence signal.
It should be noted that the operation method of the present invention is easy to change, and the idea and execution method of using the present invention to compensate clock bias are all within the protection scope of the present invention.
The invention is described below in conjunction with the drawings, it being understood that the description is provided for illustration and explanation of the invention only and is not intended to limit the invention thereto.
The invention is applied to a comprehensive tester for analyzing vector signal performance, the clock deviation of an I circuit and a Q circuit can be caused by different component clocks used by the comprehensive tester, the invention designs a clock deviation compensation module in the comprehensive tester for compensating adverse effects of different clocks of an IQ circuit and an ADC circuit on a baseband signal, the clock deviation compensation module realizes the determination of compensation coefficients through a calibration means, and then compensates according to the compensation coefficients when analyzing the vector signal, thereby correcting the influence of the clock deviation of the comprehensive tester on the vector signal to be analyzed and the accuracy and stability of the DUT signal performance.
Thus, the present invention essentially comprises three processes: one is a clock error compensation system design, one is a calibration design of the comprehensive tester using the compensation system, and one is a compensation design of the comprehensive tester for measuring DUT signals, and each process is described in detail below.
1. Clock error compensation system design
The clock error compensation system design of the embodiment is realized by designing a clock error compensation module in the comprehensive tester.
As shown in fig. 2, the clock error compensation module design in this example mainly includes four implementation steps:
S1: reading a signal source and a preset clock deviation value;
S2: constructing a compensation coefficient according to the duration deviation value;
s3: reconstructing a signal of clock deviation according to the compensation coefficient;
s4: the output signal source compensates the compensation signal after the clock imbalance.
The comprehensive tester is commonly used for research and development and production end equipment for evaluating whether the performance of products (objects to be tested and DUTs) is qualified or not, and is required to have high precision, and a basic receiving model of the comprehensive tester is shown in figure 1. Errors can be caused by components of the comprehensive tester, and if any errors exist, errors of the comprehensive tester are introduced when the object to be tested is tested, and the testing precision is greatly affected. Therefore, the comprehensive tester needs to press the error of the comprehensive tester in a very small range, and the precision error is far lower than that of the object to be tested. The processing procedure of each step is described in detail below.
Step S1: reading signal source and preset clock deviation value
The baseband signal acquired by the comprehensive tester is expressed as y (k) =i (k) +q (k) ×i, k=1, …, M, I is an imaginary unit. Wherein the baseband signal duration is τ, the sampling rate is Fs, and m=τ×fs is the total number of sampling points. The I-path signal is I (k), and the Q-path signal is Q (k). I. The clock bias of the Q-way is known Δt.
Step S2: building compensation coefficient according to duration deviation value
From theory, it is deduced that Δt affects Q * (k) by L points nearby, and Q * (k±1) is the greatest, L is generally not too much, and in this example, l=6, and then the compensation coefficient sequence is:
Step S3: reconstructing a signal from compensation coefficients
Reconstructing the Q-channel signal to receive the Q (k) channel signal and calculate the compensation coefficient in step S2 by the following way
When k+ -M <1 or k+ -M > M (m.epsilon.0, L/2 ]), Q (k+ -M) in the formula takes a value of 0.
Step S4: compensating signal after input signal source compensating clock unbalance
And outputting the baseband of the Q paths of signals compensated in the step 3, so that the clock deviation of I, Q is compensated after the compensation.
y*(k)＝I(k)+Q*(k)*i，k＝1,…,M
2. Calibration design of comprehensive tester by using compensation system
Because the I path analog signal and the Q path analog signal are respectively: Where ω s is the radio frequency at which the signal is located, Is the initial phase introduced after passing through the receiving and transmitting end. That is, I, Q-way clock skew affects inconsistencies across different radio frequencies ω s.
Then, after the comprehensive tester is molded, the specific clock deviation delta t at a certain frequency point is not confirmed, but the delta t can be basically fixed after the comprehensive tester is molded. Then Δt can be confirmed with the clock imbalance compensation system.
As shown in fig. 3, the method for confirming this example uses an ideal signal source to send a signal, traverses different Δt to perform clock imbalance compensation, analyzes signal quality of the signal after compensating for different Δt, can evaluate the signal quality with EVM, and comprehensively obtains the clock offset Δt with the minimum EVM, which can be regarded as the clock offset value on the corresponding frequency point of the comprehensive tester, and is used as the clock imbalance compensation value of the frequency point. The respective steps are described in detail below.
Step B1: signal source selection frequency point transmitting standard signal
According to the signal frequency supported by the comprehensive tester radio frequency, such as the common frequency bands of 2.4G and 5G, the signal source transmits ideal signal groups by traversing according to the granularity of 1M, and the ideal signals can select the common signals in the WLAN protocol.
Step B2: traversing clock imbalance compensation values
The comprehensive tester continuously receives standard signals sent by the signal source in the step 1, and baseband signals collected and combined by I, Q paths of ADC (analog to digital converter) are marked as y (k) =I (k) +Q (k) ×i, k=1, … and M, wherein the duration of the baseband signals is tau, the sampling rate is Fs, and M=tau×Fs is the total sampling point number. Traversal at time granularity τ=0.01×ts, i.e. clock bias, in the range [ -Ts/2, …, ts/2]
Step B3: the clock deviation compensation module compensates
And (3) sending y (k) in the step (1) and deltat in the step (2) to a clock error compensation module, and obtaining a signal y * (k) after compensating clock deviation.
Step B4: signal analysis demodulation
The y * (k) signal is analyzed, and finally the signal error vector EVM is resolved. As defined for EVM in fig. 5, after demodulating the signal, the receiving position of the signal is analyzed from the defined position distance, i.e., the EVM is obtained. The calculation method is as follows:
wherein S meas,r is the position of the signal in the signal receiving process, S std,r is the ideal position after demodulation in S meas,r, and N is the number of points of all effective signals.
Step 5: selecting clock bias corresponding to optimal EVM combination
And under the corresponding frequency point, comparing EVM obtained based on signal analysis after different delta t compensation, and selecting delta t with the smallest EVM correlation as a clock deviation compensation value of the current frequency point. After compensation, the error still exists is not corrected by I, Q paths of clock deviation, but the phase noise of the device, and the signal error caused by links such as noise and the like is generated.
Then, all frequency points supported by the comprehensive tester determine corresponding I, Q paths of clock offset values, and the corresponding I, Q paths of clock offset values are written into the comprehensive tester and used as fixed data of a calibration module.
3. Comprehensive tester measuring DUT signal compensation system
The final purpose of the tester is to measure DUT signals.
As shown in FIG. 4, the calibration design of the DUT signal compensation system measured by the comprehensive tester mainly comprises four steps: and receiving the DUT test signal, reading a clock deviation value in the calibration module according to the signal frequency point, supplementing by the clock deviation compensation module, and analyzing and demodulating the signal. The respective steps are described in detail below.
Step A1: receiving DUT test signals
The comprehensive tester establishes a link with the DUT to control the DUT to send radio frequency signals to be measured, and the comprehensive tester collects the radio frequency signals at corresponding frequency points to form baseband signals y (k) =i (k) +Q (k) ×i, k=1, … and M, wherein the duration of the baseband signals is tau, the sampling rate is Fs, and the M=tau×Fs is the total sampling point number.
Step A2: reading clock deviation value in calibration module according to signal frequency point
And reading a clock deviation value delta t of a corresponding frequency point from the comprehensive tester calibration system according to the frequency point of the radio frequency signal.
Step A3: the clock deviation compensation module compensates
And (3) sending y (k) in the step (1) and deltat in the step (2) to a clock error compensation module, and obtaining a signal y * (k) after compensating clock deviation.
Step A4: signal analysis demodulation
Analyzing y * (k) signals, analyzing each index according to the test requirement of DUT signals, checking whether the DUT signal index reaches the performance index required by the protocol, if so, designing the DUT to reach the standard, otherwise, failing the DUT, and redesigning and calibrating according to the method.
The above embodiments are preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, which includes but is not limited to the embodiments, and equivalent modifications according to the present invention are within the scope of the present invention.
Claims (8)
1. A method for compensating signal IQ path clock deviation by a comprehensive tester is characterized in that: the comprehensive tester is internally provided with a clock deviation compensation module which performs clock compensation on the received IQ signal, and the compensation method of the clock deviation compensation module comprises the following steps:
S1: reading a signal source and a preset clock deviation value;
S2: constructing a compensation coefficient according to the duration deviation value;
s3: reconstructing a signal of clock deviation according to the compensation coefficient;
s4: the output signal source compensates the compensation signal after the clock imbalance,
The method for compensating the signal IQ path clock deviation by the comprehensive tester comprises the following steps:
A1: acquiring a test signal of a DUT (device under test);
A2: reading the calibrated clock deviation compensation value according to the frequency point;
a3: adopting a clock deviation compensation module to compensate;
A4: the signal is analyzed and demodulated,
In step A2, the method for calibrating the clock offset value includes:
B1: the signal source selects the frequency point to send the standard signal;
B2: traversing the clock imbalance compensation value;
B3: the clock deviation compensation module compensates;
B4: signal analysis and demodulation;
b5: and selecting the clock deviation corresponding to the optimal EVM combination as a final clock deviation compensation value.
2. The method for compensating signal IQ path clock bias by a comprehensive tester according to claim 1 wherein: in step S1, the baseband signal acquired by the heald meter is denoted as y (k) =i (k) +q (k) ×i, k=1, …, M, I is an imaginary unit, where the baseband signal duration is τ, the sampling rate is Fs, m=τ×fs is the total number of sampling points, k is the sampling point, I-channel signal is I (k), Q-channel signal is Q (k), and I, Q-channel clock deviation is a known Δt,
In step S2, L points near the sampling point within a certain period of time are set, L is an even number, and then a compensation coefficient sequence is obtained according to the L points, where the compensation coefficient sequence is as follows:
3. the method for compensating signal IQ path clock bias by a comprehensive tester according to claim 2 wherein: selecting the number of samples L near the sampling point as 6, and reconstructing the Q paths of signals in step S3, wherein the signals after reconstructing the Q paths of signals according to the compensation coefficient are as follows:
When k+/-M is less than 1 or k+/-M is more than M, M is 0 and L/2, Q (k+/-M) in the formula is 0, and in step S4, outputting the baseband compensated with Q paths of signals, wherein the output baseband signals are as follows:
y*(k)＝I(k)+Q*(k)*i。
4. The method for compensating signal IQ path clock bias for a comprehensive tester according to claim 3 wherein: the specific processing method of the step B2 is as follows:
The comprehensive tester continuously receives standard signals sent by a signal source in the step A201, and the baseband signals collected and combined by I, Q paths of ADC (analog to digital converter) are recorded as y (k) =I (k) +Q (k) I, and the signals are traversed by time granularity tau=0.01 x Ts, namely clock deviation Where τ is the baseband signal duration, ts is the sampling period, fs is the sampling rate, m=τ×fs is the total number of sampling points, and k=1, …, M in the range of [ -Ts/2, …, ts/2 ].
5. The method for compensating signal IQ path clock bias for a comprehensive tester according to claim 4 wherein: in step B4, the signal analysis and demodulation processing method comprises the following steps:
Analyzing the baseband signal compensated by the clock deviation compensation module, analyzing a signal error vector EVM, and after signal demodulation, analyzing the distance between the receiving position and the defined position of the signal, namely obtaining the EVM, wherein the calculating mode is as follows:
wherein S meas,r is the signal receiving position, S std,r is the ideal position after demodulation in S meas,r, and N is the number of points of all effective signals.
6. The method for compensating signal IQ path clock bias for a comprehensive tester according to claim 5 wherein: in step B5, at the corresponding frequency point, the EVM obtained based on the signal analysis after the different Δt compensation is compared, and Δt with the smallest EVM correlation is selected as the clock bias compensation value of the current frequency point.
7. A system for implementing the method for compensating signal IQ path clock deviation by using comprehensive measuring instrument according to any one of claims 1-6,
Characterized by comprising the following steps:
And a receiving module: the method comprises the steps of obtaining a test signal of a device under test DUT;
And a reading module: the clock bias compensation value is used for reading the clock bias compensation value according to the frequency point;
and the compensation module is used for: the clock deviation compensation module is used for compensating;
demodulation module: for analysis and demodulation of the compensated signal.
8. The system according to claim 7, wherein: the clock deviation compensation value calibration module is also included: for calibrating a clock skew compensation value, the clock skew compensation value calibration module comprising:
A signal transmitting unit: for selecting a frequency point to transmit a standard signal;
traversing unit: for traversing the clock imbalance compensation values;
And a compensation unit: the clock deviation compensation module is used for compensating;
and a selection module: and the clock deviation compensation module is used for acquiring the optimal EVM combination processed by the compensation module and the demodulation module, and then selecting the clock deviation corresponding to the optimal EVM combination as a final clock deviation compensation value.
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