CN115202257B

CN115202257B - LPC bus protocol conversion and equipment parallel control device and method

Info

Publication number: CN115202257B
Application number: CN202210831547.0A
Authority: CN
Inventors: 苏振宇
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-07-15
Filing date: 2022-07-15
Publication date: 2024-01-23
Anticipated expiration: 2042-07-15
Also published as: CN115202257A

Abstract

The invention relates to the field of LPC bus protocol conversion, in particular to an LPC bus protocol conversion and equipment parallel control device and method, wherein a PCI/PCIE protocol IP core converts a physical PCI/PCIE signal into a local end signal, and stores an M-bit data signal of the local end into a data buffer area; the master control state machine divides the local end data signals in the data buffer into N groups, each group has 4bit, and corresponding packet data is sent to each gated LPC control logic; receiving data read from LPC equipment by each strobe LPC control logic, combining the data into M-bit data, and sending the data to an upper computer through a PCI/PCIE bus; the data buffer area buffers the data; the LPC control logic realizes an LPC bus protocol, converts received packet data and control signals into LPC bus signals, and drives external LPC equipment to work; the clock control module performs clock frequency conversion. The invention overcomes the limitation of the prior art, realizes the compatibility of the server main board to the LPC equipment, and can meet the use of the LPC equipment with an LPC interface, thereby improving the safety and efficiency of the system.

Description

LPC bus protocol conversion and equipment parallel control device and method

Technical Field

The invention relates to the field of LPC bus protocol conversion, in particular to an LPC bus protocol conversion and equipment parallel control device and method.

Background

LPC is a bus protocol developed by Intel corporation for replacing the conventional ISA bus in computer systems. The LPC is a parallel bus with 33MHz clock frequency and 4 bits data width, and consists of 13 signal wires, wherein 7 necessary signals and 6 optional signals can realize LPC communication only by 7 necessary signals, so that the implementation mode is flexible. However, with the development of server motherboard technology, the main current motherboard generally only has 1 LPC physical slot, even some motherboards do not provide LPC slots, so that the IO devices with LPC interfaces such as TCM and TPM cannot be used on the server in a compatible manner, and therefore, the use requirement of the server on the cryptographic module with LPC bus interfaces cannot be met. Moreover, the existing motherboard has only 1 LPC physical slot, so that the parallel running function of a plurality of LPC devices cannot be realized. FIGS. 1 and 2 are prior art two LPC interface schemes, in FIG. 1, the LPC bus is located under the south bridge PCH, and cannot control a plurality of LPC devices in parallel, and in addition, if the motherboard does not have an LPC physical slot, the LPC devices cannot be used; fig. 2 shows that a BMC (baseboard management controller) communicates with a PCH as an LPC device, and the BMC also supports an LPC bus protocol, but receives PCH information only as a Slave mode (Slave), and cannot control an LPC device such as TCM as a Master mode (Master).

Disclosure of Invention

In order to solve the problems, the invention provides an LPC bus protocol conversion and equipment parallel control device and method, which utilize PCI/PCIe physical slots to convert PCI/PCIe bus signals into multipath LPC bus signals, can control a plurality of LPC equipment to work in parallel, realize the compatibility of a server main board to the LPC equipment, meet the use of the LPC equipment with an LPC interface, and improve the safety and efficiency of a system.

In a first aspect, the present invention provides an LPC bus protocol conversion and device parallel control apparatus, including a board, on which a programmable logic device is provided, where the programmable logic device is provided with a master control state machine, a data buffer area, a PCI/PCIE protocol IP core, a clock control module, and N LPC control logics;

PCI/PCIE protocol IP core: the PCI/PCIE signal conversion module is connected with the PCI/PCIE bus, converts the physical PCI/PCIE signal into a local end signal, and stores the local end M bit data signal into a data buffer area; wherein m=n×4;

and (3) a main control state machine: dividing local end data signals in a data buffer area into N groups, wherein each group is 4 bits, gating LPC control logic, and transmitting corresponding packet data to each gated LPC control logic; receiving data read from LPC equipment by each strobe LPC control logic, combining the data into M-bit data, and sending the data to an upper computer through a PCI/PCIE bus;

data buffer area: caching the data;

LPC control logic: the LPC bus protocol is realized, the received packet data and the control signal are converted into LPC bus signals, and external LPC equipment is driven to work;

and the clock control module is used for: and performing clock frequency conversion to serve as an operating clock of each module on the programmable logic device.

Further, the board card is also provided with an external interface, comprising a PCI/PCIe physical bus interface, an LPC equipment interface and a JATG/AS interface;

the PCI/PCIe physical bus interface is used for connecting the PCI/PCI E protocol IP core to the PCI/PCI E bus; the LPC device interface is used for connecting LPC control logic to external LPC device, and the JATG/AS interface is used for debugging and downloading program of the programmable logic device.

Further, a power module is further arranged on the board card to provide working voltage for each module on the board card.

Further, the programmable logic device is an FPGA.

Further, the data buffer is a random access memory or a first-in first-out stack.

In a second aspect, the present invention provides an apparatus for conversion of LPC bus protocol and parallel control of devices, including a BMC, where the BMC is provided with an LPC control logic, and the BMC is connected to an external LPC device through the LPC control logic;

the BMC sends the data and the control signals to the LPC control logic, the LPC control logic realizes an LPC bus protocol, converts the received data and control signals into LPC bus signals, drives external LPC equipment to work, and realizes the active control of the BMC on the external LPC equipment.

In a third aspect, the present invention provides a method for LPC bus protocol conversion and device parallel control of any one of the above devices, including the following steps:

the upper computer sends the data to be processed to the board card through the PCI/PCIE bus;

the PCI/PCIE protocol IP core on the board card receives PCI/PCIE bus data with M bits, processes the PCI/PCIE bus data into a local data signal and stores the local data signal into a data buffer area;

the main control state machine divides the local end data signals in the data buffer area into N groups of 4 bits each; wherein N4 = M;

the master control state machine gates at least one LPC control logic and sends corresponding packet data to each gated LPC control logic;

each gating LPC control logic converts received packet data and control signals into LPC bus signals to drive the LPC equipment to work;

after the gated LPC control logic finishes the reading operation of the LPC equipment data, informing a main control state machine to read the data, and storing the read data into a data buffer area by the main control state machine;

after the master control state machine reads the data from all the gated LPC control logics, the master control state machine combines the 4-bit data of all the LPC control logics into M-bit data and sends the M-bit data to the upper computer through the PCI/PCIE bus.

Further, when the 4-bit data of all the LPC control logic are combined into M-bit data, the corresponding position of the 4-bit data of the ungated LPC control logic in the combined M-bit data is set to "0000".

Further, the LPC control logic drives the LPC equipment through a writing operation state machine of the LPC control logic;

the write operation state machine includes the following states: idle, start, transfer type, write address, write data, control transfer, write wait, end;

the transition flow between states comprises the following steps of:

1) Entering an idle state after the system is reset, and entering a starting state when the reset is finished and the bus transmission signal is valid;

2) In the start state, after 1 clock cycle, the write operation state machine transmits data "0000" to the LAD bus of the LPC device to represent the start of transmission, and then enters a transmission type state;

3) In the transmission type state, transmitting a high-level read-write control signal to an LAD bus of the LPC device after 1 clock period, representing the IO write operation type, and then entering a write address state;

4) In the write address state, 4 clock cycles are passed, the write operation state machine transmits 4-bit addresses to the LAD bus of the LPC device, namely the LPC device receives 16-bit addresses and then enters a write data state;

5) In the data writing state, 2 clock cycles are passed, the writing operation state machine transmits 2 data of 4 bits to the LAD bus of the LPC device, namely the LPC device receives 8bit data and then enters a control right conversion state;

6) In the control right conversion state, the write operation state machine transmits 1111 to the LAD bus of the LPC device after 2 clock cycles, which represents that the control right of the bus is given to the LPC device, and then enters a write waiting state;

7) In the writing waiting state, the writing operation state machine waits for the completion of the operation of the LPC equipment, monitors the LAD bus of the writing operation state machine, and when LAD=0000, the writing operation state machine represents that the operation of the LPC equipment is completed, and then enters an ending state;

8) In the end state, the LPC device passes control back to the write operation state machine after 2 clock cycles, and then returns to the idle state.

Further, the read operation of the LPC control logic to the LPC device data is realized by a read operation state machine of the LPC control logic;

the read operation state machine includes the following states: idle, start, transfer type, read address, control right conversion, read wait, read data, end;

the conversion flow between states comprises the following steps of realizing the reading of LPC control logic to LPC equipment data:

2) In the start state, after 1 clock cycle, the read operation state machine transmits data "0000" to the LAD bus of the LPC device to represent the start of transmission, and then enters a transmission type state;

3) In the transmission type state, transmitting a low-level read-write control signal to an LAD bus of the LPC device after 1 clock period, representing the IO read operation type, and then entering a read address state;

4) In the address reading state, after 4 clock cycles, the read operation state machine reads 4bit addresses from the LAD bus of the LPC device, namely reads the 16bit address of the LPC device, and then enters a control right conversion state;

5) In the control right conversion state, after 2 clock cycles, the read operation state machine transmits 1111 to the LAD of the LPC device, which represents that the control right of the bus is given to the LPC device, and then enters a read waiting state;

6) In a read waiting state, the read operation state machine waits for the data of the LPC device to be ready, monitors the LAD bus of the LPC device, and when LAD=0000, the LPC device is represented to complete the data preparation, and then enters a read data state;

7) In the data reading state, after 2 clock cycles, the read operation state machine reads 2 pieces of 4-bit data from the LAD bus of the LPC equipment, and then enters an ending state;

8) In the end state, after 2 clock cycles, the LPC device passes control back to the read operation state machine, and the read operation state machine sets the data ready-to-complete flag bit to high level, indicating that the reading of the LPC device data has been completed, and then returns to the idle state.

Compared with the prior art, the LPC bus protocol conversion and equipment parallel control device and method provided by the invention have the following beneficial effects: the conversion of LPC protocol and the expansion card of equipment are realized based on the programmable logic device, and the PCI/PCIe bus signals are converted into multipath LPC bus signals by using 1 PCI/PCIe physical slot, so that a plurality of LPC equipment can be controlled to work in parallel. Therefore, the limitation of the prior art can be overcome, the compatibility of the server main board to the LPC equipment is realized, the use of the LPC equipment with an LPC interface can be met, and the safety and the efficiency of the system are improved.

Drawings

For a clearer description of embodiments of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some embodiments of the present application, and that other drawings may be obtained from these drawings by a person of ordinary skill in the art without inventive effort.

Fig. 1 is a prior art LPC interface scheme.

Fig. 2 is a diagram of another prior art LPC interface scheme.

Fig. 3 is a schematic structural diagram of an LPC bus protocol conversion and device parallel control apparatus according to an embodiment of the present invention.

FIG. 4 is a schematic structural diagram of an embodiment of an LPC bus protocol conversion and device parallel control apparatus according to the present invention.

Fig. 5 is a schematic structural diagram of an LPC bus protocol conversion and device parallel control apparatus according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of an LPC bus protocol conversion and device parallel control method according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a connection between a master control state machine and LPC control logic in an embodiment of the present invention.

FIG. 8 is a schematic diagram of an LPC control logic write operation state machine in an embodiment of the present invention.

FIG. 9 is a schematic diagram of an LPC control logic read operation state machine in an embodiment of the present invention.

Detailed Description

In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Fig. 3 is a schematic structural diagram of an LPC bus protocol conversion and device parallel control device provided by the embodiment of the present invention, including a board card, on which a programmable logic device is disposed, and on which a plurality of functional modules are disposed to implement LPC bus protocol conversion and device parallel, where the functional modules include: the PCI/PCIE protocol IP core comprises a main control state machine, a data buffer area, a PCI/PCIE protocol IP core, a clock control module and N LPC control logics.

The specific functions of the respective functional modules are described below.

1) PCI/PCIE protocol IP core: the PCI/PCIE bus is connected with the PCI/PCIE bus, the physical PCI/PCIE signal is converted into a local end signal, and the M-bit data signal of the local end is stored in the data buffer area; where m=n×4.

The data bus bit width of the PCI/PCIE signal is 32bit and 64bit, the data bus bit width of the LPC protocol is 4bit, the protocol conversion converts the 32bit or 64bit width into 4bit width to adapt to the LPC device, thus if the PCI/PCIE signal is 32bit wide, 32/4=8 LPC devices can be controlled in parallel correspondingly, 8 LPC control logics can be set correspondingly, if the PCI/PCIE signal is 64bit wide, 64/4=16 LPC devices can be controlled in parallel correspondingly.

2) And (3) a main control state machine: dividing local end data signals in a data buffer area into N groups, wherein each group is 4 bits, gating LPC control logic, and transmitting corresponding packet data to each gated LPC control logic; and receiving data read from the LPC equipment by each strobe LPC control logic, combining the data into M-bit data, and transmitting the data to the upper computer through the PCI/PCIE bus.

For driving the LPC device, the local side data signals of Mbit are grouped into 4-bit data, i.e. into 8 groups of 4-bit data if they are 32-bit local side data signals, and into 16 groups of 4-bit data if they are 64-bit local side data signals, so as to be allocated to the respective LPC control logic.

The number of the LPC control logics is N, but the LPC control logics are not necessarily all gated in actual operation, only the LPC control logic corresponding to the LPC equipment to be controlled is gated, then the master control state machine sends the corresponding packet data in the packet data to the corresponding gated LPC control logic, and the LPC control logic drives the LPC equipment according to the data and the control signals.

Of course, the master control state machine is also responsible for recombining the data collected from the LPC device into the PCI/PCIE data of 32 bits or 64 bits, and sending the PCI/PCIE data to the upper computer through the PCI/PCIE bus. It should be noted that, when in combination, each LPC control logic corresponds to 4bit data, for gated LPC control logic, the data transmitted to the master state machine is 4bit data read from the LPC device, and for non-gated LPC control logic, the corresponding 4bit position in the combined data may be set to "0000".

3) Data buffer area: and caching the data.

The cached data comprises local end data signals converted by PCI/PCIE signals sent by the upper computer and data read by LPC control logic from LPC equipment.

4) LPC control logic: the LPC bus protocol is realized, the received packet data and control signals are converted into LPC bus signals, and external LPC equipment is driven to work.

N total are set, 8 if the PCI/PCIE data signal is 32 bits wide, and 16 if the PCI/PCIE data signal is 64 bits wide.

5) And the clock control module is used for: and performing clock frequency conversion to serve as an operating clock of each module on the programmable logic device.

For example, to convert the Local side clock signal to the 33MHz clock frequency required for the LPC bus.

The LPC bus protocol conversion and equipment parallel control device provided by the embodiment of the invention realizes the conversion of the LPC protocol and the equipment expansion card based on the programmable logic device, converts PCI/PCIe bus signals into multipath LPC bus signals by using 1 PCI/PCIe physical slot, and can control a plurality of LPC equipment to work in parallel. Therefore, the limitation of the prior art can be overcome, the compatibility of the server main board to the LPC equipment is realized, the use of the LPC equipment with an LPC interface can be met, and the safety and the efficiency of the system are improved.

In a specific embodiment, an external interface is further arranged on the board card to realize connection with external equipment, and specifically comprises a PCI/PCIe physical bus interface, an LPC equipment interface and a JATG/AS interface.

The PCI/PCIe physical bus interface is connected to a signal line corresponding to the PCI/PCIE protocol IP core of the programmable logic device, and is used for connecting the PCI/PCIE protocol IP core to the PCI/PCIE bus.

The LPC device interfaces are N and are used for connecting LPC control logic to external LPC devices.

The JATG/AS interface is a debugging/downloading interface of the program and is used for debugging and downloading the program of the programmable logic device.

In specific implementation, a power module is further arranged on the board to provide working voltages for each module on the board, for example, 3.3V, 2.5V, 1.2V, etc.

The programmable logic device may be an FPGA, and the data buffer area on the FPGA may be a RAM (random access memory) or a FIFO (first-in first-out stack).

Based on the above embodiment, fig. 4 is a schematic structural diagram of a specific embodiment, in which an FPGA uses Intel Cyclone IV series chips, PCIe protocol hardware IP cores are integrated on the chip, a data buffer area uses RAM, a clock control module converts a 100MHz clock frequency of a Local end into a 33MHz clock for use by an LPC device, and the LPC device is a TCM/TPM. Therefore, the problem that multiple LPC devices cannot be used due to the fact that the main board does not have a PCI bus is solved.

FIG. 5 is a schematic structural diagram of an LPC bus protocol conversion and device parallel control device according to an embodiment of the present invention, including a BMC, on which LPC control logic is provided, the BMC being connected to an external LPC device through the LPC control logic; the BMC sends the data and the control signals to the LPC control logic, the LPC control logic realizes an LPC bus protocol, converts the received data and control signals into LPC bus signals, drives external LPC equipment to work, and realizes the active control of the BMC on the external LPC equipment.

The LPC bus protocol conversion and device parallel control device provided in this embodiment, by transplanting the LPC control logic in the above embodiment into the BMC, can realize the Master mode of the LPC protocol, and realize the active control of the BMC on external LPC devices such as TCM, thereby overcoming the defect in FIG. 2.

The embodiment of the LPC bus protocol conversion and equipment parallel control device is described in detail above, and based on the LPC bus protocol conversion and equipment parallel control device described in the above embodiment, the embodiment of the invention also provides an LPC bus protocol conversion and equipment parallel control method corresponding to the device.

The embodiment of the invention provides an LPC bus protocol conversion and equipment parallel control method, fig. 6 is a schematic diagram of the method, an upper computer sends data to a board card, a main control state machine processes local signals, the data are grouped, then the main control state machine selects any several LPC control logics (such as 8 LPC control logics, 1-8 LPC control logics are selected) according to the need, sends the data and control signals, then the main control state machine enters a waiting state, judges whether the LPC control logics finish the reading of LPC equipment, waits if the LPC control logics finish the reading of the LPC equipment, and sends the data group packet to the upper computer after the data group packet is read from the LPC control logics if the LPC control logic finish the reading of the LPC equipment does not finish the LPC equipment.

The method is specifically described below, and specifically includes the following steps.

S101, the upper computer sends the data to be processed to the board card through the PCI/PCIE bus.

S102, the PCI/PCIE protocol IP core on the board converts the physical PCI/PCIE bus signal into a local end signal, and stores the M-bit data signal of the local end into a data buffer area.

S103, dividing local end data signals in the data buffer area into N groups by a main control state machine, wherein each group is 4 bits; where N4 = M.

S104, the master control state machine gates at least one LPC control logic and sends corresponding packet data to each gated LPC control logic.

The master control state machine of the board card processes the local end signal, converts the local end signal of PCI/PCIe into the relevant control signal of LPC control logic, and transmits the data signal to each gated LPC device after grouping, for example, each 32bit data signal is divided into 8 groups, and each group is 4 bits.

It should be noted that, the master control state machine selects the LPC control logic, and may simultaneously select any several of the N sets of LPC control logic.

The master state machine sets control signals to send data packets to each of the selected LPC control logic.

Then the main control state machine enters a waiting state, at the moment, the LPC control logic converts the LPC protocol and controls the working of the LPC equipment

S105, each gating LPC control logic converts the received packet data and control signals into LPC bus signals to drive the LPC equipment to work.

S106, after finishing the reading operation of the LPC device data, the LPC control logic informs the master control state machine to read the data, and the master control state machine stores the read data into the data buffer area.

S107, after the master control state machine reads the data from all the strobe LPC control logics, the master control state machine combines the 4-bit data of all the LPC control logics into M-bit data and sends the M-bit data to the upper computer through the PCI/PCIE bus.

For example, the master control state machine reads data from the corresponding LPC control logic, combines the data with the width of 4 bits of each LPC control logic into 32 bits, and sequentially stores the 32 bits in the buffer. For the LPC control logic that was not selected in step 104, the corresponding position of its 4bit data in the combined 32bit data may be set to "0000".

In order to further understand the present invention, the functional pins and connection relationships of the master state machine and the LPC control logic are described below, and fig. 7 is a schematic diagram of the connection relationships of the master state machine and the LPC control logic.

And (3) a main control state machine: the function is to communicate with Local signals of PCI/PCIe bus IP core and interact with LPC control logic, the main signals are as follows:

CLK: a clock output signal generating a 33MHz clock frequency as a clock input to the LPC control logic;

data_in [31..0]: the 32bit data output signal is in a bus multiplexing mode and comprises data types in 3 formats of command, data and address;

LRESET: a reset signal, active low, connected to the reset input port lreset_in of the LPC control logic;

LFRAME: indicating the start of a bus cycle, active low, connected to the input port lframe_in of the LPC control logic;

IO_R_W: a read-write control signal, the high level representing a write operation, i.e., data is transmitted from the LPC control logic to the LPC device; the low level represents a read operation and data is transferred by the LPC device to the LPC control logic;

CS [7..0]: an 8-bit chip select signal, wherein a high level represents selecting a corresponding LPC control logic, for example CS [0] =1 represents selecting a first LPC control logic to control the operation of an LPC device; CS 0=0 indicates that the LPC control logic is not active;

data_out [31..0]:32 bit Data input signal, i.e. Data is input by LPC control logic to the master state machine;

the Ready [7..0]: 8bit complete signal, active high, indicates that the corresponding LPC control logic has completed the read operation of LPC device data, the master control state machine can read the data of the LPC control logic, for example, ready [0] = 1 indicates that the data of the 1 st LPC device has been read by the LPC control logic, the master control state machine can read the data from the LPC control logic; ready [0] =0 means that the 1 st LPC control logic is temporarily not finished reading the LPC device, and the master control state machine needs to wait.

LPC control logic: for N groups, the functions of each group are the same, 1 LPC device is controlled by the logic of the internal state machine, and the LPC bus time sequence is output according to the data and signals sent by the main control state machine, so that the external LPC device is driven to work, and the main signals are as follows:

lclk_in: a clock signal connected to 33MHz and output to a clock signal line LCLK of an external LPC device as an operation clock of the LPC device;

data_in [3..0]: a 4-bit data input signal connected to the data bit corresponding to the master control state machine and outputting to a bidirectional data/address bus LAD [3..0] of the external LPC device;

lreset_in: a reset signal, LRESET, connected to the reset signal of the LPC device;

lframe_in: bus cycle start signal, LFRAME connected to LPC device:

IO_R_W: a read-write control signal, wherein a high level represents IO write operation, and data is written into the LPC device; the low level indicates an IO read operation, reading data from the LPC device;

CS: chip select signal, LPC control logic works normally when CS=1, LPC control logic does not work when CS=0;

data_out [3..0]: 4bit Data output signal, read Data by LAD [3..0] bus of external LPC equipment, then transmit to data_out [3..0], and return to master control state machine;

ready: data Ready completion flag bit, ready=1 indicates that reading of LPC device data has been completed, ready=0 indicates that data reading has not been completed.

The LPC control logic realizes the writing and reading operations to the LPC device through a writing operation state machine and a reading operation state machine respectively, and fig. 8 is a schematic diagram of the writing operation state machine of the LPC control logic, and fig. 9 is a schematic diagram of the reading operation state machine of the LPC control logic. The following describes the implementation of the LPC control logic state machine by taking the write operation and the read operation of one bus transmission cycle in the manner of the LPC bus protocol IO, respectively.

As shown in fig. 8, the write operation state machine includes IDLE (IDLE), START (START), transfer TYPE (cyc_type), write address (wr_addr), write DATA (wr_data), control right transition (wr_tar), write wait (wr_sync), and end (final_tar) states, and the transition relationships among the states are as follows:

1) Entering an IDLE state after the system is reset, and entering a START state when the reset is finished and bus transmission signals are valid, namely lreset_in=1 and lframe_in=0;

2) In the START state, after 1 clock cycle, the state machine transmits data "0000" to the LAD bus of the LPC device, indicating the START of transmission, and then enters the cyc_type state;

3) In the cyc_type state, after 1 clock cycle, the state of io_r_w (which has been set to io_r_w=1 by the master state machine at this time) is transferred to the LAD bus of the LPC device, representing the IO write operation TYPE, and then the wr_addr state is entered;

4) In the WR_ADDR state, 4 clock periods are passed, the state machine transmits 4-bit addresses to the LAD bus of the LPC device, namely the LPC device receives 16-bit addresses, and then enters the WR_DATA state;

5) In the WR_DATA state, 2 clock periods are passed, the state machine transmits 2 4-bit DATA to the LAD bus of the LPC device, namely the LPC device receives 8-bit DATA, and then enters the WR_TAR state;

6) In wr_tar state, after 2 clock cycles, the state machine transmits "1111" to the LAD bus of the LPC device, representing that control of the bus is given to the LPC device, and then enters into a waiting state wr_sync;

7) In the WR_SYNC state, the state machine waits for the completion of the LPC device operation, monitors the LAD bus of the state machine, and when LAD=0000, the state machine represents that the LPC device completes the operation, and then enters the FINAL_TAR state;

8) In the final_tar state, the LPC device passes control back to the state machine over 2 clock cycles, after which it returns to the IDLE state.

Thus, the IO write operation of 1 bus cycle is completed.

As shown in fig. 9, the read operation state machine includes IDLE (IDLE), START (START), transfer TYPE (cyc_type), read address (rd_addr), control right transition (rd_tar), read wait (rd_sync), read DATA (rd_data), and end (final_tar) states, and the transition relationships among the states are as follows:

3) In the cyc_type state, after 1 clock cycle, the state of io_r_w (which has been set to io_r_w=0 by the master state machine at this time) is transferred to the LAD bus of the LPC device, representing the IO read operation TYPE, and then enters the rd_addr state;

4) In the RD_ADDR state, after 4 clock cycles, the state machine reads 4bit addresses from the LAD bus of the LPC device, namely reads the 16bit address of the LPC device, and then enters the RD_TAR state;

5) In the rd_tar state, after 2 clock cycles, the state machine transmits "1111" to the LAD of the LPC device, which represents that control of the bus is given to the LPC device, and then enters the wait state rd_sync;

6) In the rd_sync state, the state machine waits for the DATA of the LPC device to be ready, monitors its LAD bus, and when lad=0000, represents that the LPC device is ready to complete the DATA, and then enters the rd_data state;

7) In the RD_DATA state, after 2 clock cycles, the state machine reads 2 4-bit DATA from the LAD bus of the LPC device, and then enters the FINAL_TAR state;

8) In the final_tar state, the LPC device passes control back to the state machine over 2 clock cycles, and the state machine sets ready=1, after which it returns to the IDLE state.

Thus, the IO read operation of 1 bus cycle is completed.

The foregoing disclosure is merely illustrative of the preferred embodiments of the invention and the invention is not limited thereto, since modifications and variations may be made by those skilled in the art without departing from the principles of the invention.

Claims

1. The LPC bus protocol conversion and equipment parallel control device is characterized by comprising a board card, wherein a programmable logic device is arranged on the board card, and the programmable logic device is provided with a master control state machine, a data buffer area, a PCI/PCIE protocol IP core, a clock control module and N LPC control logics;

PCI/PCIE protocol IP core: the PCI/PCIE bus is connected with the PCI/PCIE bus, the physical PCI/PCIE signal is converted into a local end signal, and the M-bit data signal of the local end is stored in the data buffer area; wherein m=n×4;

data buffer area: caching the data;

2. The LPC bus protocol conversion and equipment parallel control device according to claim 1, wherein an external interface is further arranged on the board card, and comprises a PCI/PCIe physical bus interface, an LPC equipment interface and a JATG/AS interface;

3. The LPC bus protocol conversion and equipment parallel control apparatus of claim 2 wherein a power module is also provided on the board to provide operating voltage for each module on the board.

4. The LPC bus protocol conversion and device parallel control apparatus as defined in claim 1, 2 or 3, wherein the programmable logic device is an FPGA.

5. The LPC bus protocol conversion and device parallel control apparatus as defined in claim 1, 2 or 3, wherein the data buffer is a random access memory or a fifo.

6. The LPC bus protocol conversion and equipment parallel control device is characterized by comprising a BMC, wherein the BMC is provided with an LPC control logic, and is connected with external LPC equipment through the LPC control logic;

7. An LPC bus protocol conversion and device parallel control method based on the apparatus of any of claims 1-5, comprising the steps of:

8. The method according to claim 7, wherein when the 4-bit data of all the LPC control logic is combined into M-bit data, the corresponding position of the 4-bit data of the ungated LPC control logic in the combined M-bit data is set to "0000".

9. The method for parallel control of LPC bus protocol conversion and device according to claim 8, wherein the LPC control logic drives the LPC device by a write operation state machine of the LPC control logic;

the transition flow between states comprises the following steps of:

10. The method for LPC bus protocol conversion and device parallel control according to claim 9, wherein the read operation of the LPC control logic to the LPC device data is implemented by a read operation state machine of the LPC control logic;