CN114650019B - Amplifier circuit with arbitrary gain temperature coefficient - Google Patents

Amplifier circuit with arbitrary gain temperature coefficient Download PDF

Info

Publication number
CN114650019B
CN114650019B CN202210546448.8A CN202210546448A CN114650019B CN 114650019 B CN114650019 B CN 114650019B CN 202210546448 A CN202210546448 A CN 202210546448A CN 114650019 B CN114650019 B CN 114650019B
Authority
CN
China
Prior art keywords
transistor
temperature coefficient
source
circuit
transconductance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210546448.8A
Other languages
Chinese (zh)
Other versions
CN114650019A (en
Inventor
丁川
姜丹丹
叶松
陶健
马文英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Iridium Communications Co ltd
Original Assignee
Chengdu Iridium Communications Co ltd
Chengdu University of Information Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Iridium Communications Co ltd, Chengdu University of Information Technology filed Critical Chengdu Iridium Communications Co ltd
Priority to CN202210546448.8A priority Critical patent/CN114650019B/en
Publication of CN114650019A publication Critical patent/CN114650019A/en
Application granted granted Critical
Publication of CN114650019B publication Critical patent/CN114650019B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses an amplifier circuit with any gain temperature coefficient, which comprises a transconductance generating circuit and a signal amplifierThe transconductance generating circuit is respectively connected with the signal amplifier circuit and the bias circuit and is used for respectively providing bias voltage for the signal amplifier circuit and the bias circuit; the bias circuit is used for providing bias voltage for the amplifier circuit. By the mode, the current temperature coefficient TC of the invention can be adjusted by adjusting the positive temperature coefficient p 、TC n Constant bias current I 0p 、I 0n Coefficient of proportionality k 1 、k 2 To realize the arbitrary adjustment of the temperature coefficient of the gain of the amplifier.

Description

Amplifier circuit with arbitrary gain temperature coefficient
Technical Field
The invention relates to the field of amplifier circuits, in particular to an amplifier circuit with any gain temperature coefficient.
Background
The conventional amplifier circuit structure is shown in fig. 5, and includes a coupling capacitor CC, a bias resistor Rb, an amplifying transistor M1, and a load resistor RL. The signal is input from the Vin end, output from the Vo end, and Vb provides bias voltage for the amplifying transistor.
The gain of a conventional amplifier is:
Figure 50856DEST_PATH_IMAGE002
Figure 806322DEST_PATH_IMAGE004
wherein gm is the transconductance of the amplifying transistor, un is the electron mobility, Cox is the thickness of the gate oxide layer of the transistor, W is the communication width of the transistor, L is the channel length of the transistor, ID is the drain current of the transistor, and RL is the load resistance.
Due to the large variation of electron mobility and transistor drain current with temperature. In addition, in different processes, under different bias voltages, the relationship between the electron mobility and the drain current along with the temperature change is different, so that the gain of the traditional amplifier circuit along with the temperature change is large, the gain temperature coefficient is uncertain, and the circuit performance is uncertain.
On the other hand, a temperature gain compensation circuit is usually required in the circuit system to compensate for the gain fluctuation of other circuits due to temperature change. And different system gains are different along with temperature fluctuation states, so that the amplifier with the arbitrarily adjustable gain temperature coefficient has wide and important application value.
Disclosure of Invention
In view of the above-mentioned deficiencies in the prior art, the present invention provides an amplifier circuit with an arbitrary gain temperature coefficient.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
an arbitrary gain temperature coefficient amplifier circuit comprises a transconductance generating circuit, a signal amplifier circuit and a bias circuit,
the transconductance generating circuit is respectively connected with the signal amplifier circuit and the bias circuit and is used for respectively providing bias voltage for the signal amplifier circuit and the bias circuit; the bias circuit is used for providing bias voltage for the amplifier circuit.
Further, the signal amplifier circuit comprises a coupling capacitor Cc and a bias resistor R b A signal amplifying transistor M1 and a load transistor M2, wherein one end of the coupling capacitor Cc is connected to the gate of the amplifying transistor M1, and the other end is connected to the input voltage signal; the bias resistor R b One end of the second resistor is connected with the grid electrode of the amplifying transistor M1, and the other end of the second resistor is connected with the output end of the transconductance generating circuit; the source electrode of the amplifying transistor M1 is grounded, and the drain electrode is connected with the drain electrode of the load transistor M2; the gate and source of the load transistor M2 are connected to the bias circuit.
Further, the bias circuit includes a transistor M b1 Transistor M b2 Transistor M b3 Transistor M b4 Wherein the transistor M b1 And a transistor M b4 Is connected to the transconductance generating circuit, the transistor M b4 Is grounded and has a drain connected to the transistor M b3 A source electrode of (a); the transistor M b1 Is grounded and has a drain connected to the transistor M b2 A source electrode of (a); the transistor M b1 And a transistor M b2 Are connected to the gate of the load transistor M2, and transistor M is connected to the drain of the load transistor M2 b2 Are interconnected with the source.
Further, the transconductance generating circuit comprises a positive temperature coefficient transconductance generating circuit and a negative temperature coefficient transconductance generating circuit, wherein when the negative temperature coefficient transconductance generating circuit is connected with the transistor M b4 A positive temperature coefficient transconductance generating circuit is connected with the transistor M b1 When the temperature coefficient amplifier circuit is used, the arbitrary gain temperature coefficient amplifier circuit generates positive temperature coefficient amplification output; when the PTC transconductance generating circuit is connected with the transistor M b1 A negative temperature coefficient transconductance generating circuit connected to the transistor M b4 And when the temperature coefficient amplifier circuit with any gain generates the negative temperature coefficient amplification output.
Further, the negative temperature coefficient transconductance generating circuit comprises a transistor M3, a transistor M4, a transistor M5, a transistor M6, a first error amplifier EA1, and a first drain voltage resistor R 1n A first positive temperature coefficient current source I PTATn A first constant current source I 0n The gates and the drains of the transistor M4 and the transistor M5 are interconnected, and the sources of the transistors are connected with a system voltage VCC; the gates of the transistor M4 and the transistor M5 are connected to the output terminal of the first error amplifier EA 1; the source of the transistor M5 is connected to a comparison terminal of the first error amplifier EA1 and to ground via the transistor M3; the drain and the gate of the transistor M3 are interconnected, and the drain is connected with the source of the transistor M5; the source of transistor M3 is connected to ground; the source of the transistor M6 is connected to the other comparison terminal of the first error amplifier EA1 and to ground through the transistor M4; the source of transistor M4 is connected to ground,the drain electrode is connected with the source electrode of the transistor M6, and the gate electrode is the output V of the negative temperature coefficient transconductance generating circuit b_neg (ii) a The source electrode of the transistor M6 also passes through a drain voltage resistor R in turn 1n And a first positive temperature coefficient current source I PTATn The series circuit of (1) is grounded; the source of the transistor M6 is also connected to a first constant current source I 0n Grounding; the transistor M3 and the transistor M4 are the same size, and the transistors M5 and M6 are the same size.
Further, the positive temperature coefficient transconductance generating circuit comprises a transistor M7, a transistor M8, a transistor M9, a transistor M10, a second error amplifier EA2 and a second drain voltage resistor R 1p A second constant current source I 0p A second positive temperature coefficient current source I PTATp The gates and the drains of the transistor M9 and the transistor M10 are interconnected, and the sources of the transistors are connected with a system voltage VCC; the gates of the transistor M9 and the transistor M10 are connected to the output terminal of the second error amplifier EA 2; the source of the transistor M9 is connected to a comparison terminal of the second error amplifier EA2 and to ground via the transistor M7; the drain and the gate of the transistor M7 are interconnected, and the drain is connected with the source of the transistor M9; the source of transistor M7 is connected to ground; the source of the transistor M10 is connected to the other comparison terminal of the second error amplifier EA2 and to ground through the transistor M8; the source of the transistor M8 is grounded, the drain is connected with the source of the transistor M10, and the gate is the output V of the negative temperature coefficient transconductance generating circuit b_pos (ii) a The source electrode of the transistor M10 also passes through a second drain voltage resistor R in turn 1p And a second constant current source I 0p The series circuit of (1) is grounded; the source of the transistor M10 is also connected with a second positive temperature coefficient current source I PTATp Grounding; the transistor M7 and the transistor M8 are the same size, and the transistor M9 and the transistor M10 are the same size.
Further, when the arbitrary gain temperature coefficient amplifier circuit generates a positive temperature coefficient amplification output, the output gain is:
Figure 398977DEST_PATH_IMAGE006
wherein,
Figure DEST_PATH_IMAGE007
is the size ratio of the transistor M1 to the transistor M8;
Figure 480066DEST_PATH_IMAGE008
is a transistor M b4 In proportion to the size of the transistor M8,
Figure DEST_PATH_IMAGE009
is a first positive temperature coefficient current source I PTATn The magnitude of the current generated is such that,
Figure 423751DEST_PATH_IMAGE010
is a second positive temperature coefficient current source I PTATp The magnitude of the current generated is such that,
Figure DEST_PATH_IMAGE011
is a first drain voltage resistor R 1n The resistance value of (1);
Figure 779646DEST_PATH_IMAGE012
is the second drain voltage resistor R 1p Resistance value;
Figure 695650DEST_PATH_IMAGE014
the current value of the second constant current source;
Figure 682060DEST_PATH_IMAGE016
the current value of the first constant current source.
Further, when the arbitrary gain temperature coefficient amplifier circuit generates a negative temperature coefficient amplified output, the output gain is:
Figure 316304DEST_PATH_IMAGE018
wherein, among others,
Figure 413573DEST_PATH_IMAGE007
ruler for transistor M1 and transistor M8Cun ratio;
Figure 511979DEST_PATH_IMAGE008
is a transistor M b4 In proportion to the size of the transistor M8,
Figure 606974DEST_PATH_IMAGE009
as a positive temperature coefficient current source I PTATn The magnitude of the current generated is such that,
Figure 790830DEST_PATH_IMAGE010
is a second positive temperature coefficient current source I PTATp The magnitude of the current generated is such that,
Figure 895053DEST_PATH_IMAGE011
is a first drain voltage resistor R 1n The resistance value of (1);
Figure 316807DEST_PATH_IMAGE012
is the second drain voltage resistor R 1p Resistance value;
Figure DEST_PATH_IMAGE019
the invention has the following beneficial effects:
the amplifier circuit with any gain temperature coefficient has the function of adjusting the gain temperature coefficient randomly and accurately, can make up the defect that the gain of the traditional amplifier is uncertain along with the temperature fluctuation, and can be used for compensating the negative influence of the gain of other circuits in a system along with the temperature fluctuation, thereby improving the reliability of the whole system.
Drawings
Fig. 1 is a schematic diagram of a negative temperature coefficient transconductance generating circuit according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a positive temperature coefficient transconductance generating circuit according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a positive temperature coefficient amplifier circuit according to an embodiment of the invention.
FIG. 4 is a schematic diagram of a negative temperature coefficient amplifier according to an embodiment of the invention.
Fig. 5 is a circuit diagram of a conventional amplifier in the prior art.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
An arbitrary gain temperature coefficient amplifier circuit comprises a transconductance generating circuit, a signal amplifier circuit and a bias circuit,
the transconductance generating circuit is respectively connected with the signal amplifier circuit and the bias circuit and is used for respectively providing bias voltage for the signal amplifier circuit and the bias circuit; the bias circuit is used for providing bias voltage for the amplifier circuit.
Specifically, as shown in fig. 1, the negative temperature coefficient transconductance generating circuit includes a transistor M3, a transistor M4, a transistor M5, a transistor M6, a first error amplifier EA1, and a first drain voltage resistor R 1n A first positive temperature coefficient current source I PTATn A first constant current source I 0n The grid electrodes and the drain electrodes of the transistor M4 and the transistor M5 are mutually connected, and the source electrodes of the transistors are connected with a system voltage VCC; the gates of the transistor M4 and the transistor M5 are connected to the output terminal of the first error amplifier EA 1; the source of the transistor M5 is connected to a comparison terminal of the first error amplifier EA1 and to ground via the transistor M3; the drain and the gate of the transistor M3 are interconnected, and the drain is connected with the source of the transistor M5; the source of transistor M3 is grounded; the source of the transistor M6 is connected to the other comparison terminal of the first error amplifier EA1 and to ground through the transistor M4; the source of the transistor M4 is grounded, the drain is connected with the source of the transistor M6, and the gate is the output V of the negative temperature coefficient transconductance generating circuit b_neg (ii) a The source electrode of the transistor M6 also passes through a drain voltage resistor R in turn 1n And a first positive temperature coefficient current source I PTATn In the clusterThe connecting circuit is grounded; the source of the transistor M6 is also connected to a first constant current source I on Grounding; the transistor M3 and the transistor M4 are the same size, and the transistors M5 and M6 are the same size.
Transistor M in FIG. 1 3 /M 4 Having the same size, M 5 /M 6 Have the same dimensions. The negative feedback loop passes M through the error amplifier EA 3 Drain voltage and M 4 The drain voltages are clamped to be equal. Because M is 3 Gate and drain voltages being equal, M 4 Gate lower than drain voltage by resistance R 1n Voltage difference of (I) PTATn *R 1n (ii) a On the other hand, M 5 And M 6 Having the same drain current, M 3 Drain current and M 5 Same, M 4 Drain current, bias current I PTATn Bias current I 0n -I PTATn The sum being equal to M 6 Drain current, therefore M 3 And M 4 Has a drain current difference of I PTATn +I 0n -I PTATn I.e. I 0n . In which I PTATn Is a positive temperature coefficient current, I 0n Is a constant current. Thus, M 4 May be approximated as M 3 And M 4 Ratio of drain current difference to gate voltage difference, i.e. I 0n /(I PTATn *R 1n ). Due to I PTATn Has a positive temperature coefficient, so that the transconductance thereof has a negative temperature coefficient.
The positive temperature coefficient transconductance generating circuit comprises a transistor M7, a transistor M8, a transistor M9, a transistor M10, a second error amplifier EA2 and a second drain voltage resistor R 1p A second constant current source I 0p A second positive temperature coefficient current source I PTATp The gates and the drains of the transistor M9 and the transistor M10 are interconnected, and the sources of the transistors are connected with a system voltage VCC; the gates of the transistor M9 and the transistor M10 are connected to the output terminal of the second error amplifier EA 2; the source of the transistor M9 is connected to a comparison terminal of the second error amplifier EA2 and to ground via the transistor M7; the drain and the gate of the transistor M7 are interconnected, and the drain is connected with the source of the transistor M9; the source of transistor M7 is grounded; the source of transistor M10 is connected to the second errorThe other comparison terminal of the difference amplifier EA2 is connected to ground through a transistor M8; the source of the transistor M8 is grounded, the drain is connected with the source of the transistor M10, and the gate is the output V of the negative temperature coefficient transconductance generating circuit b_pos (ii) a The source electrode of the transistor M10 also passes through a second drain voltage resistor R in turn 1p And a second constant current source I 0p The series circuit of (a) is grounded; the source of the transistor M10 is also connected with a second positive temperature coefficient current source I PTATp Grounding; the transistor M7 and the transistor M8 are the same size, and the transistor M9 and the transistor M10 are the same size.
As shown in fig. 2, the transistor M 7 /M 8 Having the same size, M 9 /M 10 Have the same dimensions. The negative feedback loop passes M through the error amplifier EA 1 Drain voltage and M 2 The drain voltages are clamped to be equal. Because M is 7 Gate and drain voltages being equal, M 8 Gate lower than drain voltage by resistance R 1p Voltage difference of (I) 0p *R 1p (ii) a On the other hand, M 9 And M 10 Having the same drain current, M 7 Drain current and M 9 Same, M 8 Drain current, bias current I 0p Bias current I PTATp -I 0p The sum being equal to M 10 Drain current, therefore M 7 And M 8 Has a drain current difference of I 0p +I PTATp -I 0p I.e. I PTATp . In which I PTATp Is a positive temperature coefficient current, I 0p Is a constant current. Thus, M 2 May be approximated as M 7 And M 8 Ratio of drain current difference to gate voltage difference, i.e. I PTATp /(I 0p *R 1p ). Due to I PTATp Has a positive temperature coefficient, so that the transconductance thereof has a negative temperature coefficient.
The signal amplifier circuit includes a coupling capacitor Cc and a bias resistor R as shown in FIG. 3 or FIG. 4 b A signal amplifying transistor M1 and a load transistor M2, wherein one end of the coupling capacitor Cc is connected to the gate of the amplifying transistor M1, and the other end is connected to the input voltage signal; the bias resistor R b Is connected to the amplifying transistor M1The other end of the grid is connected with the output end of the transconductance generating circuit; the source electrode of the amplifying transistor M1 is grounded, and the drain electrode is connected with the drain electrode of the load transistor M2; the gate and source of the load transistor M2 are connected to the bias circuit.
The bias circuit comprises a transistor M b1 Transistor M b2 Transistor M b3 Transistor M b4 Wherein the transistor M b1 And a transistor M b4 Is connected to the transconductance generating circuit, the transistor M b4 Is grounded and has a drain connected to the transistor M b3 A source electrode of (a); the transistor M b1 Is grounded and has a drain connected to the transistor M b2 A source electrode of (a); the transistor M b1 And a transistor M b2 Has drains connected to the gate of the load transistor M2, and a transistor M b2 Are interconnected with the source.
The transconductance generating circuit comprises a positive temperature coefficient transconductance generating circuit and a negative temperature coefficient transconductance generating circuit, wherein when the negative temperature coefficient transconductance generating circuit is connected with the transistor M b4 A positive temperature coefficient transconductance generating circuit is connected with the transistor M b1 When the temperature coefficient amplifier circuit is used, the arbitrary gain temperature coefficient amplifier circuit generates positive temperature coefficient amplification output; when the PTC transconductance generating circuit is connected with the transistor M b1 A negative temperature coefficient transconductance generating circuit connected to the transistor M b4 And when the temperature coefficient amplifier circuit with any gain generates the negative temperature coefficient amplification output.
As shown in fig. 3, the signal amplifier part is composed of a signal coupling capacitor C C Bias resistor R b Transistor M for signal amplification 1 Load transistor M 2 Is composed of a bias circuit part consisting of M b1 、M b2 、M b3 、M b4 And (4) forming. Wherein M is 1 The bias voltage is generated by a positive temperature coefficient transconductance generating circuit, in which the amplifier circuit is M 1 M in the positive temperature coefficient transconductance generating circuit 2 Dimension ratio of k 1 (ii) a M in bias circuit b1 Bias voltage of (2) from positive temperatureA degree-coefficient transconductance generation circuit provides b1 Size and positive temperature coefficient transconductance generating circuit 2 Is also k 1 (ii) a M in bias circuit b4 Is provided by a negative temperature coefficient transconductance generating circuit, M b4 The size ratio of M2 in the PTC transconductance generating circuit is also k 2 . Furthermore M b2 And M b3 Having the same size, load transistors M 2 M in the negative temperature coefficient generation circuit 2 The size ratio is also k 2 . In the amplifying circuit shown in fig. 3, the amplifying transistor M 1 The current being derived from a bias voltage V b_pos Determining M in a PTC transconductance generating circuit 2 Current ratio of k 1 Then amplifying transistor M 1 M in transconductance generation circuit with positive temperature coefficient transconductance 2 K of transconductance 1 Doubling; negative carrier tube M 2 The current being derived from a bias voltage V b_neg Determining M in a negative temperature coefficient transconductance generating circuit 2 Current ratio of k 2 Then the carrier tube M is supported 2 Transconductance is M in a negative temperature coefficient transconductance generating circuit 2 K of transconductance 2 And (4) doubling. Therefore, when the arbitrary gain temperature coefficient amplifier circuit generates a positive temperature coefficient amplification output, the output gain is:
Figure 645020DEST_PATH_IMAGE006
wherein,
Figure 380672DEST_PATH_IMAGE007
is the size ratio of the transistor M1 to the transistor M8;
Figure 288585DEST_PATH_IMAGE008
is a transistor M b4 In proportion to the size of the transistor M8,
Figure 830424DEST_PATH_IMAGE009
is a first positive temperature coefficient current source I PTATn The magnitude of the current generated is such that,
Figure 595118DEST_PATH_IMAGE010
is a second positive temperature coefficient current source I PTATp The magnitude of the current generated is such that,
Figure 425671DEST_PATH_IMAGE011
is a first drain voltage resistor R 1n The resistance value of (1);
Figure 934013DEST_PATH_IMAGE012
is the second drain voltage resistor R 1p Resistance value;
Figure 533621DEST_PATH_IMAGE014
the current value of the second constant current source;
Figure 469216DEST_PATH_IMAGE016
the current value of the first constant current source.
If I PTATp Has a temperature coefficient of TC p ,I PATAn Has a temperature coefficient of TC n The temperature coefficient of the amplifier gain is
Figure DEST_PATH_IMAGE021
Therefore, the temperature coefficient TC of the current can be adjusted by adjusting the positive temperature coefficient p 、TC n Constant bias current I 0p 、I 0n Coefficient of proportionality k 1 、k 2 The temperature coefficient of the amplifier is adjusted.
If V in FIG. 3 is exchanged b_pos And V b_neg The negative temperature coefficient gain can be obtained by the connection relation of (3), as shown in fig. 4, when the arbitrary gain temperature coefficient amplifier circuit generates the negative temperature coefficient amplified output, the output gain is:
Figure 318224DEST_PATH_IMAGE018
wherein, in the process,
Figure 364677DEST_PATH_IMAGE007
is the size ratio of the transistor M1 to the transistor M8;
Figure 84371DEST_PATH_IMAGE008
is a transistor M b4 In proportion to the size of the transistor M8,
Figure 190868DEST_PATH_IMAGE009
is a positive temperature coefficient current source I PTATn The magnitude of the current generated is such that,
Figure 792750DEST_PATH_IMAGE010
is a second positive temperature coefficient current source I PTATp The magnitude of the current generated is such that,
Figure 580578DEST_PATH_IMAGE011
is a first drain voltage resistor R 1n The resistance value of (1);
Figure 217095DEST_PATH_IMAGE012
is the second drain voltage resistor R 1p Resistance value;
Figure 432176DEST_PATH_IMAGE014
the current value of the second constant current source;
Figure 521355DEST_PATH_IMAGE016
the current value of the first constant current source.
The temperature coefficient is negative, and the current temperature coefficient TC can be adjusted by adjusting the positive temperature coefficient p 、TC n Constant bias current I 0p 、I 0n Coefficient of proportionality k 1 、k 2 The temperature coefficient of the amplifier is adjusted.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (6)

1. An arbitrary gain temperature coefficient amplifier circuit, comprising a transconductance generating circuit, a signal amplifier circuit, and a bias circuit, wherein,
the bias circuit is used for providing bias voltage for the signal amplifier circuit, wherein the bias circuit comprises a transistor M b1 Transistor M b2 Transistor M b3 Transistor M b4 Wherein the transistor M b1 And a transistor M b4 Is connected to the transconductance generating circuit, the transistor M b4 Is grounded and has a drain connected to the transistor M b3 A source electrode of (a); the transistor M b1 Is grounded and has a drain connected to the transistor M b2 A source electrode of (a); the transistor M b1 And a transistor M b2 Is connected to the signal amplifier circuit, and a transistor M b2 The grid electrode and the source electrode are interconnected;
the transconductance generating circuit is respectively connected with the signal amplifier circuit and the bias circuit and is used for respectively providing bias voltage for the signal amplifier circuit and the bias circuit, wherein the transconductance generating circuit comprises a positive temperature coefficient transconductance generating circuit and a negative temperature coefficient transconductance generating circuit, and when the negative temperature coefficient transconductance generating circuit is connected with the transistor M b4 A positive temperature coefficient transconductance generating circuit is connected with the transistor M b1 When the temperature coefficient amplifier circuit is used, the arbitrary gain temperature coefficient amplifier circuit generates positive temperature coefficient amplification output; when the positive temperature coefficientA transconductance generating circuit connected with the transistor M b1 A negative temperature coefficient transconductance generating circuit connected to the transistor M b4 And when the temperature coefficient amplifier circuit with any gain generates the negative temperature coefficient amplification output.
2. The arbitrary gain temperature coefficient amplifier circuit according to claim 1, wherein the signal amplifier circuit comprises a coupling capacitor Cc and a bias resistor R b A signal amplifying transistor M1 and a load transistor M2, wherein one end of the coupling capacitor Cc is connected to the gate of the amplifying transistor M1, and the other end is connected to the input voltage signal; the bias resistor R b One end of the second resistor is connected with the grid electrode of the amplifying transistor M1, and the other end of the second resistor is connected with the output end of the transconductance generating circuit; the source electrode of the amplifying transistor M1 is grounded, and the drain electrode is connected with the drain electrode of the load transistor M2; the gate and source of the load transistor M2 are connected to the bias circuit.
3. The amplifier circuit of claim 1, wherein the negative temperature coefficient transconductance generating circuit comprises a transistor M3, a transistor M4, a transistor M5, a transistor M6, a first error amplifier EA1, and a first drain voltage resistor R 1n A first positive temperature coefficient current source I PTATn A first constant current source I 0n The gates and the drains of the transistor M4 and the transistor M5 are interconnected, and the sources of the transistors are connected with a system voltage VCC; the gates of the transistor M4 and the transistor M5 are connected to the output terminal of the first error amplifier EA 1; the source of the transistor M5 is connected to a comparison terminal of the first error amplifier EA1 and to ground via the transistor M3; the drain and the gate of the transistor M3 are interconnected, and the drain is connected with the source of the transistor M5; the source of transistor M3 is connected to ground; the source of the transistor M6 is connected to the other comparison terminal of the first error amplifier EA1 and to ground through the transistor M4; the source of the transistor M4 is grounded, the drain is connected with the source of the transistor M6, and the gate is the output V of the negative temperature coefficient transconductance generating circuit b_neg (ii) a The source electrode of the transistor M6 also passes through a drain voltage resistor R in turn 1n And a positive temperature coefficient current source I PTATn The series circuit of (1) is grounded; the source of the transistor M6 is also grounded through a first constant current source; the transistor M3 and the transistor M4 are the same size, and the transistors M5 and M6 are the same size.
4. The amplifier circuit as claimed in claim 3, wherein the PTC transconductance generating circuit includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a second error amplifier EA2, and a second drain voltage resistor R 1p A second constant current source I 0p A second PTC current source I PTATp The gates and the drains of the transistor M9 and the transistor M10 are interconnected, and the sources of the transistors are connected with a system voltage VCC; the gates of the transistor M9 and the transistor M10 are connected to the output terminal of the second error amplifier EA 2; the source of the transistor M9 is connected to a comparison terminal of the second error amplifier EA2 and to ground via the transistor M7; the drain and the gate of the transistor M7 are interconnected, and the drain is connected with the source of the transistor M9; the source of transistor M7 is connected to ground; the source of the transistor M10 is connected to the other comparison terminal of the second error amplifier EA2 and to ground through the transistor M8; the source of the transistor M8 is grounded, the drain is connected with the source of the transistor M10, and the gate is the output V of the negative temperature coefficient transconductance generating circuit b_pos (ii) a The source electrode of the transistor M10 also passes through a second drain voltage resistor R in turn 1p And a second constant current source I 0p The series circuit of (1) is grounded; the source of the transistor M10 is also connected with a second positive temperature coefficient current source I PTATp Grounding; the transistor M7 and the transistor M8 are the same size, and the transistor M9 and the transistor M10 are the same size.
5. The temperature-coefficient of arbitrary gain amplifier circuit of claim 4, wherein when the temperature-coefficient of arbitrary gain amplifier circuit produces a positive temperature coefficient amplified output, its output gain is:
Figure FDA0003743854760000031
wherein k is 1 Is the size ratio of the transistor M1 to the transistor M8; k is a radical of 2 Is a transistor M b4 To the size of the transistor M8, I PTATn As a positive temperature coefficient current source I PTATn Magnitude of the generated current I PTATp Is a second positive temperature coefficient current source I PTATp Magnitude of the generated current, R 1n Is a first drain voltage resistor R 1n The resistance value of (1); r 1p Is the second drain voltage resistor R 1p Resistance value; I.C. A 0p The current value of the positive temperature coefficient constant current source; i is 0n The current value of the negative temperature coefficient constant current source.
6. The temperature-coefficient of arbitrary gain amplifier circuit of claim 5, wherein when the temperature-coefficient of arbitrary gain amplifier circuit produces a negative temperature-coefficient amplified output, its output gain is:
Figure FDA0003743854760000032
wherein, k is 1 Is the size ratio of the transistor M1 to the transistor M8; k is a radical of 2 Is a transistor M b4 To the size of the transistor M8, I PTATn As a positive temperature coefficient current source I PTATn Magnitude of the generated current I PTATp Is a second positive temperature coefficient current source I PTATp Magnitude of the generated current, R 1n Is a first drain voltage resistor R 1n The resistance value of (1); r 1p Is the second drain voltage resistor R 1p Resistance value; i is 0p The current value of the positive temperature coefficient constant current source; i is 0n The current value of the negative temperature coefficient constant current source.
CN202210546448.8A 2022-05-20 2022-05-20 Amplifier circuit with arbitrary gain temperature coefficient Active CN114650019B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210546448.8A CN114650019B (en) 2022-05-20 2022-05-20 Amplifier circuit with arbitrary gain temperature coefficient

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210546448.8A CN114650019B (en) 2022-05-20 2022-05-20 Amplifier circuit with arbitrary gain temperature coefficient

Publications (2)

Publication Number Publication Date
CN114650019A CN114650019A (en) 2022-06-21
CN114650019B true CN114650019B (en) 2022-09-20

Family

ID=81997592

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210546448.8A Active CN114650019B (en) 2022-05-20 2022-05-20 Amplifier circuit with arbitrary gain temperature coefficient

Country Status (1)

Country Link
CN (1) CN114650019B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109116904A (en) * 2018-09-25 2019-01-01 聚辰半导体(上海)有限公司 A kind of biasing circuit
CN112039444A (en) * 2020-11-04 2020-12-04 成都铱通科技有限公司 Gain amplifier for improving variation range of positive temperature coefficient

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2150502A1 (en) * 1994-08-05 1996-02-06 Michael F. Mattes Method and apparatus for measuring temperature
CN101043199A (en) * 2006-03-24 2007-09-26 苏州中科半导体集成技术研发中心有限公司 Voltage controlled oscillator with automatic amplitude control
CN101470458B (en) * 2007-12-26 2010-10-27 中国科学院微电子研究所 Band-gap reference voltage reference circuit
TWI470399B (en) * 2012-12-20 2015-01-21 Integrated Circuit Solution Inc Low voltage bandgap reference circuit
CN103595402B (en) * 2013-11-18 2017-05-24 四川和芯微电子股份有限公司 High-accuracy oscillator
CN112332786B (en) * 2020-10-30 2023-09-05 西南电子技术研究所(中国电子科技集团公司第十研究所) Chip-level fully-integrated low-gain temperature drift radio frequency amplifier
CN113359932B (en) * 2021-06-21 2021-12-17 东南大学 Constant transconductance biasing circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109116904A (en) * 2018-09-25 2019-01-01 聚辰半导体(上海)有限公司 A kind of biasing circuit
CN112039444A (en) * 2020-11-04 2020-12-04 成都铱通科技有限公司 Gain amplifier for improving variation range of positive temperature coefficient

Also Published As

Publication number Publication date
CN114650019A (en) 2022-06-21

Similar Documents

Publication Publication Date Title
TWI457743B (en) Bandgap reference circuit and self-referenced regulator
US7332965B2 (en) Gate leakage insensitive current mirror circuit
JPH07307624A (en) Cmos operational amplifier of low-voltage high-speed operation
US20060250185A1 (en) Linear amplifier
CN1436399A (en) Boosted high-gain, very wide common mode range, self-biased operational amplifier
TWI487262B (en) Voltage to current converting circuit
CN112039444B (en) Gain amplifier for improving variation range of positive temperature coefficient
US20110140782A1 (en) Differential Gm-Boosting Circuit and Applications
US6545502B1 (en) High frequency MOS fixed and variable gain amplifiers
US9231542B1 (en) Amplifier common-mode control method
CN114650019B (en) Amplifier circuit with arbitrary gain temperature coefficient
US8064622B1 (en) Self-biased amplifier device for an electrecret microphone
Safari et al. A simple low voltage, high output impedance resistor based current mirror with extremely low input and output voltage requirements
TWI641215B (en) Variable gain amplifier
US20050231275A1 (en) Operational amplifier
US8035448B1 (en) Differential amplifier that compensates for process variations
JPH04582Y2 (en)
JP3814256B2 (en) Cross-pair transconductor
TW201025838A (en) Operational amplifier and method for reducing offset voltage of operational amplifiers
JP2707667B2 (en) Comparison circuit
JPH10107562A (en) Variable gain amplifier
JP3655290B2 (en) Operational amplifier circuit
JPH0645844A (en) Differential amplifier
CN111431489B (en) Common mode feedback circuit and differential amplifier
Padilla-Cantoya et al. Four-quadrant multiplier using the floating-bulk technique for rail-to-rail input range and insensitivity to different input dc levels

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240112

Address after: 611730 1st floor, building 1, No. 6, Kexin Road, high tech Zone (West District), Chengdu, Sichuan

Patentee after: CHENGDU IRIDIUM COMMUNICATIONS CO.,LTD.

Address before: 610225 24 section 1 Xuefu Road, Southwest Airport Economic Development Zone, Chengdu, Sichuan

Patentee before: CHENGDU University OF INFORMATION TECHNOLOGY

Patentee before: CHENGDU IRIDIUM COMMUNICATIONS CO.,LTD.