CN114566431A - Method for etching porous organic silicate material with low damage - Google Patents

Method for etching porous organic silicate material with low damage Download PDF

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Publication number
CN114566431A
CN114566431A CN202210155688.5A CN202210155688A CN114566431A CN 114566431 A CN114566431 A CN 114566431A CN 202210155688 A CN202210155688 A CN 202210155688A CN 114566431 A CN114566431 A CN 114566431A
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CN
China
Prior art keywords
etching
organic silicate
porous organic
damage
silicate material
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CN202210155688.5A
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Chinese (zh)
Inventor
陈润泽
尚青
花莹曦
马领军
罗雪薇
姜世楠
刘宇腾
张心智
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Peric Special Gases Co Ltd
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Peric Special Gases Co Ltd
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Priority to CN202210155688.5A priority Critical patent/CN114566431A/en
Publication of CN114566431A publication Critical patent/CN114566431A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Microelectronics & Electronic Packaging (AREA)
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  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention provides a method for etching a porous organic silicate material with low damage, which comprises the following steps: placing a porous organic silicate material into an etching system, precooling the etching system to the temperature of minus 60 ℃ to minus 40 ℃, and introducing SF into the precooled etching system at the temperature of minus 60 ℃ to minus 40 DEG C6And C4F6And (3) carrying out plasma etching on the porous organic silicate material by using the mixed gas and an etching system to obtain the low-damage etched porous organic silicate material. The invention can greatly reduce the damage to the porous organic silicate material in the plasma etching process.

Description

Method for etching porous organic silicate material with low damage
Technical Field
The invention belongs to the technical field of semiconductor etching, and particularly relates to a method for etching a porous organic silicate material with low damage.
Background
In order to reduce power consumption of integrated CMOS circuits, Low-K porous organosilicate materials (OSG) are used in advanced interconnect technologies. But the dielectric property and reliability of the etching solution are degraded due to plasma damage in the etching process, so that the application capability of the etching solution is limited.
To overcome this problem, a Low temperature etching technique is applied to the etching process of Low-K porous organosilicate material (OSG). Most etching processes are at SF6Alcohol-like byproducts are formed in the plasma under the low-temperature environment (-120 ℃ to-70 ℃), and the byproducts are condensed in the porous material, so that the plasma damage in the etching process is reduced. But this process requires the ambient temperature to be reduced to a very low temperature. This means that more energy consumption is required.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method for etching a porous organosilicate material with low damage, aiming at the defects of the prior art, wherein the method can greatly reduce the damage to the porous organosilicate material in the plasma etching process.
In order to solve the technical problems, the invention adopts the technical scheme that: a method for etching a porous organosilicate material with low damage, the method comprising:
s1, placing the porous organic silicate material into an etching system, and precooling the etching system to the temperature of-60 ℃ to-40 ℃ to obtain a precooled etching system;
s2, introducing SF into the pre-cooled etching system in S1 at the temperature of-60 to-40 DEG C6And C4F6Mixed gas, and the etching system carries out plasma etching on the porous organic silicate material in S1 to obtain low-damage etched porous organic silicateA salt material.
SF in the invention6And C4F6The gas mixture can take place to condense and liquefy under low temperature environment to adhere to at the material inner wall, fill up the inside space of porous organic silicate even, form the protective layer, among the etching process, through keeping lower substrate platform temperature, the liquefied gas of condensing can protect the material always, under the effect of protective layer, plasma reduces substantially to porous organic silicate's damage, after the sculpture is accomplished, resumes substrate platform temperature to room temperature, the liquefied gas of condensing can volatilize naturally, does not have the pollution to the system.
Preferably, SF as described in S26And C4F6SF in mixed gas6The purity of the product is 99.99 to 99.999 percent, C4F6The purity of the product is 99.99-99.999%.
Preferably, SF as described in S26And C4F6SF in mixed gas6The flow rate of (C) is 20-40 sccm4F6The flow rate of (2) sccm to 6 sccm.
Preferably, the pressure of the etching system in S2 is 15mTorr to 25 mTorr.
Preferably, the etching system in S2 has an RF power of 300W-500W and a DC bias of 50W-150W.
Compared with the prior art, the invention has the following advantages:
the invention can greatly reduce the damage to the porous organic silicate material in the plasma etching process. The use of SF in the invention6And C4F6Mixed gas as etching gas, C4F6As the etching gas, the high-boiling-point etching gas has a high boiling point, can realize etching at the temperature of-60 ℃ to-40 ℃, can greatly increase the etching temperature compared with the traditional method, and does not need extremely low temperature in a system, thereby reducing the energy consumption problem of the traditional process, reducing the process difficulty and simultaneously remarkably reducing the damage of plasma etching. Furthermore, SF6Increase the density of fluorine ions and increase the etching speed, and C4F6A layer of protective layer can be formed on the side wall of the groove in the etching processAnd the film is protected, so that the transverse etching of the groove is prevented, and the etching selectivity is improved.
The present invention will be described in further detail with reference to examples.
Detailed Description
Example 1
The method for etching the porous organic silicate material with low damage in the embodiment comprises the following steps:
s1, placing the porous organic silicate material into an etching system, and precooling the etching system to-60 ℃ to obtain a precooled etching system;
s2, introducing SF into the pre-cooled etching system in S1 at the temperature of-60 DEG C6And C4F6The etching system carries out plasma etching on the porous organosilicate material in S1 under the condition that the pressure is 15mTorr, the RF power of the etching system is 300W during plasma etching, and the DC bias is 50W, so that the low-damage etched porous organosilicate material is obtained; the SF6And C4F6SF in mixed gas6Has a purity of 99.99% and C4F6The purity of (2) is 99.99%; the SF6And C4F6SF in mixed gas6At a flow rate of 20sccm, C4F6The flow rate of (2) was 6 sccm.
SF in this example6And C4F6The mixed gas is etched under a low-temperature environment to form an alcohol-like byproduct, the alcohol-like byproduct is condensed into gaps of the porous organosilicate at a low temperature to form a protective layer, and the damage of plasma to the porous organosilicate is greatly reduced under the action of the protective layer.
Example 2
The method for etching the porous organic silicate material with low damage in the embodiment comprises the following steps:
s1, placing the porous organic silicate material into an etching system, and precooling the etching system to-40 ℃ to obtain a precooled etching system;
s2, pre-cooling etching in S1 at-40 DEG CIntroducing SF into the system6And C4F6The etching system carries out plasma etching on the porous organosilicate material in S1 under the condition that the pressure is 25mTorr, the RF power of the etching system is 500W during plasma etching, and the DC bias is 150W, so that the low-damage etched porous organosilicate material is obtained; the SF6And C4F6SF in mixed gas6Has a purity of 99.999% and C4F6The purity of (A) is 99.999%; the SF6And C4F6SF in mixed gas6At a flow rate of 40sccm, C4F6The flow rate of (2 sccm).
SF in this example6And C4F6The mixed gas is etched under a low-temperature environment to form an alcohol-like byproduct, the alcohol-like byproduct is condensed into gaps of the porous organosilicate at a low temperature to form a protective layer, and the damage of plasma to the porous organosilicate is greatly reduced under the action of the protective layer.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Any simple modification, change and equivalent changes of the above embodiments according to the technical essence of the invention are still within the protection scope of the technical solution of the invention.

Claims (5)

1. A method for etching a porous organosilicate material with low damage is characterized in that the method comprises the following steps:
s1, placing the porous organic silicate material into an etching system, and precooling the etching system to the temperature of-60 ℃ to-40 ℃ to obtain a precooled etching system;
s2, introducing SF into the pre-cooled etching system in S1 at the temperature of-60 to-40 DEG C6And C4F6And (3) mixing the gases, and carrying out plasma etching on the porous organic silicate material in the S1 by using the etching system to obtain the low-damage etched porous organic silicate material.
2. The low damage etch of claim 1A process for the preparation of a porous organosilicate material, characterized in that SF as described in S26And C4F6SF in mixed gas6The purity of the product is 99.99 to 99.999 percent, C4F6The purity of the product is 99.99-99.999%.
3. The method for low damage etching of porous organosilicate material of claim 1, wherein said SF at S26And C4F6SF in mixed gas6The flow rate of (C) is 20-40 sccm4F6The flow rate of (2) sccm to 6 sccm.
4. The method for low damage etching of porous organosilicate material of claim 1, wherein the pressure of said etching system in S2 is between 15mTorr and 25 mTorr.
5. The method for low damage etching of porous organosilicate material of claim 1, wherein said etching system at S2 has an RF power of 300W-500W and a DC bias of 50W-150W.
CN202210155688.5A 2022-02-21 2022-02-21 Method for etching porous organic silicate material with low damage Pending CN114566431A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005071721A1 (en) * 2004-01-26 2005-08-04 Oxford Instruments Plasma Technology Limited Plasma etching process
US20150294880A1 (en) * 2012-10-30 2015-10-15 Curtis Anderson Fluorocarbon molecules for high aspect ratio oxide etch
US20160276133A1 (en) * 2015-03-17 2016-09-22 Imec Vzw Plasma etching of porous substrates
US20160307732A1 (en) * 2015-04-20 2016-10-20 Tokyo Electron Limited Method of etching porous film
TW202141622A (en) * 2020-04-27 2021-11-01 大陸商中微半導體設備（上海）股份有限公司 Low temperature etching method and device for substrate characterized by improving the accumulation of charges on the etched surface and preventing the deflection of the ion bombarding direction, thereby increasing the maximum etching depth and improving the structure deformation after etching

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005071721A1 (en) * 2004-01-26 2005-08-04 Oxford Instruments Plasma Technology Limited Plasma etching process
US20150294880A1 (en) * 2012-10-30 2015-10-15 Curtis Anderson Fluorocarbon molecules for high aspect ratio oxide etch
US20160276133A1 (en) * 2015-03-17 2016-09-22 Imec Vzw Plasma etching of porous substrates
US20160307732A1 (en) * 2015-04-20 2016-10-20 Tokyo Electron Limited Method of etching porous film
TW202141622A (en) * 2020-04-27 2021-11-01 大陸商中微半導體設備（上海）股份有限公司 Low temperature etching method and device for substrate characterized by improving the accumulation of charges on the etched surface and preventing the deflection of the ion bombarding direction, thereby increasing the maximum etching depth and improving the structure deformation after etching
CN113643973A (en) * 2020-04-27 2021-11-12 中微半导体设备(上海)股份有限公司 Low-temperature etching method and device

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