CN114089726A

CN114089726A - Fault diagnosis system

Info

Publication number: CN114089726A
Application number: CN202111395896.4A
Authority: CN
Inventors: 赵振宇; 杜辉; 孟凯旋; 王力; 张晓红
Original assignee: Hangzhou Hollysys Automation Co Ltd
Current assignee: Hangzhou Hollysys Automation Co Ltd
Priority date: 2021-11-23
Filing date: 2021-11-23
Publication date: 2022-02-25
Anticipated expiration: 2041-11-23
Also published as: CN114089726B

Abstract

The application discloses fault diagnosis system, including information acquisition processor, ADC chipset, change over switch group and acquisition controller. The acquisition information processor forms a field signal acquisition link and a diagnosis signal link by controlling a change-over switch pin of the change-over switch group; and determining whether the sampling resistance and/or the acquisition link of the AI acquisition system are/is in fault according to the field acquisition data. One end of the change-over switch group is connected with the target equipment, and the other end of the change-over switch group is connected with the ADC chip group; the ADC chip group performs analog-to-digital conversion on the received signals and sends data obtained by conversion to the acquisition information processor; the number of ADC chips of the ADC chip set and the number of input channels of each ADC chip are determined by the number of signal acquisition paths. The acquisition controller is used for controlling the time sequence control and the field signal acquisition of the ADC chip set. On the basis of low cost, the fault diagnosis meeting the SIL3 requirements on the SISAI acquisition system under the framework of 1oo1 is realized.

Description

Fault diagnosis system

Technical Field

The application relates to the field of SIS, in particular to a fault diagnosis system.

Background

As is well known, a Distributed Control System (DCS) and a Safety Instrumentation System (SIS) are indispensable devices in a production process, and the DCS is used for continuous measurement, conventional Control, operation Control and management in the production process to ensure stable operation of a production apparatus. The DCS is a dynamic system which continuously detects, calculates and controls process variables all the time, dynamically controls the production process and ensures the quality and the yield of products. And the SIS is used for monitoring the running condition of the production device and rapidly processing the abnormal working condition, so that the harm is reduced to the minimum, and personnel and the production device are in a safe state. The SIS is a static system, the operation of the production device is always monitored under normal working conditions, the output of the system is unchanged, the production process is not influenced, and the production device is subjected to logic operation according to the preset design under abnormal working conditions to realize the safety interlocking or parking of the production device. Therefore, DCS can be used for replacing SIS in some application scenes, but the requirements of reliability and usability of SIS are stricter than that of DCS, and the independent arrangement of SIS and DCS hardware is recommended in the standards of IEC61508, IEC61511, ISAS84.01, SH/T3018 and the like. Therefore, a separate SIS is required for some specific sites, and a DCS (Distributed Control System) cannot be used instead. For example, one or two major sources of danger involving toxic gases, liquefied gases, and highly toxic liquids require a separate SIS, or a separate SIS is required to eliminate Safety risks with instrument circuits rated at SIL (Safety Integrity Level) 1 and above.

For the application scenario requiring independent configuration of SIS, each SIS manufacturer designs a self-organized SIS according to its own understanding of IEC61508 standard. In order to meet the certification requirement of the SIL3, most manufacturers diagnose AI (Analog Input) acquisition systems in a redundancy comparison manner, specifically compare data acquired by 2 or 3 independent AI acquisition systems, so that the fault diagnosis coverage meets the requirement of the SIL3 on the premise of a certain fault margin. However, it must rely on redundant systems to achieve diagnostic goals. For a 1oo1 system with a fault margin of 0, the so-called 1oo1 system refers to a system with 1 AI acquisition system in one channel, and the method is obviously not applicable. In addition, adding redundant systems also increases SIS cost.

In view of this, how to implement fault diagnosis meeting the requirements of SIL3 on an SIS AI acquisition system under a 1oo1 architecture on the basis of low cost is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The application provides a fault diagnosis system, and on the basis of low cost, fault diagnosis meeting SIL3 requirements is carried out on an AI acquisition system of an SIS under a 1oo1 framework.

In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:

the embodiment of the invention provides a fault diagnosis system, which is applied to an AI acquisition system of SIS and comprises an acquisition information processor, an ADC chip set, a change-over switch set and an acquisition controller;

the acquisition information processor is used for forming a field signal acquisition link and a diagnosis signal link by controlling pins of all the change-over switches in the change-over switch group; the device is also used for determining whether the sampling resistor and/or the acquisition link of the AI acquisition system are in failure or not according to the field signal acquisition data;

one end of the change-over switch group is connected with target equipment, and the other end of the change-over switch group is connected with an input channel of the ADC chip group;

the ADC chip set is used for carrying out analog-to-digital conversion on the received signals and sending data obtained by conversion to the acquisition information processor; the number of ADC chips in the ADC chip group and the number of input channels of each ADC chip are determined by the number of signal acquisition paths;

the acquisition controller is used for controlling the time sequence control and the field signal acquisition of the ADC chip set.

Optionally, the ADC chipset includes a first ADC chip, a second ADC chip, a third ADC chip, and a fourth ADC chip;

the first ADC chip, the second ADC chip, the third ADC chip and the fourth ADC chip are connected in parallel, and the first ADC chip, the second ADC chip, the third ADC chip and the fourth ADC chip adopt the same framework.

Optionally, the system further comprises an isolator disposed between the collected information processor and the collection controller.

Optionally, the target device is a first resistor and a second resistor; the first resistor and the second resistor are two resistors which divide the sampling resistor into two resistors according to a preset proportional relation;

correspondingly; the acquisition information processor is used for determining whether the sampling resistor of the AI acquisition system breaks down or not by comparing whether the proportional value of the voltage values acquired by the first resistor and the second resistor is consistent with the preset proportional relationship or not.

Optionally, the first resistor includes a channel first resistor and a channel first resistor; the second resistor comprises a channel second resistor and a channel second resistor; the first channel first resistor and the first channel second resistor are disposed in a first acquisition channel, and the second channel first resistor and the second channel second resistor are disposed in a second acquisition channel;

the change-over switch group comprises a first analog switch, a second analog switch, a third analog switch and a fourth analog switch which all comprise 3 pins; a first pin of the first analog switch is connected with one end of the second resistor of the channel, a second pin is communicated with the diagnostic signal link, and a third pin is connected with a first pin of the third analog switch; a first pin of the second analog switch is simultaneously connected with the other end of the second resistor of the channel and one end of the first resistor of the channel, a second pin is communicated with the diagnostic signal link, and a third pin is connected with a first pin of the fourth analog switch; a second pin of the third analog switch is connected with one end of the second resistor of the second channel, and a third pin of the third analog switch is connected with a first input channel of the ADC chip set; a second pin of the fourth analog switch is simultaneously connected with the other end of the second resistor of the second channel and one end of the first resistor of the second channel, and a third pin is connected with a second input channel of the ADC chip set; the other end of the first resistor of the first channel and the other end of the first resistor of the second channel are both grounded.

Optionally, the target device is a multi-channel analog-to-digital converter, and the total number of channels in each group of the analog-to-digital converter is the same as the number of input channels of each ADC chip in the ADC chip set; the number of the groups of the analog-to-digital converters is the same as the total number of the ADC chips of the ADC chip group;

each output channel of the analog-to-digital converter is connected to a corresponding switch pin in the change-over switch group so as to be communicated with an input channel of the ADC chip group through a channel formed by the change-over switch group; the analog-to-digital converter is used for providing a diagnosis voltage signal for the ADC chip set;

correspondingly, the acquisition information processor is used for determining whether a sampling link of the AI acquisition system fails by judging whether the voltage signal output by the ADC chip set is consistent with the voltage signal output by the analog-to-digital converter.

Optionally, the switch group includes a first analog switch, a second analog switch, a third analog switch, and a fourth analog switch, each of which includes 3 pins;

the first pin of the first analog switch is used for communicating the field signal acquisition link, the second pin is connected with the first output channel of the analog-to-digital converter, and the third pin is connected with the first pin of the third analog switch;

the first pin of the second analog switch is used for communicating the field signal acquisition link, the second pin is connected with the second output channel of the analog-to-digital converter, and the third pin is connected with the first pin of the fourth analog switch;

a second pin of the third analog switch is used for communicating the field signal acquisition link, and a third pin is connected with a first input channel of the ADC chip set;

and a second pin of the fourth analog switch is used for communicating the field signal acquisition link, and a third pin of the fourth analog switch is connected with a second input channel of the ADC chip set.

Optionally, the acquired information processor is further configured to control a preset value of the analog-to-digital converter according to a preset diagnostic channel DAC setting code value rule.

Optionally, the collected information processor is further configured to:

controlling switch pins of the change-over switch group corresponding to each input channel of the ADC chip group to be in a DAC test pattern state, and setting a voltage value of each output channel of the analog-to-digital converter according to the current diagnosis step number;

the method comprises the steps that fault diagnosis is carried out on a field signal acquisition channel by judging whether input voltage information acquired by each input channel is consistent with a preset expected value or not;

and when the fault diagnosis operation of the field signal acquisition channel is detected to be finished, controlling the switch pins of the selector switch group corresponding to each input channel of the ADC chip group to be in a normal signal acquisition state.

Optionally, the collected information processor is further configured to:

controlling switch pins of the change-over switch group corresponding to each input channel of the ADC chip group to be in a DAC test pattern state;

if the current diagnosis step number indicates the crosstalk diagnosis of the ADC odd channels, setting the odd output channels and the even output channels in the target group of the analog-to-digital converter to output first specific voltage signals, and setting the output channels of the other groups to output second specific voltage signals; if the current diagnosis step number indicates crosstalk diagnosis of an ADC even channel, setting odd output channels and even output channels in the target group of the analog-to-digital converter to output third specific voltage signals, and setting output channels of other groups to output fourth specific voltage signals;

diagnosing crosstalk among the input channels of the ADC chip set by judging whether input voltage information acquired by each input channel is consistent with a preset expected value or not;

and when the fault diagnosis operation of the inter-channel crosstalk is detected to be finished, controlling the switch pins of the selector switch group corresponding to each input channel of the ADC chip set to be in a normal signal acquisition state.

The technical scheme provided by the application has the advantages that the switching mode of different switch pins of the selector switch group is controlled by the acquisition information processor, the field signal acquisition link and the diagnosis signal link can be provided at the same time, whether sampling resistance or sampling link faults exist in the AI acquisition system of the SIS can be diagnosed by data information acquired by a plurality of input channels of the ADC chip group, rapid and comprehensive diagnosis of the AI acquisition system can be realized, and the diagnosis coverage rate can reach high requirements. And a redundant part is not required to be arranged, so that the cost of the whole SIS system is reduced, and fault diagnosis meeting the SIL3 requirement on the AI acquisition system of the SIS under the 1oo1 framework can be realized.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the related art, the drawings required to be used in the description of the embodiments or the related art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic diagram of a framework of an exemplary fault diagnosis application scenario in the related art according to an embodiment of the present invention;

fig. 2 is a structural diagram of an embodiment of a fault diagnosis system according to an embodiment of the present invention;

fig. 3 is a schematic frame diagram of a fault diagnosis system for performing fault diagnosis on a sampling resistor according to an embodiment of the present invention;

fig. 4 is a schematic frame diagram of a fault diagnosis system for performing fault diagnosis on an acquisition link according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and claims of this application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.

According to the requirements of IEC61508-2 or GB/T20438.2, specific diagnosis measures are required for three failure modes, namely DC failure (direct current failure), drifting and oscillation, with medium or high safety failure scores. The reference design given in the standard is "input compare/vote" which is the maximum diagnostic coverage that can be achieved by the diagnostic measure of 99%, the diagnostic coverage being the part with the lowest probability of failure of the hardware threat resulting from the automatic diagnostic test, and the critical failure being the failure that puts the safety system in a potentially dangerous or non-functional state. But the method is applicable only when the data stream changes within the diagnostic test interval. The structure of an AI acquisition system commonly used in the related art SIS is shown in fig. 1 according to the recommendations in the above standards. In the diagnosis scheme shown in fig. 1, AI acquisition circuits adopt a redundant form, each AI acquisition circuit respectively sends acquired data to a data voting component for data comparison, a comparator of the data voting component compares the two sets of data, and if the data are consistent and do not exceed a preset deviation range, the data are reported. If the collected values of the two redundant circuits are continuously inconsistent, the value collected by the channel is considered to be unreliable, data is not reported, and the quality bit of the channel is set to be bad.

For the fault diagnosis method shown in fig. 1, which uses redundant acquisition circuits, it is obvious that this one acquisition circuit is not suitable for the occasions with low cost requirement. Furthermore, for AI-type acquisition systems, the external meter signal that is typically acquired is a 4-20mA signal. For such signals, the comparison with redundant circuits is difficult in design. The use of the diagnostic method described above can only be ensured if the sampling resistors of the two acquisition circuits are connected in series. However, for the series-type acquisition circuit, when one of the sampling resistors is open, it is difficult to bypass the current by technical means without acquisition precision loss. In order to solve the technical defects existing in the related art, the following technical scheme is provided. Various non-limiting embodiments of the present application are described in detail below.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a fault diagnosis system in a specific implementation manner according to an embodiment of the present invention, where the embodiment is used for performing fault diagnosis on an AI acquisition system of an SIS, and the embodiment of the present invention may include the following contents:

the fault diagnosis system may include an acquisition information processor 21, an ADC chipset 22, a switch group 23, and an acquisition controller 24. The collected information processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, a controller, a microcontroller, a microprocessor or other data processing chip, and the like. The collected information processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the acquisition information processor 21 may be integrated with a GPU (Graphics Processing Unit) for rendering and drawing content to be displayed on the display screen. In some embodiments, the acquired information processor 21 may further include an AI (Artificial Intelligence) processor for processing a calculation operation related to machine learning. The ADC chip set 22 may include a plurality of ADC (Analog-to-digital converter) chips, each ADC chip may be any device capable of implementing Analog-to-digital conversion, which does not affect the implementation of the present application, each ADC chip may include a plurality of input channels, and the number of ADC chips in the ADC chip set and the number of input channels of each ADC chip are determined by the number of signal acquisition paths. For example, the ADC chipset 22 may include a first ADC chip, a second ADC chip, a third ADC chip, and a fourth ADC chip; the first ADC chip, the second ADC chip, the third ADC chip and the fourth ADC chip are connected in parallel, and the first ADC chip, the second ADC chip, the third ADC chip and the fourth ADC chip adopt the same framework. The switch group 23 includes a plurality of switches, and the number of the switches included in the switch group is determined by the number of input channels included in the ADC chipset 22 or the total number of channels of signals to be acquired by the entire system. The switch group 23 may include a plurality of switch subgroups, each switch subgroup includes a plurality of switches, and those skilled in the art can set the switch subgroups according to actual needs, which is not limited in this application. The acquisition controller 24 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array).

In this embodiment, the collected information processor 21 may be configured to form a field signal collecting link and a diagnostic signal link by controlling pins of each switch in the switch group 23; and the sampling resistance and/or the acquisition link of the AI acquisition system are/is determined whether to have a fault or not according to the field signal acquisition data. According to the embodiment, data acquisition is carried out through a field signal acquisition link or a diagnosis signal link according to actual requirements, and then whether the AI acquisition system breaks down or not is judged by analyzing and comparing the acquired data with expected data. Specifically, the diagnosis can be performed not only on the sampling resistance of the AI acquisition system, but also on the acquisition link. Furthermore, if a fault is diagnosed, the fault can be reported, and the existing fault can be fed back through any one of voice, mail, alarm, text box prompt and the like.

In the present embodiment, one end of the switch group 23 is connected to the target device, and the other end is connected to the input channel of the ADC chipset 22. The target device is determined according to the diagnosis target, if the diagnosis is carried out on the sampling resistor, the target device is a resistor component, and if the diagnosis is carried out on the acquisition link, the target device is a device capable of inputting voltage signals, such as a digital-to-analog converter (DAC). The ADC chip set 23 is configured to perform analog-to-digital conversion on the received signal, and send the converted data to the acquired information processor 21. The acquisition controller 24 may be used to control timing control of the ADC chipset and to control the acquisition operation of the field signals.

In addition, in order to further improve the data acquisition precision and reduce interference, the field-side digital quantity signal after the ADC conversion and the system-side acquisition controller 24 may be isolated, that is, the whole system may further include an isolator, which is disposed between the acquisition information processor and the acquisition controller. Inevitably, the entire system should also include memory, which may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high speed random access memory as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. The memory may in some embodiments be an internal storage unit of the electronic device, e.g. a hard disk of a server. The memory may also be an external storage device of the electronic device in other embodiments, such as a plug-in hard disk provided on a server, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 70 may also include both an internal storage unit and an external storage device of the electronic device. The memory can be used for storing application software installed in the electronic device and various data, such as: the code of the program that executes the vulnerability handling method, etc. may also be used to temporarily store data that has been output or is to be output. In this embodiment, the memory is at least used for storing a computer program, wherein after being loaded and executed by the collected information processor 21 and the collection controller 24, the computer program can implement relevant steps of the fault diagnosis method disclosed in any one of the foregoing embodiments. In addition, the resources stored in the memory may also include an operating system, data and the like, and the storage mode may be transient storage or permanent storage. The operating system may include Windows, Unix, Linux, and the like. The data may include, but is not limited to, data generated throughout the fault diagnosis process, and the like.

In the technical scheme provided by the embodiment of the invention, the on-site signal acquisition link and the diagnosis signal link can be simultaneously provided by controlling the switching mode of different switch pins of the switch group through the acquisition information processor, and whether the sampling resistor or the sampling link fault exists in the AI acquisition system of the SIS can be diagnosed through the data information acquired by the plurality of input channels of the ADC chip group, so that the rapid and comprehensive diagnosis of the AI acquisition system can be realized, and the diagnosis coverage rate can meet high requirements. And a redundant part is not required to be arranged, so that the cost of the whole SIS system is reduced, and fault diagnosis meeting the SIL3 requirement on the AI acquisition system of the SIS under the 1oo1 framework can be realized.

The above-described embodiments define how to diagnose the sampling resistance of the AI acquisition system of the SIS, and the present application also provides an exemplary embodiment that may include the following:

in this embodiment, the sampling resistor is divided into two resistors according to a preset proportional relationship, that is, a first resistor and a second resistor, and accordingly, the target device is the first resistor and the second resistor. In this embodiment, a circuit structure of the entire fault detection system is described by taking an example that an ADC chipset at least includes one ADC chip, and each ADC chip includes two input channels: since the ADC chipset 22 includes two input channels, each input channel corresponds to one acquisition channel, and each of the first resistors and the second resistors has 2 resistors, which need to be disposed in the two acquisition channels, for convenience of distinction, each first resistor may be referred to as a first channel first resistor and a second channel first resistor; the 2 second resistors are called a channel second resistor and a channel second resistor; the first channel resistor and the second channel resistor are disposed in the first acquisition channel, and the first channel resistor and the second channel resistor are disposed in the second acquisition channel. The change-over switch group 23 includes a first analog switch, a second analog switch, a third analog switch, and a fourth analog switch each including 3 pins. The first pin of the first analog switch is connected with one end of a channel second resistor, the second pin of the first analog switch is communicated with the diagnosis signal link, and the third pin of the first analog switch is connected with the first pin of the third analog switch. The first pin of the second analog switch is simultaneously connected with the other end of the second resistor of the channel and one end of the first resistor of the channel, the second pin of the second analog switch is communicated with the diagnosis signal link, and the third pin of the second analog switch is connected with the first pin of the fourth analog switch. The second pin of the third analog switch is connected to one end of the second resistor of the two-channel, and the third pin of the third analog switch is connected to the first input channel of the ADC chipset 22. A second pin of the fourth analog switch is connected with the other end of the two-channel second resistor and one end of the two-channel first resistor at the same time, and a third pin of the fourth analog switch is connected with a second input channel of the ADC chip set 22; the other end of the first resistor of the first channel and the other end of the first resistor of the second channel are both grounded.

Based on the above circuit structure, the acquisition controller 24 realizes the timing control and the field signal acquisition of each ADC chip of the ADC chip sets. The acquired information processor 21 is configured to determine whether the sampling resistor of the AI acquisition system fails by comparing whether a proportional value of the voltage value acquired by the first resistor and the second resistor is consistent with a preset proportional relationship, so as to implement the sampling resistor diagnosis of the AI acquisition system of the SIS.

In order to make the technical solution of the present application more clear to those skilled in the art, the present application takes the acquisition information processor 21 as a microprocessor MCU, the acquisition controller 24 as an FPGA, and the switch set includes a plurality of analog switches as an example, and with reference to fig. 3, a process of implementing the sampling resistance diagnosis by acquiring 32 signals is described, which may include:

in this embodiment, the ADC chipset may include a first ADC chip U1, a second ADC chip U2, a third ADC chip U3, and a fourth ADC chip U4; the first ADC chip U1, the second ADC chip U2, the third ADC chip U3, and the fourth ADC chip U4 are connected in parallel, and the first ADC chip U1, the second ADC chip U2, the third ADC chip U3, and the fourth ADC chip U4 adopt the same architecture, and each ADC chip includes 8 input channels. Since the ADC chips have the same structure, the second ADC chip U2 and the third ADC chip U3 are omitted in fig. 3. For each ADC chip, each input channel corresponds to one acquisition channel and comprises a selector switch group and a sampling resistor, and each selector switch group comprises 2 analog switches. For each sampling resistor, the embodiment divides the sampling resistor into two resistors in proportion, namely, the R2 resistor is diagnosed by increasing the R1 resistor, the field signal acquisition and the sampling resistor test pattern are performed simultaneously, the voltage at two ends of the R2 resistor is V2, and the voltage at two ends of the R1 resistor is V1. The resistances of the sampling resistors at V1 and V2 may be 130 Ω, for example, the resistors may convert the current signal into a voltage signal, the switching switch group for switching the switching of the field signal and the diagnostic signal may employ ADG5436 including S1, S2, S3 and S4 analog switches, and the ADC chip may employ an AD7779 chip, for example. IN1-IN8 correspond to the 8 signal input channels of the ADC. The wiring of each component can be seen from fig. 3, in which the dotted line is a diagnostic signal path and the solid line is a field signal acquisition path. In this embodiment, the wiring relationship between the components corresponding to the two input channels of one ADC chip is described, and the wiring relationship between the other input channels in the chip and the input channels of the other ADC chips may refer to corresponding descriptions, which are not described herein again. The isolator isolation completes isolation between the field side digital quantity signal converted by the ADC and the system side FPGA. The FPGA realizes the sequential control and the field signal acquisition of the ADC chip set. And the MCU reads a field signal acquisition value from a fixed register address in the FPGA, and performs judgment comparison and fault reporting.

For the sampling resistance test pattern described in fig. 3, the sampling resistance is divided into two resistances R1 and R2 having a certain proportional relationship, and whether the voltage values acquired by the two sampling resistances are consistent with a preset proportional relationship is compared, so as to determine whether the sampling resistance fails. Because the fault margin of the partial circuit is 0, in order to meet the requirement of high diagnosis coverage rate (99%), the diagnosis is carried out in real time along with the acquisition of external signals, and when the sampling resistor has a fault, the related fault can be reported in real time.

The foregoing embodiments define how to diagnose an acquisition link of an AI acquisition system of an SIS, where the acquisition link may include an acquisition link ADC chip combined data storage RAM, and the present application further provides an exemplary embodiment that may include the following:

in this embodiment, the target device may be a multi-channel analog-to-digital converter DAC, and the total number of channels in each group of the analog-to-digital converter is the same as the number of input channels of each ADC chip in the ADC chip set 22; the number of the groups of the analog-to-digital converters is the same as the total number of ADC chips of the ADC chip group. Taking the example of collecting 32 channels of signals, the ADC chipset includes 4 ADC chips, each ADC chip includes 8 input channels, and then the analog-to-digital converter DAC includes 4 sets of output channels, each set including 8 output channels. Each output channel of the analog-to-digital converter is connected to a corresponding switch pin in the change-over switch group so as to be communicated with an input channel of the ADC chip group through a channel formed by the change-over switch group; the analog-to-digital converter is used for providing a diagnosis voltage signal for the ADC chip set. Taking the example that each ADC chip set includes one ADC chip, each ADC chip includes 2 output channels, the connection relationship between each output channel of the analog-to-digital converter and the switch set is: the change-over switch group comprises a first analog switch S1, a second analog switch S2, a third analog switch S3 and a fourth analog switch S4 which all comprise 3 pins; a first pin of the first analog switch S1 is used for communicating a field signal acquisition link, a second pin of the first analog switch S1 is connected to a first output channel of the analog-to-digital converter, and a third pin of the first analog switch S1 is connected to a first pin of a third analog switch. A first pin of the second analog switch S2 is used for communicating a field signal acquisition link, a second pin of the second analog switch S2 is connected with a second output channel of the analog-to-digital converter, and a third pin of the second analog switch S2 is connected with a first pin of the fourth analog switch S4; a second pin of the third analog switch S3 is used for communicating the field signal acquisition link, and a third pin of the third analog switch S3 is connected to the first input channel of the ADC chipset 22; a second pin of the fourth analog switch S4 is used for communicating the field signal acquisition link, and a third pin of the fourth analog switch S4 is connected to a second input channel of the ADC chipset 22.

In this embodiment, the acquired information processor 21 may be configured to determine whether a sampling link of the AI acquisition system fails by determining whether a voltage signal output by the ADC chip set is consistent with a voltage signal output by the analog-to-digital converter. The collected information processor 21 is further configured to control the preset value of the analog-to-digital converter according to the preset diagnostic channel DAC setting code value rule, that is, the voltage of the DAC may be set according to two columns of the diagnostic channel DAC setting code values in table 1. In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the present application takes the acquisition information processor 21 as a microprocessor MCU, the acquisition controller 24 as an FPGA, and the switch group includes a plurality of analog switches as an example, and in combination with fig. 3, a description is given of an implementation process of acquiring link diagnosis by acquiring 32 signals, which may include:

in this embodiment, the ADC chipset may include a first ADC chip U1, a second ADC chip U2, a third ADC chip U3, and a fourth ADC chip U4; the first ADC chip U1, the second ADC chip U2, the third ADC chip U3, and the fourth ADC chip U4 are connected in parallel, and the first ADC chip U1, the second ADC chip U2, the third ADC chip U3, and the fourth ADC chip U4 adopt the same architecture, and each ADC chip includes 8 input channels. Since the ADC chips have the same structure, the second ADC chip U2 and the third ADC chip U3 are omitted in fig. 4. For each ADC chip, each input channel corresponds to one acquisition channel and comprises a selector switch group and a sampling resistor, and each selector switch group comprises 2 analog switches. The group of switches for switching between the field signal and the diagnostic signal may employ ADG5436, for example, and the ADC chip may employ an AD7779 chip, for example. IN1-IN8 correspond to the 8 signal input channels of the ADC. The wiring of the components can be seen in fig. 4, where the dotted lines are diagnostic signal paths and the solid lines are field signal acquisition paths. In this embodiment, the wiring relationship between the components corresponding to the two input channels of one ADC chip is described, and the wiring relationship between the other input channels in the chip and the input channels of the other ADC chips may refer to corresponding descriptions, which are not described herein again. The ADC test pattern principle is as shown in fig. 4, 1 piece of 8-channel DAC is used to provide the same diagnostic voltage signal for 4 pieces of ADC, and 4 pieces of ADC respectively complete the diagnosis result determination according to whether the adopted voltage signal is consistent with the DAC output voltage signal. During the test pattern, the analog switches S1 and S2 need to be switched from 1 pin to 2 pins in advance, and then output the DAC preset values according to the voltage values shown in table 1, that is, according to the two columns of the DAC set code values of the diagnostic channels (the setting parameters of the DAC are REF gain of 1 and output gain of 2). Because the 4 ADC chips are in parallel, the diagnosis of the same channel of the 4 chips can be completed by one-time diagnosis.

TABLE 1 Preset diagnostic channel DAC set code value rules

Based on the above embodiments, the present application further provides a walk diagnosis manner for diagnosing only a field signal acquisition channel, that is, for diagnosing bit, the walk diagnosis only focuses on a channel corresponding to V2, and does not need to focus on a channel corresponding to V1, and V1 and V2 respectively correspond to terminal voltages of two sampling resistors on each CH acquisition channel. Where V2 is treated as the actual sensor value in the code and V1 is treated as the diagnostic voltage of V2, both are normally equal. The specific diagnostic steps are described below, i.e. the collected information processor 21 is also configured to:

controlling switch pins of a change-over switch group corresponding to each input channel of the ADC chip set to be in a DAC test pattern state, and setting a voltage value of each output channel of the analog-to-digital converter according to the current diagnosis step number;

In this embodiment, referring to fig. 4, after the MCU 21 enters the diagnostic interrupt service routine, the MCU accumulates the diagnostic steps, and automatically clears the diagnostic steps when the diagnostic steps reach the upper limit, and determines which operations to execute in this step according to the current diagnostic step information, that is, the MCU controls the DAC to output different voltage values. The MCU controls the analog switches corresponding to the 32 input channels to be in a DAC test pattern state, namely, the connection between the ADC and a field signal is disconnected, and during diagnosis, S1 and S2 in the picture 4 are connected with pins 2, and S3 and S4 are connected with pins 1. In normal collection, the pins S1 and S2 are connected with 1, and the pins S3 and S4 are synchronously switched between the front 16 channels and the rear 16 channels. Then, the input voltage of 8 channels (4 groups) of the DAC chip is set according to the current step number, the input voltage of the current diagnosed channel in the 4 ADC chips is one of Vref 1-Vref 10, and the voltage values of the rest channels are Vref 11; the remaining channels refer to the remaining 7 channels of the ADC, and only one channel can be diagnosed per diagnosis. The voltage setting value may be set in a manner as shown in table 2, and the voltage value is settled according to the code value, which is related to the acquisition accuracy of the product. For the acquisition precision of 0.2%, the acquisition precision corresponds to the first 10 bits, so that 10 groups of voltage values can be obtained by only closing a loop by one bit each time. The 32-channel circuit collects input voltage and judges whether the result is consistent with an expected value; the diagnosis of a single acquisition channel of the 4 ADC chips is completed through the above operations, and the MCU controls the analog switches of the 32 input channels to be in a state corresponding to normal acquisition. And after the interruption is finished, the MCU returns to a normal acquisition state. The reference voltage Vref selects 10 different values Vref 1-Vref 10 according to a walking-bit method, and 1 different Vref value is used when diagnosis interruption is entered each time. After 40 diagnostic interrupts were performed, the A/D conversion test was completed. The summary of the walk diagnosis steps can be organized into the diagnosis steps shown in Table 2.

In the embodiment, the Vref 1-Vref 10 are selected based on a walk diagnosis method to detect the DC fault of the ADC data line. Due to the limitation of an ADC chip, when positive voltage is collected, the highest bit is always 0, so that the method does not include the step, for a 24-bit ADC, a high 10-bit data line is adopted for performing walk diagnosis, and the low 13 bits are noise which is not necessary to be concerned, namely:

vref1 corresponds to an AD-converted output 01000000000 x xxxx xxxx xxxx;

vref 2 corresponds to an AD-converted output 00100000000 x xxxx xxxx xxxx;

vref 3 corresponds to an AD-converted output 00010000000 x xxxx xxxx xxxx;

vref 4 corresponds to an AD-converted output 00001000000 x xxxx xxxx xxxx;

vref 5 corresponds to an AD-converted output 00000100000 x xxxx xxxx xxxx;

vref 6 corresponds to output 00000010000 x xxxx xxxx xxxx after AD conversion;

vref 7 corresponds to an AD-converted output 00000001000 x xxxx xxxx xxxx;

vref 8 corresponds to an AD-converted output 00000000100 x xxxx xxxx xxxx;

vref 9 corresponds to an AD-converted output 00000000010 x xxxx xxxx xxxx;

vref10 corresponds to AD-converted output 00000000001 x xxxx xxxx xxxx.

TABLE 2 roaming diagnosis procedure Table

In this embodiment, the magnitude of the mutual interference between the input channels of the ADC chipset is also diagnosed, that is, inter-channel crosstalk diagnosis is performed, and the specific diagnosis steps of the input channels of the ADC including the acquisition channel and crosstalk detection between the diagnostic channels are described as follows, that is, the acquired information processor may be further configured to:

controlling switch pins of a change-over switch group corresponding to each input channel of the ADC chip group to be in a DAC test pattern state;

if the current diagnosis step number indicates the crosstalk diagnosis of the ADC odd channels, setting odd output channels and even output channels in a target group of the analog-to-digital converter to output first specific voltage signals, and outputting second specific voltage signals by the output channels of the other groups; if the current diagnosis step number indicates crosstalk diagnosis of an ADC even channel, setting odd output channels and even output channels in a target group of the analog-to-digital converter to output third specific voltage signals, and outputting fourth specific voltage signals by output channels of other groups;

diagnosing crosstalk among the input channels of the ADC chip set by judging whether the input voltage information acquired by each input channel is consistent with a preset expected value or not;

and when the fault diagnosis operation of the crosstalk between the channels is detected to be finished, controlling the switch pins of the selector switch group corresponding to each input channel of the ADC chip group to be in a normal signal acquisition state.

In this embodiment, referring to fig. 4, after the MCU 21 enters the diagnostic interrupt service routine, the MCU accumulates the diagnostic steps, and automatically clears the diagnostic steps when the diagnostic steps reach the upper limit, and determines which operations to execute in this step according to the current diagnostic step information, that is, the MCU controls the DAC to output different voltage values. The MCU controls the analog switches corresponding to the 32 input channels to be in a DAC test pattern state, namely, the connection between the ADC and a field signal is disconnected, and during diagnosis, S1 and S2 in the picture 4 are connected with pins 2, and S3 and S4 are connected with pins 1. In normal collection, the S1 and S2 are connected with 1 pin, and the S3 and S4 are synchronously switched between the front 16 channels and the rear 16 channels. If the current diagnosis step number indicates crosstalk diagnosis of the odd channels of the ADC, setting OUTX (x is equal to 1, 3, 5 and 7) and OUTy (y is equal to 2, 4, 6 and 8) of the DAC chip to output a specific voltage signal Vref12, and outputting zero values to the remaining 3 groups of channels; if the current diagnostic step number indicates crosstalk diagnosis of the ADC even-numbered channels, OUTx (x ═ 1, 3, 5, and 7) and OUTy (y ═ 2, 4, 6, and 8) of the DAC chip are set to output one specific voltage signal Vref13, and zero values are output to the remaining 3 groups of channels. The 32-channel circuit collects corresponding input voltage and judges whether the result is consistent with the expected value. After the diagnosis is finished, the MCU controls the analog switches corresponding to the 32 input channels to be in a normal acquisition state. After 8 diagnostic interrupts are performed according to the above steps, the detection of crosstalk between 8 input channels of ADC 1-ADC 4 is completed. The diagnostic procedure for the inter-channel crosstalk described above can be summarized as shown in table 3.

TABLE 3 diagnosis of interchannel crosstalk

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

A fault diagnosis system provided by the present application is described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, it can make several improvements and modifications to the present application, and those improvements and modifications also fall into the protection scope of the claims of the present application.

Claims

1. A fault diagnosis system is characterized in that the AI acquisition system applied to the SIS comprises an acquisition information processor, an ADC chip set, a change-over switch set and an acquisition controller;

2. The fault diagnosis system of claim 1, wherein the ADC chipset comprises a first ADC chip, a second ADC chip, a third ADC chip, and a fourth ADC chip;

3. The fault diagnosis system according to claim 1, further comprising an isolator provided between the acquisition information processor and the acquisition controller.

4. The fault diagnostic system of claim 1, wherein the target device is a first resistor and a second resistor; the first resistor and the second resistor are two resistors which divide the sampling resistor into two resistors according to a preset proportional relation;

5. The fault diagnostic system of claim 4, wherein the first resistance comprises a channel first resistance and a channel first resistance; the second resistor comprises a channel second resistor and a channel second resistor; the first channel first resistor and the first channel second resistor are disposed in a first acquisition channel, and the second channel first resistor and the second channel second resistor are disposed in a second acquisition channel;

6. The fault diagnosis system of claim 1, wherein the target device is a multi-channel analog-to-digital converter, and the total number of channels in each group of the analog-to-digital converter is the same as the number of input channels of each ADC chip in the ADC chipset; the number of the groups of the analog-to-digital converters is the same as the total number of ADC chips of the ADC chip group;

7. The fault diagnosis system according to claim 6, wherein the change-over switch group comprises a first analog switch, a second analog switch, a third analog switch and a fourth analog switch each including 3 pins;

8. The fault diagnosis system according to claim 6 wherein the collected information processor is further configured to control the preset values of the analog-to-digital converter according to preset diagnostic channel DAC set code value rules.

9. The fault diagnosis system according to claim 6, wherein the acquisition information processor is further configured to:

10. The fault diagnostic system of claim 6, wherein the collected information processor is further configured to: