CN113938623B - Frame transfer CCD with quasi-pixel exposure control structure - Google Patents
Frame transfer CCD with quasi-pixel exposure control structure Download PDFInfo
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- CN113938623B CN113938623B CN202111136478.3A CN202111136478A CN113938623B CN 113938623 B CN113938623 B CN 113938623B CN 202111136478 A CN202111136478 A CN 202111136478A CN 113938623 B CN113938623 B CN 113938623B
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/72—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors using frame transfer [FT]
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Abstract
The invention relates to a CCD image sensor structure, in particular to a frame transfer CCD with a similar pixel exposure control structure, which comprises a mode of inserting the similar pixel exposure control structure between a photosensitive area and a storage area for exposure control, wherein the similar pixel exposure control structure consists of a vertical transfer gate, an exposure grating, an exposure drain, an exposure potential barrier and a ditch resistance, and the exposure grating and the exposure drain are electrically connected through a primary contact hole, a primary metal, a secondary contact hole and a secondary metal; the invention adopts the similar pixel exposure control structure inserted between the photosensitive area and the storage area to carry out exposure control, does not occupy the pixel area of the photosensitive area, and ensures that the performances of frame transfer CCD sensitivity, potential well capacity, dynamic range and the like are not influenced.
Description
Technical Field
The invention relates to a CCD image sensor structure, in particular to a frame transfer CCD with a similar pixel exposure control structure.
Background
The frame transfer CCD is used as an important branch of the area array CCD, is widely applied to the photoelectric imaging fields of astronomical observation, space remote sensing and the like, and is a key component in some special fields such as hyperspectral imaging, collision test photography, animal ecology research and the like. When the frame transfer CCD is used as a key component of a hyperspectral camera imaging system to run in an on-orbit mode, the frame transfer CCD is saturated and has imaging blurring due to factors such as atmospheric light scattering, system parameter errors, radiometric calibration errors, dark current increase at the end of the service life of the frame transfer CCD, full well capacity reduction caused by working point drift and the like, and therefore an exposure control function is required to be added to the frame transfer CCD. Conventional exposure control structures require additional photosensitive area to cause reduced sensitivity or reduced potential well capacity and are not suitable for high sensitivity imaging applications.
Disclosure of Invention
In order to meet the application requirements of a camera imaging system taking a frame transfer CCD image sensor as a core component, the invention provides a frame transfer CCD with a similar pixel exposure control structure, wherein the similar pixel exposure control structure is inserted between a photosensitive area and a storage area to perform exposure control, the similar pixel exposure control structure comprises a first vertical transfer gate, a second vertical transfer gate, an exposure grating, an exposure drain, an exposure barrier and a ditch resistance, the first vertical transfer gate and the second vertical transfer gate are vertically and electrically connected, a primary contact hole is respectively arranged on the exposure grating and the exposure drain, primary metal is filled in the primary contact hole, a secondary contact hole is arranged on the primary metal, secondary metal is filled in the secondary contact hole, and the exposure grating and the exposure drain are electrically connected with a peripheral driving circuit through the secondary metal; an exposure barrier is arranged below the exposure gate, and the opening and closing of a channel under the gate are realized under the control of the exposure gate.
Further, frame transfer CCD timing control of the N frame-like pixel exposure control structure includes:
frame N invalid integration time;
the frame is transferred to a charge discharging channel of the pixel-like exposure control structure, and the channel is composed of an exposure grating, an exposure drain and an exposure barrier of the pixel-like exposure control structure;
the nth frame effective integration time;
transferring the frame to a storage area;
an nth frame read out is performed, and an n+1th frame invalid integration time is started at the same time as the nth frame read out.
Further, the frame period T frame For a period of time from the time of invalid integration of the current frame to the time of transition of the current frame to the memory area, the valid integration period of the current frame is T int If needed to realize T int ＝T frame In the charge integration and transfer process of the photosensitive region, the exposure gate controls the exposure barrier to be closed, N lines of signals after the integration of the photosensitive region is completed are quickly transferred to the storage area, and each line of charge signals of the photosensitive region is subjected to storage and transfer in the first vertical transfer gate and the second vertical transfer gate of the pixel-like exposure control structureAnd (5) processing.
Further, the frame period T frame For a period of time from the time of invalid integration of the current frame to the time of transition of the current frame to the memory area, the valid integration period of the current frame is T int If the n+1st frame signal needs to realize T int ＜T frame The method specifically comprises the following steps:
let it be assumed that at t 0 When the pixel is in an=0 state, the frame transfer process of the N-th frame signal is finished, the n+1-th frame signal starts to integrate the vertical transfer gate of the photosensitive area and is in an integrated level state, the vertical transfer gate of the pixel-like exposure control structure is biased to be in a low level, and the exposure gate is biased to be in a high level, so that an exposure barrier is opened;
at t=t frame -T int When the photosensitive region vertical transfer gate is in a frame transfer pulse level state, the vertical transfer gate and the exposure gate of the pixel-like exposure control structure still keep the level at the time t=0, so that the exposure barrier is opened, and the photosensitive region is at t 0 The charge signal generated by integration in t period is transferred under the action of driving pulse, and the exposure barrier is opened, so that at t 0 During the period of t, the charge signal generated by the integration of the frame transfer CCD with the pixel-like exposure control structure is discharged to the exposure drain, and the charge is emptied, so that the exposure control is realized;
then the vertical transfer gate of the photosensitive area is in an integration level state again, and the integration time of the photosensitive area is T int The vertical transfer gate of the pixel-like exposure control structure still maintains t 0 Time level, exposure gate bias changes to low level, so that exposure barrier is closed;
the photosensitive area has an integration time T int After the integration process of (2), a frame transfer process is carried out, and the vertical transfer gate of the pixel-like exposure control structure is from t 0 The time level changes into driving pulse, the exposure gate is biased into low level state, so that the exposure barrier is closed, and the photosensitive region is in T int The charge signal generated during the period does not enter the exposure drain due to the closing of the exposure barrier, but is rapidly transferred to the storage area until the output amplifier reads out the charge signal.
The frame transfer CCD with the pixel-like exposure control structure provided by the invention ensures that the frame transfer CCD has the exposure control function and simultaneously does not influence the performances such as the sensitivity, the potential well capacity, the dynamic range and the like of the frame transfer CCD.
Drawings
FIG. 1 is a prior art frame transfer CCD pixel architecture with a lateral charge-discharge control structure;
FIG. 2 is a prior art frame transfer CCD pixel architecture with a vertical charge bleed control structure;
FIG. 3 is a frame transfer CCD pixel architecture with a pixel-like exposure control structure in accordance with the present invention;
FIG. 4 is a schematic diagram of the exposure control structure of the pixel-like element of the present invention;
FIG. 5 is a schematic diagram of a frame transfer CCD timing control with a pixel-like exposure control structure according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a frame transfer CCD with a similar pixel exposure control structure, wherein the exposure control is carried out in a mode of inserting the similar pixel exposure control structure between a photosensitive area and a storage area, the similar pixel exposure control structure comprises a first vertical transfer gate, a second vertical transfer gate, an exposure grating, an exposure drain, an exposure barrier and a ditch resistance, the first vertical transfer gate and the second vertical transfer gate are vertically and electrically connected, a primary contact hole is respectively arranged on the exposure grating and the exposure drain, primary metal is filled in the primary contact hole, a secondary contact hole is arranged on the primary metal, secondary metal is filled in the secondary contact hole, and the exposure grating and the exposure drain are electrically connected with a peripheral driving circuit through the secondary metal; an exposure barrier is arranged below the exposure gate, and the opening and closing of a channel under the gate are realized under the control of the exposure gate.
The embodiment further describes a frame transfer CCD with a similar pixel exposure control structure according to the invention based on the existing CCD exposure control technology of frame transfer.
The prior frame transfer CCD exposure control technology is divided into two types, namely transverse charge release control and longitudinal charge release control, taking two-phase frame transfer CCD as an example, and a frame transfer CCD pixel architecture with a transverse charge release control structure is shown in FIG. 1.
The pixel architecture shown in fig. 1 is composed of a trench resistor, an anti-corona drain, a transverse anti-corona gate and a vertical drive V1/V2, wherein the potential distribution under the transverse anti-corona gate is in the state A in fig. 1 (b) by applying the level to the transverse anti-corona gate, at the moment, charges are stored in a vertical CCD potential well, and photo-generated charges exceeding the capacity of the vertical CCD potential well can enter the anti-corona drain beyond the potential barrier under the transverse anti-corona gate, so that the inhibition of the halation is realized; and (2) increasing a horizontal anti-blooming gate driving level, wherein the potential distribution under the horizontal anti-blooming gate is in the B state in the (B) of fig. 1, and all charges stored in a vertical CCD potential well are discharged to anti-blooming leakage at the moment, so that exposure control is realized. As can be seen from the analysis of the working principle of the frame transfer CCD with the transverse charge relief control structure, the transverse charge relief control structure occupies a part of the area of the CCD pixel, so that the frame transfer CCD has reduced performances such as sensitivity, potential well capacity, dynamic range and the like, and is not suitable for high-sensitivity imaging application.
The frame transfer CCD pixel structure with longitudinal charge drain control structure shown in FIG. 2 is composed of trench resistor and vertical drive V1/V2, wherein the charge drain structure is composed of buried trench-p-well-n-type epitaxial layer-n in FIG. 2 + A mold substrate. At n + The potential distribution of the charge discharging structure under the action of the substrate bias voltage forms an A state in (b) of fig. 2, at the moment, charges are stored in a vertical CCD potential well, and photo-generated charges exceeding the capacity of the vertical CCD potential well can enter anti-corona leakage beyond a horizontal anti-corona gate lower potential barrier, so that the inhibition of halation is realized; increasing n + The potential distribution of the charge discharging structure forms the B state in the (B) of fig. 2 due to the bias voltage of the substrate, and at the moment, all charges stored in the vertical CCD potential well are discharged to the anti-corona-leakage state, so that the exposure control is realized. As can be seen from the analysis of the working principle of the frame transfer CCD with the longitudinal charge release control structure, the frame transfer with the longitudinal charge release control structureThe CCD is manufactured based on an n-type substrate, and back illumination incidence cannot be realized, so that the frame transfer CCD with a longitudinal charge release control structure has limited sensitivity improving space, and is not suitable for high-sensitivity imaging application.
Aiming at the problems that the traditional frame transfer CCD exposure control structure needs to occupy extra photosensitive element area to cause sensitivity reduction or to cause full well capacity and dynamic range reduction, and is not suitable for high-sensitivity imaging application, in order to avoid the influence of the exposure control structure on the frame transfer CCD performance, an image element-like exposure control structure is inserted between a photosensitive area and a storage area to perform exposure control, the image element area of the photosensitive area is not occupied, and the performances of the frame transfer CCD such as sensitivity, potential well capacity and dynamic range are not influenced.
In this embodiment, a two-phase frame transfer CCD is taken as an example to describe a pixel-like exposure control structure, and a schematic diagram thereof is shown in fig. 4 below, and the structure is composed of a vertical transfer gate TG1/TG2, an exposure gate EG, an exposure drain ED, an exposure barrier EB, and a trench resistance. The exposure grating EG and the exposure drain ED are electrically connected through a primary contact hole, a primary metal, a secondary contact hole and a secondary metal.
As shown in FIG. 4, the vertical transfer gate TG1/TG2 of the pixel-like exposure control structure and the vertical transfer gate V1/V2 of the pixel in the photosensitive area have similar structural design and function, and can realize the storage and transfer of signals. The vertical transfer gate TG1 of the pixel-like exposure control structure receives the vertical transfer gate V1 of the photosensitive region, and the storage region vertical transfer gate V1 receives the vertical transfer gate TG2 of the pixel-like exposure control structure; the structure is different from the pixel of the photosensitive area in that a charge discharging channel formed by an exposure gate EG, an exposure drain ED and an exposure potential barrier EB is added.
Let the frame period be T frame The effective integration period is T int The frame transfer CCD timing control with the pixel-like exposure control structure is shown in FIG. 5:
(1) If T is needed to be realized int ＝T frame Then the exposure barrier EB is controlled to be closed by the exposure grating EG during the charge integration and transfer processes of the photosensitive region. The N-line signals after the integration of the photosensitive area are rapidly transferred to the storage area, and each line of charge signals of the photosensitive area are in the same classThe vertical transfer gate TG1/TG2 of the pixel exposure control structure undergoes a storage and transfer process, and since the exposure barrier EB is closed by the exposure gate EG, charge signals flowing through the vertical transfer gate TG1/TG2 do not enter the exposure drain ED, the charge signals are not emptied, the storage area in this case is equivalent to adding one row, i.e., n+1 rows, and the charge signals entering the storage area are transferred through n+1 slow rows to realize signal final readout.
(2) If T is needed to be realized int ＜T frame At t 0 When the pixel is=0, the frame transfer process of the nth frame signal is finished, the n+1st frame signal starts integration, at this time, the vertical transfer gate V1/V2 of the photosensitive region is in an integrated level state, the vertical transfer gate TG1/TG2 of the pixel-like exposure control structure is biased to a low level, and the exposure gate EG is biased to a high level, so that the exposure barrier EB is opened.
At t=t frame -T int When the photosensitive region vertical transfer gate is in a frame transfer pulse level state, the frame transfer time is ignored, the vertical transfer gate TG1/TG2 and the exposure gate EG of the pixel-like exposure control structure still keep the t=0 moment level, so that the exposure barrier EB is opened, and the photosensitive region is at t 0 The charge signal generated by integration in t period is transferred under the action of driving pulse, and the exposure barrier EB is opened, so that at t 0 During the period of t, a charge signal generated by integration of a frame transfer CCD with a similar pixel exposure control structure is discharged to an exposure drain ED, and charges are emptied, so that exposure control is realized.
Then the vertical transfer gate of the photosensitive area is in an integration level state again, and the integration time of the photosensitive area is T int The vertical transfer gate TG1/TG2 of the pixel-like exposure control structure still holds t 0 At the time level, the exposure gate EG bias is changed to a low level, so that the exposure barrier EB is closed.
The photosensitive area has an integration time T int After the integration process of (2), a frame transfer process is carried out, and the vertical transfer gate TG1/TG2 of the pixel-like exposure control structure is from t 0 The time level changes into driving pulse, the exposure gate EG bias is still in a low level state, so that the exposure barrier EB is closed, and the photosensitive region is in T int The charge signal generated during this time is due to the exposure barrier EBThe switch-off does not enter the exposure drain ED, but is quickly transferred to the storage area until the output amplifier reads out the charge signal.
In the description of the present invention, it should be understood that the terms "coaxial," "bottom," "one end," "top," "middle," "another end," "upper," "one side," "top," "inner," "outer," "front," "center," "two ends," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "connected," "secured," "rotated," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other or in interaction with each other, unless explicitly defined otherwise, the meaning of the terms described above in this application will be understood by those of ordinary skill in the art in view of the specific circumstances.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. The frame transfer CCD with the similar pixel exposure control structure is characterized in that exposure control is carried out in a mode of inserting the similar pixel exposure control structure between a photosensitive area and a storage area, the similar pixel exposure control structure comprises a first vertical transfer gate, a second vertical transfer gate, an exposure grating, an exposure drain, an exposure barrier and a ditch resistance, the first vertical transfer gate and the second vertical transfer gate are vertically and electrically connected, a primary contact hole is respectively arranged on the exposure grating and the exposure drain, primary metal is filled in the primary contact hole, a secondary contact hole is arranged on the primary metal, secondary metal is filled in the secondary contact hole, and the exposure grating and the exposure drain are electrically connected with a peripheral driving circuit through the secondary metal; an exposure barrier is arranged below the exposure gate, and the opening and closing of a channel under the gate are realized under the control of the exposure gate.
2. The frame transfer CCD with a pixel-like exposure control structure according to claim 1, wherein the frame transfer CCD timing control of the nth frame pixel-like exposure control structure includes:
frame N invalid integration time;
the frame is transferred to a charge discharging channel of the pixel-like exposure control structure, and the channel is composed of an exposure grating, an exposure drain and an exposure barrier of the pixel-like exposure control structure;
the nth frame effective integration time;
transferring the frame to a storage area;
an nth frame read out is performed, and an n+1th frame invalid integration time is started at the same time as the nth frame read out.
3. A frame transfer CCD with a pixel-like exposure control structure according to claim 2, characterized by a frame period T frame For a period of time from the time of invalid integration of the current frame to the time of transition of the current frame to the memory area, the valid integration period of the current frame is T int If needed to realize T int =T frame In the charge integration and transfer process of the photosensitive area, the exposure gate controls the exposure barrier to be closed, N lines of signals after the integration of the photosensitive area are quickly transferred to the storage area, and each line of charge signals of the photosensitive area are subjected to the storage and transfer processes in the first vertical transfer gate and the second vertical transfer gate of the pixel-like exposure control structure.
4. A frame transfer CCD with a pixel-like exposure control structure according to claim 2, characterized by a frame period T frame For a period of time from the time of invalid integration of the current frame to the time of transition of the current frame to the memory area, the valid integration period of the current frame is T int If the n+1st frame signal needs to realize T int ＜T frame The method specifically comprises the following steps:
let it be assumed that at t 0 When the pixel is in an=0 state, the frame transfer process of the N-th frame signal is finished, the n+1-th frame signal starts to integrate the vertical transfer gate of the photosensitive area and is in an integrated level state, the vertical transfer gate of the pixel-like exposure control structure is biased to be in a low level, and the exposure gate is biased to be in a high level, so that an exposure barrier is opened;
at t=t frame -T int When the photosensitive region vertical transfer gate is in a frame transfer pulse level state, the vertical transfer gate and the exposure gate of the pixel-like exposure control structure still keep the level at the time t=0, so that the exposure barrier is opened, and the photosensitive region is at t 0 The charge signal generated by integration in t period is transferred under the action of driving pulse, and the exposure barrier is opened, so that at t 0 During the period of t, the charge signal generated by the integration of the frame transfer CCD with the pixel-like exposure control structure is discharged to the exposure drain, and the charge is emptied, so that the exposure control is realized;
then the vertical transfer gate of the photosensitive area is in an integration level state again, and the integration time of the photosensitive area is T int The vertical transfer gate of the pixel-like exposure control structure still maintains t 0 Time level, exposure gate bias changes to low level, so that exposure barrier is closed;
the photosensitive area has an integration time T int After the integration process of (2), a frame transfer process is carried out, and the vertical transfer gate of the pixel-like exposure control structure is from t 0 The time level changes into driving pulse, the exposure gate is biased into low level state, so that the exposure barrier is closed, and the photosensitive region is in T int The charge signal generated during the period does not enter the exposure drain due to the closing of the exposure barrier, but is rapidly transferred to the storage area until the output amplifier reads out the charge signal.
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