CN113889023B - Display panel driving method and display panel - Google Patents
Display panel driving method and display panel Download PDFInfo
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- CN113889023B CN113889023B CN202111275077.6A CN202111275077A CN113889023B CN 113889023 B CN113889023 B CN 113889023B CN 202111275077 A CN202111275077 A CN 202111275077A CN 113889023 B CN113889023 B CN 113889023B
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
The application is suitable for the technical field of display, and provides a driving method of a display panel and the display panel. The method comprises the steps of determining whether a current sub-pixel is a third sub-pixel in a second pixel according to a source electrode driving signal; if yes, acquiring a gray level difference between the current sub-pixel and a second sub-pixel of a second pixel adjacent to the current sub-pixel; calculating a voltage compensation value of a source driving signal according to the gray level difference, the parasitic capacitance and the capacitance of the current sub-pixel; the voltage compensation is carried out on the source electrode driving signal according to the voltage compensation value, the influence of the parasitic capacitance on the brightness of the current sub-pixel can be quantified by obtaining the gray level difference, the voltage compensation value of the source electrode driving signal is calculated by substituting the gray level difference, the voltage of the source electrode driving signal is increased in a targeted mode, the voltage consumed by the parasitic capacitance is neutralized, the brightness of the current sub-pixel is restored to normal brightness, and the vertical stripe phenomenon of the display panel is eliminated.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a driving method of a display panel and the display panel.
Background
With the rapid development of display technology, display panels are widely used in various fields such as entertainment, education, security, etc., and the display effect requirements of users on the display panels are gradually increased. The Dual Gate (Dual Gate) architecture reduces the number of Source Driver circuits (Source Driver ICs) required for the display panel by half by doubling the number of Gate Driver circuits (Gate Driver ICs), and reduces the production cost of the Source Driver circuits by reducing the number of Source Driver circuits, thereby increasing the screen ratio of the Source Driver circuits in the display panel.
In the dual-gate architecture, one data line is connected with two pixels in the same row, and the interval distance between the two pixels in the same row is too short, so that parasitic capacitance is easily formed at the interval, any one of the two pixels affected by the coupling action of the parasitic capacitance can be caused when the pixel is charged, the driving voltage of the affected pixel is reduced, and therefore the brightness is reduced.
Disclosure of Invention
In view of the above, embodiments of the present application provide a driving method of a display panel and a display panel, so as to solve the problems that in the existing dual-gate architecture, the affected pixels are subjected to the coupling effect of parasitic capacitance during charging, so that the driving voltage of the affected pixels is reduced, and the brightness is reduced, and one data line is connected to a plurality of rows of pixels, so that the brightness of a plurality of rows of pixels in a same row is reduced, and a vertical stripe phenomenon is formed on the display panel, so as to affect the display effect.
A first aspect of an embodiment of the present application provides a driving method of a display panel, including:
determining whether the current sub-pixel is a third sub-pixel in the second pixel according to the source driving signal and the gate driving signal;
if the current sub-pixel is a third sub-pixel in the second pixels, acquiring the gray level difference between the current sub-pixel and the second sub-pixels of the second pixels adjacent to the current sub-pixel;
calculating a voltage compensation value of the source driving signal according to the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the parasitic capacitance and the capacitance of the current sub-pixel;
And performing voltage compensation on the source electrode driving signal according to the voltage compensation value so as to improve the brightness of the current sub-pixel.
A second aspect of an embodiment of the present application provides a display panel including a memory, a processor, a computer program stored in the memory and executable on the processor;
the memory is connected to the processor, and the processor executes the computer program to implement the steps of the driving method for the display panel provided in the first aspect of the embodiment of the present application.
According to the driving method of the display panel, the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel is obtained, the influence of parasitic capacitance on the brightness of the current sub-pixel can be quantified, the gray level difference is substituted into the calculated voltage compensation value of the source driving signal, the voltage of the source driving signal is increased in a targeted manner, the voltage consumed by the parasitic capacitance is neutralized, the brightness of the current sub-pixel can be restored to normal brightness, and the vertical stripe phenomenon of the display panel is eliminated.
It will be appreciated that the advantages of the second aspect may be found in the relevant description of the first aspect, and will not be described in detail herein.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to a first embodiment of the present application;
fig. 2 is a schematic diagram of a pixel structure of a display panel according to a first embodiment of the application;
fig. 3 is a flowchart illustrating a driving method of a display panel according to a second embodiment of the application;
fig. 4 is a flowchart of a driving method of a display panel according to a third embodiment of the present application;
reference numerals:
a display panel: 1, a step of; a memory 11; a processor: 12; a computer program 13; a first pixel: 110; a second pixel: 120; a first sub-pixel: 111. 121; a second sub-pixel: 112. 122, a step of; third sub-pixel: 113. 123, a step of; a first scan line: 210; a second scan line: 220; a first data line: 310; a second data line: 320. Third data line: 330; an electronic switch: 400; parasitic capacitance: 124.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Example 1
As shown in fig. 1, a schematic structural diagram of a display panel 1 according to a first embodiment of the present application is provided, where the display panel 1 includes a memory 11, a processor 12, and a computer program 13 stored in the memory 11 and executable on the processor 12;
The memory 11 is connected to the processor 12, and the processor 12 executes the computer program 13 to realize the steps of the driving method of the display panel corresponding to fig. 3 and 4 described below.
In application, the display panel may be a liquid crystal display panel based on TFT-LCD (Thin Film Transistor Liquid Crystal Display ) technology, a liquid crystal display panel based on LCD (Liquid Crystal Display ) technology, an Organic Light-Emitting Diode (OLED) technology-based Organic electro-mechanical laser display panel, a quantum dot Light-Emitting Diode (qde) display panel based on qde (Quantum Dot Light Emitting Diodes) technology, or a curved display panel.
In application, the display panel can be mounted on any type of equipment with display function, such as a display, a television, a notebook computer, a tablet computer, a multimedia advertisement machine, an electronic billboard and the like.
In application, the display panel may include, but is not limited to, a processor, a memory, a computer program stored in the memory that can run on the processor, and a display panel. It will be appreciated by those skilled in the art that fig. 1 is merely an example of a display panel and is not intended to be limiting, and may include more or fewer components than shown, or may combine certain components, or different components, such as may also include input and output devices, network access devices, etc.
In applications, the processor may be a timing controller (Timer Control Register, TCON) or a Chip on Chip (SOC) or a central processing unit (Central Processing Unit, CPU), which may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
In applications, the memory may in some embodiments be an internal storage unit of the display panel, such as a hard disk or a memory of the display panel. The memory may also be an external storage device of the display panel in other embodiments, such as a plug-in hard disk provided on the display panel, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), etc. Further, the memory may also include both an internal storage unit of the display panel and an external storage device. The memory is used to store an operating system, application programs, boot loader (bootloader), data, and other programs, etc., such as program code for a computer program, etc. The memory may also be used to temporarily store data that has been output or is to be output.
As shown in fig. 2, based on the schematic structural diagram of the display panel 1 provided in fig. 1, the display panel 11 includes i scan lines, u scan lines, i×u/6 first pixels and i×u/6 second pixels, the first pixels and the second pixels are arranged in an array form and are arranged at intervals in a row direction, each first pixel includes a first sub-pixel, a second sub-pixel and a third sub-pixel sequentially arranged in the row direction, each second pixel includes a first sub-pixel, a second sub-pixel and a third sub-pixel sequentially arranged in the row direction, and i, u is a positive integer;
the first sub-pixels 111 and 121 in the first pixel 110 and the second pixel 120 disposed at an arbitrary row interval are electrically connected to the first scan line 210, the second sub-pixels 112 and 122 are electrically connected to the second scan line 220, the third sub-pixel 113 in the first pixel 110 is electrically connected to the second scan line 220, the third sub-pixel 113 in the second pixel 120 is electrically connected to the first scan line 210, the first sub-pixel 111 and the second sub-pixel 121 in the first pixel 110 are electrically connected to the first data line 310, the third sub-pixel 113 is electrically connected to the second data line 320, the first sub-pixel 121 in the second pixel 120 is electrically connected to the second data line 320, and the second sub-pixel 122 and the third sub-pixel 123 are electrically connected to the third data line 330.
It should be noted that fig. 2 only illustrates two sets of adjacent first pixels 110 and second pixels 120, each row of pixels is formed by multiple sets of adjacent first pixels and second pixels, and the array structure of the display panel is formed by multiple rows of pixels.
In application, the colors of the first sub-pixels 111, 121, the second sub-pixels 112, 122 and the third sub-pixels 113, 123 in the first pixel and/or the second pixel may be different from each other to display different colors when being lightened, and specifically, the first sub-pixels 111, 121, the second sub-pixels 112, 122 and the third sub-pixels 113, 123 may be Red sub-pixels, green sub-pixels and Blue sub-pixels, respectively, to form an RGB Color Mode (Red-Green-Blue Color Mode). For example, the first sub-pixels 111, 121 are red sub-pixels, the second sub-pixels 112, 122 are green sub-pixels, and the third sub-pixels 113, 123 are blue sub-pixels; alternatively, the first sub-pixels 111 and 121 are green sub-pixels, the second sub-pixels 112 and 122 are red sub-pixels, and the third sub-pixels 113 and 123 are blue sub-pixels. In addition, the first sub-pixels 111, 121 in the first pixel 110 and the second pixel 120 are the same in color, the second sub-pixels 112, 122 in the first pixel 110 and the second pixel 120 are the same in color, and the third sub-pixels 113, 123 in the first pixel 110 and the second pixel 120 are the same in color. The specific colors of the first sub-pixels 111, 121, the second sub-pixels 112, 122 and the third sub-pixels 113, 123 in the first pixel 110 and/or the second pixel 120 are not limited in the embodiments of the present application.
In application, the polarity of any one sub-pixel when turned on is determined according to the polarity of the source driving signal output by the connected data line, and the polarities of the source driving signals output by the adjacent data lines are opposite, for example (as shown in fig. 2), the first data line 310 outputs a source driving signal of positive polarity, the second data line 320 outputs a source driving signal of negative polarity, and the third data line 330 outputs a source driving signal of positive polarity.
In application, each sub-pixel is electrically connected with the data line and the scanning line through the electronic switch 400, and the electronic switch 400 is used for being turned on when receiving the gate driving signal output by the scanning line, and is also used for receiving the source driving signal output by the data line and sending the source driving signal to the sub-pixel; the electronic switch 400 is also configured to turn off when the gate driving signal output from the scan line is not received, and stop sending the source driving signal to the sub-pixel. The electronic switch 400 may control each sub-pixel to be turned on or off according to whether a gate driving signal is received. Wherein the electronic switch 400 may be a triode or a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), in particular a thin film field effect transistor (Thin Film Transistor, TFT)
In one embodiment, a parasitic capacitance 124 is connected between the second sub-pixel 122 and the third sub-pixel 123 in the second pixel 120.
In the application, taking a group of adjacent first pixels 110 and second pixels 120 as an example, the parasitic capacitance 124 connected between the second sub-pixels 122 and the third sub-pixels 123 in the second pixels 120 causes the driving voltage of the third sub-pixels 123 in the second sub-pixels 120 to decrease, thereby causing the brightness to decrease, and further causing the brightness of the pixels in the same row to decrease, and the reason for the moire phenomenon formed on the display panel will be described below:
in the first period, the first scan line 210 outputs the gate driving signal, and the first data line 310, the second data line 320, and the third data line 330 sequentially output the source driving signal according to the control of the processor, the first sub-pixels 111 and 121 in the first pixel 110 and the second pixel 120 are charged and turned on, and the third sub-pixel 123 in the second pixel 120 is charged and turned on;
in the second period, the second scan line 220 outputs the gate driving signal, and the first, second and third data lines 310, 320, 330 sequentially output the source driving signal according to the control of the processor, the second sub-pixels 112, 122 in the first and second pixels 110, 120 are charged and turned on, and the third sub-pixel 123 in the third pixel 120 is charged and turned on;
Any two sub-pixels connected on the same data line, due to the fact that the interval distance is too short, parasitic capacitance is easy to form at the interval, so that when one sub-pixel of the any two sub-pixels is charged firstly through a source driving signal, the source driving signal is consumed to charge the parasitic capacitance at the same time, the driving voltage of one sub-pixel of the any two sub-pixels is reduced, brightness is reduced, the first sub-pixels 111 and 121 of the first pixel 110 and the second pixel 120 are charged and lightened in the same time period (first time period), and even if the brightness is reduced, the brightness of the two first sub-pixels 111 and 121 is kept consistent; the second sub-pixels 112, 122 in the first pixel 110 and the second pixel 120 are also charged and lighted in the same period of time (second period of time) in which the parasitic capacitance is fully charged, and the brightness of the two second sub-pixels 112, 122 is normal and kept uniform;
and the third sub-pixel 123 in the second pixel 120 is charged and turned on in the first period, the brightness is reduced, the third sub-pixel 113 in the first pixel 110 is charged and turned on in the second period, the brightness is normal, the brightness of the third sub-pixel 123 with the same color is lower than that of the third sub-pixel 113, and under the array structure of the display panel, the brightness of the third sub-pixel 123 in the same column is lower than that of the third sub-pixel 113 in the adjacent column, so that the moire phenomenon is formed on the display panel.
It should be noted that, fig. 2 illustrates an array structure of a display panel that may form a moire phenomenon on the display panel, and in a display panel adopting a dual-gate architecture, when charging periods of sub-pixels of any one or more colors located in the same row are different, the sub-pixel that is charged first is easily affected by parasitic capacitance to make brightness lower than that of the sub-pixel that is charged later, so that the moire phenomenon is formed on the display panel. The second and third embodiments described below provide a driving method based on the array structure of the display panel shown in the first embodiment, so as to eliminate the moire phenomenon formed on the display panel.
It should be noted that, because the content of information interaction and execution process between the above devices/modules is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein.
Example two
According to the driving method of the display panel realized based on the structure of the display panel in the first embodiment, the influence of parasitic capacitance on the brightness of the current sub-pixel can be quantified by acquiring the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, and the gray level difference is substituted into the calculated voltage compensation value of the source driving signal, so that the voltage of the source driving signal is increased in a targeted manner, the voltage consumed by the parasitic capacitance is neutralized, the brightness of the current sub-pixel can be restored to normal brightness, and the vertical stripe phenomenon of the display panel is eliminated.
As shown in fig. 3, a driving method of a display panel according to a second embodiment of the present application is applied to a display panel, and includes steps S301 to S304 as follows:
step S301, determining whether the current sub-pixel is the third sub-pixel in the second pixel according to the source driving signal and the gate driving signal.
In application, the processor (specifically, the timing controller) outputs a source driving signal by controlling one data line, and outputs a gate driving signal by controlling one scan line, so that a current sub-pixel connected to the one data line and the one scan line is charged and turned on. The processor may determine a specific position of the current sub-pixel in the display panel according to a serial number of the data line through which the source driving signal flows and a serial number of the scan line through which the gate driving signal flows, so as to determine whether the current sub-pixel is a third sub-pixel in the second pixel.
In application, each row of pixels of the display panel comprises a plurality of groups of first pixels and second pixels, the first pixels and the second pixels are arranged at intervals, and the positions of the first pixels and the second pixels in the display panel can be determined according to the array structure of the display panel.
Specifically, whether the sub-pixel of any column of the display panel is the sub-pixel of the first pixel (or the second pixel) can be determined, for example, when the sub-pixel of the first column of the display panel is the sub-pixel of the first pixel, the sub-pixel of the 6k-2 column, the sub-pixel of the 6k-1 column and the sub-pixel of the 6k column of the display panel are the first sub-pixel, the second sub-pixel and the third sub-pixel of the second pixel respectively, and the sub-pixel of the 6k-5 column, the 6k-4 column and the sub-pixel of the 6k-3 column of the display panel are the first sub-pixel, the second sub-pixel and the third sub-pixel of the first pixel respectively; or when the first column of the display panel is the sub-pixel of the second pixel, the 6k-2 th column, the 6k-1 th column and the 6k th column of the display panel are the first sub-pixel, the second sub-pixel and the third sub-pixel of the first pixel respectively, and the 6k-5 th column, the 6k-4 th column and the 6k-3 th column of the display panel are the first sub-pixel, the second sub-pixel and the third sub-pixel of the second pixel respectively. Wherein k is a positive integer.
In one embodiment, step S301 includes:
determining the column sequence number of the current sub-pixel according to the source electrode driving signal and the grid electrode driving signal;
and determining whether the current sub-pixel is a third sub-pixel in the second pixel according to the column serial number of the current sub-pixel.
In an application, the processor may determine the column number of the current subpixel according to the number of the data line through which the source driving signal flows and the number of the scan line through which the gate driving signal flows.
In application, when the 6 k-th column sub-pixel of the display panel is the third sub-pixel of the second pixel, judging whether the column number of the current sub-pixel belongs to 6k, if so, determining that the current sub-pixel is the third sub-pixel of the second pixel, and if not, determining that the current sub-pixel is not the third sub-pixel of the second pixel; or when the 6k-3 th column sub-pixel of the display panel is the third sub-pixel of the second pixel, judging whether the column serial number of the current sub-pixel belongs to 6k-3, if so, determining that the current sub-pixel is the third sub-pixel of the second pixel, and if not, determining that the current sub-pixel is not the third sub-pixel of the second pixel.
In one embodiment, after step S301, it includes:
if the current sub-pixel is not the third sub-pixel in the second pixel, the current sub-pixel is driven by the source driving signal.
In application, if the current sub-pixel is not the third sub-pixel in the second pixel, the brightness of the current sub-pixel and the sub-pixel with the same color as the current sub-pixel in the same row can be kept consistent, no vertical stripe phenomenon can be formed on the display panel, and the current sub-pixel can be directly driven by the source driving signal.
Step S302, if the current sub-pixel is the third sub-pixel in the second pixel, the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel is obtained.
In application, after determining that the current sub-pixel is the third sub-pixel in the second pixel, it is explained that the current sub-pixel is susceptible to parasitic capacitance, resulting in a reduction of the driving voltage, and thus resulting in a sub-pixel of the same color, i.e. the third sub-pixel in the first pixel, that is lower in brightness than the post-charge of the same row.
In application, the gray level of the current sub-pixel can be obtained when the current sub-pixel is lightened, the gray level of the second sub-pixel of the second pixel adjacent to the current sub-pixel can be obtained when the second sub-pixel of the second pixel adjacent to the current sub-pixel is lightened, and the gray level of the second sub-pixel of the second pixel adjacent to the current sub-pixel is subtracted from the gray level of the current sub-pixel to obtain the gray level difference. It should be noted that, the gray level of the second sub-pixel of the second pixel adjacent to the current sub-pixel reflects the gray level when the brightness of the current sub-pixel is normal, so the influence of the parasitic capacitance on the brightness of the current sub-pixel can be quantified according to the calculated gray level difference.
In one embodiment, step S302 includes:
if the current sub-pixel is the third sub-pixel in the second pixel, acquiring the gray level of the current sub-pixel and the gray level of the second sub-pixel of the second pixel adjacent to the current sub-pixel through the image measuring instrument;
the gray level difference between the current sub-pixel and a second sub-pixel of a second pixel adjacent to the current sub-pixel is obtained.
In an application, the image measuring instrument (Image Measuring Instrument) may include an image capturing device and an image analysis module, and when the display panel displays a picture, the image measuring instrument may capture the picture of each frame displayed by the display panel through the image capturing device, analyze the picture of each frame through the image analysis module, detect the gray level of the picture of each frame, and may locate the gray level of each pixel in the picture of each frame.
In application, the gray scale of the current sub-pixel and the gray scale of the second sub-pixel of the second pixel adjacent to the current sub-pixel can be obtained through the image measuring instrument, and the gray scale difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel is calculated through the processor.
In one embodiment, step S302 includes:
if the current sub-pixel is the third sub-pixel in the second pixel, the gray scale of the current sub-pixel and the gray scale of the second sub-pixel of the second pixel adjacent to the current sub-pixel are read by the processor.
In an application, the processor may specifically be a timing controller, where the timing controller may read the gray information in the source driving signal when outputting the source driving signal, so as to determine a first preset gray of the current subpixel and a second preset gray of a second subpixel of a second pixel adjacent to the current subpixel. It should be noted that, the brightness of the second sub-pixel of the second pixel adjacent to the current sub-pixel is normal when the second sub-pixel is lighted, so that the gray level of the second sub-pixel of the second pixel adjacent to the current sub-pixel is equal to the first preset gray level; and the brightness of the current sub-pixel is reduced when the current sub-pixel is lightened, and the gray level of the current sub-pixel is smaller than the second preset gray level.
In application, the timing controller can acquire the voltage value on the current sub-pixel after the current sub-pixel is lightened, and determine the gray level of the current sub-pixel according to the voltage value on the current sub-pixel, so as to avoid acquiring the gray level information with errors according to the source driving signal.
Step S303, calculating the voltage compensation value of the source driving signal according to the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the parasitic capacitance and the capacitance of the current sub-pixel.
In one embodiment, the calculation formula for calculating the voltage compensation value of the source driving signal in step S303 is as follows:
Gain＝ΔLv*C p2p3 /C p3 ；
wherein Gain represents a voltage compensation value of the source driving signal, deltaLv represents a gray scale difference between the current sub-pixel and a second sub-pixel of a second pixel adjacent to the current sub-pixel, C p2p3 Representing a parasitic capacitance value between the current subpixel and a second subpixel of a second pixel adjacent to the current subpixel, C p3 Representing the capacitance value of the current sub-pixel.
In application, the capacitance of the current sub-pixel is determined according to the actual type of the third sub-pixel of the second pixel; the parasitic capacitance between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel may be obtained by table lookup, specifically, before calculating the voltage compensation value of the source driving signal, the parasitic capacitance value between the third sub-pixel and the second sub-pixel in each second pixel of the display panel may be detected, and a table corresponding to each second pixel and the parasitic capacitance value may be formed.
In the application, the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel is substituted into calculation, and the voltage compensation value of the source driving signal can be calculated according to the influence of the parasitic capacitance on the brightness of the current sub-pixel.
In one embodiment, prior to step S303, comprising:
and determining a parasitic capacitance value between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel according to the interval distance between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the resistance-capacitance parameter of the current sub-pixel and the resistance-capacitance parameter of the second sub-pixel of the second pixel adjacent to the current sub-pixel.
In application, the resistance-capacitance parameter may include a resistance value, a capacitance value, an inductance value, and the like. The resistance-capacitance parameter of the current sub-pixel is determined according to the actual selection type of the third sub-pixel of the second pixel, and the resistance-capacitance parameter of the second sub-pixel of the second pixel adjacent to the current sub-pixel is determined according to the actual selection type of the second sub-pixel of the second pixel. In general, the smaller the separation distance between the current subpixel and the second subpixel of the second pixel adjacent to the current subpixel, the larger the parasitic capacitance value. When driving different display panels, the parasitic capacitance value between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel can be determined according to the interval distance between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the resistance-capacitance parameter of the current sub-pixel and the resistance-capacitance parameter of the second sub-pixel of the second pixel adjacent to the current sub-pixel.
Step S304, performing voltage compensation on the source driving signal according to the voltage compensation value to improve the brightness of the current sub-pixel.
In application, the processor can add the calculated voltage compensation value with the initial voltage of the source driving signal, compensate the voltage of the source driving signal, improve the brightness of the current sub-pixel, and enable the brightness of the current sub-pixel, which is reduced due to the influence of parasitic capacitance, to be restored to normal brightness, so as to eliminate the vertical stripe phenomenon of the display panel.
According to the driving method of the display panel provided by the second embodiment of the application, whether the current sub-pixel is the third sub-pixel in the second pixel is determined according to the source driving signal and the gate driving signal; if the current sub-pixel is a third sub-pixel in the second pixels, acquiring the gray level difference between the current sub-pixel and the second sub-pixels of the second pixels adjacent to the current sub-pixel; calculating a voltage compensation value of a source driving signal according to the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the parasitic capacitance and the capacitance of the current sub-pixel; the voltage compensation is carried out on the source electrode driving signal according to the voltage compensation value, the influence of the parasitic capacitance on the brightness of the current sub-pixel can be quantified by obtaining the gray level difference, the voltage compensation value of the source electrode driving signal is calculated by substituting the gray level difference, the voltage of the source electrode driving signal is increased in a targeted mode, the voltage consumed by the parasitic capacitance is neutralized, the brightness of the current sub-pixel can be restored to normal brightness, and the vertical line phenomenon of the display panel is eliminated.
Example III
As shown in fig. 4, the third embodiment provided in the present application, based on the second embodiment corresponding to fig. 3, includes the following steps S401 to S410:
step S401, determining whether the current sub-pixel is a third sub-pixel in the second pixel according to the source driving signal and the gate driving signal;
step S402, if the current sub-pixel is a third sub-pixel in the second pixel, acquiring a gray level difference between the current sub-pixel and a second sub-pixel of a second pixel adjacent to the current sub-pixel;
step S403, calculating a voltage compensation value of the source driving signal according to the gray level difference, the parasitic capacitance and the capacitance of the current sub-pixel between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel.
In application, the steps S401 to S403 are consistent with the driving method provided in the steps S301 to S303 in the second embodiment, and are not described herein.
Step S404, determining the serial number of the third data line electrically connected with the current sub-pixel and the serial number of the first scanning line electrically connected with the current sub-pixel according to the source driving signal and the gate driving signal.
In application, the processor may determine the sequence number of the third data line electrically connected to the current sub-pixel according to the sequence number of the data line through which the source driving signal flows, and may determine the sequence number of the first scan line electrically connected to the current sub-pixel according to the sequence number of the scan line through which the gate driving signal flows.
Step S405, determining a vertical area where the third data line electrically connected to the current sub-pixel is located according to the serial number of the third data line electrically connected to the current sub-pixel.
In application, the display panel comprises i scanning lines and u data lines, the i scanning lines are sequentially divided into n horizontal areas according to the serial numbers of the scanning lines, the u data lines are sequentially divided into m vertical areas according to the serial numbers of the data lines, each horizontal area comprises i/n scanning lines, each vertical area comprises u/m data lines, i, n, u and m are positive integers, n is smaller than or equal to i, and m is smaller than or equal to u.
In application, according to the serial number of the third data line electrically connected with the current sub-pixel, the calculation formula for determining the vertical area where the third data line electrically connected with the current sub-pixel is located is as follows:
wherein V represents the serial number of the vertical region where the third data line electrically connected with the current sub-pixel is located, columb u A serial number indicating a third data line electrically connected to the current sub-pixel, m indicating the number of vertical regions,represent the Column u Dividing the result by m to be rounded upwards; column u ∈[1，u]。
Step S406, determining a horizontal area where the first scan line electrically connected to the current sub-pixel is located according to the serial number of the first scan line electrically connected to the current sub-pixel.
In the application, according to the serial number of the first scanning line electrically connected with the current sub-pixel, the calculation formula for determining the horizontal area where the first scanning line electrically connected with the current sub-pixel is located is as follows:
wherein H represents the serial number of the horizontal region where the first scanning line electrically connected with the current sub-pixel is located, row i A serial number representing a first scan line electrically connected to the current sub-pixel, n representing the number of horizontal regions,representing the Row i The result divided by n is rounded up; row (Row) i ∈[1，i]。
Step S407, determining a compensation area where the current sub-pixel is located according to a vertical area where a third data line electrically connected with the current sub-pixel is located and a horizontal area where a first scanning line electrically connected with the current sub-pixel is located;
step S408, determining the compensation coefficient of the current sub-pixel according to the compensation area of the current sub-pixel.
In the application, according to m vertical areas and n horizontal areas, m×n compensation areas of an array may be formed, and according to the vertical area where the third data line electrically connected to the current subpixel is located and the horizontal area where the first scan line electrically connected to the current subpixel is located, the compensation area where the current subpixel is located may be determined, so as to determine the compensation coefficient of the current subpixel.
In application, the compensation coefficient of each compensation area may be different, specifically, each compensation area may set the compensation coefficient according to the resistance-capacitance parameter of the sub-pixel corresponding to the compensation area, and may also set the compensation coefficient according to the serial number of the data line connected to the sub-pixel corresponding to the compensation or the serial number of the scan line connected to the sub-pixel, and the specific compensation coefficient of each compensation area may be determined according to the actual driving requirement.
Step S409, calculating the voltage compensation value of the source driving signal according to the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the parasitic capacitance, the capacitance of the current sub-pixel and the compensation coefficient of the current sub-pixel.
In application, the calculation formula for calculating the voltage compensation value of the source driving signal is as follows:
Gain＝ΔLv*C p1p2 *CR HV /C p1 ；
wherein CR is HV Representing the compensation coefficient of the current sub-pixel.
In application, the difference of the positions of the sub-pixels in the display panel may cause different driving voltages, and the compensation coefficient of the current sub-pixel is substituted into the calculation of the voltage compensation value to realize regional compensation, so that the compensation coefficient of the calculated voltage compensation value can be adaptively adjusted according to the difference of the compensation regions, and the brightness of the current sub-pixel can be more accurately restored to normal brightness by the source driving signal after the voltage compensation.
Step S410, performing voltage compensation on the source driving signal according to the voltage compensation value to increase the brightness of the current sub-pixel.
In application, the processor can add the calculated voltage compensation value with the initial voltage of the source driving signal, compensate the voltage of the source driving signal, improve the brightness of the current sub-pixel, and enable the brightness of the current sub-pixel, which is reduced due to the influence of parasitic capacitance, to be restored to normal brightness, so as to eliminate the vertical stripe phenomenon of the display panel.
It should be noted that, the driving method of the display panel provided in the second embodiment and the third embodiment of the present application may be used for a display panel after leaving factory, so that the display panel performs self-detection on whether the vertical stripe phenomenon exists according to the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, and performs self-adaptive compensation on the source driving signal according to the voltage compensation value when the vertical stripe phenomenon is detected; the method can also be used for a display panel before delivery, so that the display panel can be debugged according to the driving method, voltage compensation values under different working conditions are obtained, the corresponding relation between the voltage compensation values and the working conditions is stored in a memory, and the display panel can obtain the corresponding voltage compensation values according to the working conditions after delivery so as to eliminate the vertical streak phenomenon of the display panel. The working conditions may include parameters such as a position of the current sub-pixel, a voltage of a source driving signal driving the current sub-pixel, a gray level difference between the current sub-pixel and a second sub-pixel of a second pixel adjacent to the current sub-pixel, and the like.
According to the driving method of the display panel provided by the embodiment of the application, the display panel is divided into the horizontal area and the vertical area to obtain the plurality of compensation areas, the corresponding compensation coefficients are set according to different compensation areas, the regional compensation is realized, the compensation coefficients of the voltage compensation value can be adaptively adjusted and calculated according to different compensation areas, and the brightness of the current sub-pixel can be more accurately recovered to the normal brightness by the source driving signal after the voltage compensation.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed terminal device and method may be implemented in other manners. For example, the above-described embodiments of the terminal device are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or modules, which may be in electrical, mechanical or other forms.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (6)
1. A driving method of display panel is characterized in that the display panel comprises i scanning lines, u scanning lines, i/u/6 first pixels and i/u/6 second pixels, the first pixels and the second pixels are arranged in an array form and are arranged at intervals in a row direction, each first pixel comprises a first sub-pixel, a second sub-pixel and a third sub-pixel which are sequentially arranged in the row direction, each second pixel comprises a first sub-pixel, a second sub-pixel and a third sub-pixel which are sequentially arranged in the row direction, the driving method of the display panel comprises the steps that a first sub-pixel in a first pixel and a second pixel which are arranged at any row interval is electrically connected with a first scanning line, a second sub-pixel in the first pixel is electrically connected with a second scanning line, a third sub-pixel in the second pixel is electrically connected with the first scanning line, the first sub-pixel in the first pixel and the second sub-pixel in the first pixel are electrically connected with a first data line, the third sub-pixel in the first pixel is electrically connected with a second data line, the first sub-pixel in the second pixel is electrically connected with a second data line, the second sub-pixel in the third sub-pixel in the second pixel is electrically connected with a third data line, i and u are positive integers, and the driving method of the display panel comprises the following steps:
Determining whether the current sub-pixel is a third sub-pixel in the second pixel according to the source driving signal and the gate driving signal;
if the current sub-pixel is a third sub-pixel in the second pixels, acquiring the gray level difference between the current sub-pixel and the second sub-pixels of the second pixels adjacent to the current sub-pixel;
calculating a voltage compensation value of the source driving signal according to the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the parasitic capacitance and the capacitance of the current sub-pixel;
performing voltage compensation on the source electrode driving signal according to the voltage compensation value so as to improve the brightness of the current sub-pixel;
the calculating the voltage compensation value of the source driving signal according to the gray level difference, the parasitic capacitance and the capacitance of the current sub-pixel between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel includes:
calculating a voltage compensation value of the source driving signal according to the gray level difference between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the parasitic capacitance, the capacitance of the current sub-pixel and the compensation coefficient of the current sub-pixel;
The i scanning lines of the display panel are sequentially divided into n horizontal areas according to the serial numbers of the scanning lines, the u data lines are sequentially divided into m vertical areas according to the serial numbers of the data lines, each horizontal area comprises i/n scanning lines, each vertical area comprises u/m data lines, n and m are positive integers, n is smaller than or equal to i, and m is smaller than or equal to u;
before calculating the voltage compensation value of the source driving signal according to the gray level difference, the parasitic capacitance, the capacitance of the current sub-pixel and the compensation coefficient of the current sub-pixel between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the method comprises:
determining a serial number of a third data line electrically connected with the current sub-pixel and a serial number of a first scanning line electrically connected with the current sub-pixel according to the source driving signal and the gate driving signal;
determining a vertical area where a third data line electrically connected with the current sub-pixel is located according to a serial number of the third data line electrically connected with the current sub-pixel;
determining a horizontal area where a first scanning line electrically connected with the current sub-pixel is located according to a serial number of the first scanning line electrically connected with the current sub-pixel;
Determining a compensation area where the current sub-pixel is located according to a vertical area where the third data line electrically connected with the current sub-pixel is located and a horizontal area where the first scanning line electrically connected with the current sub-pixel is located;
determining a compensation coefficient of the current sub-pixel according to the compensation area of the current sub-pixel;
the formula for calculating the voltage compensation value of the source driving signal according to the gray level difference, the parasitic capacitance, the capacitance of the current sub-pixel and the compensation coefficient of the current sub-pixel between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel is as follows:
；
wherein Gain represents a voltage compensation value of the source driving signal,representing the current sub-pixelGray level difference between second sub-pixels of second pixels adjacent to the current sub-pixel,/v>A parasitic capacitance value between the current sub-pixel and a second sub-pixel of a second pixel adjacent to the current sub-pixel, < >>Compensation coefficient representing the current sub-pixel, +.>Representing the capacitance value of the current sub-pixel.
2. The method of driving a display panel according to claim 1, wherein determining whether the current sub-pixel is the third sub-pixel of the second pixel according to the source driving signal and the gate driving signal comprises:
Determining the column sequence number of the current sub-pixel according to the source electrode driving signal and the grid electrode driving signal;
and determining whether the current sub-pixel is a third sub-pixel in the second pixel according to the column serial number of the current sub-pixel.
3. The driving method of a display panel according to claim 1, wherein before calculating the voltage compensation value of the source driving signal according to a gray level difference between the current sub-pixel and a second sub-pixel of a second pixel adjacent to the current sub-pixel, a parasitic capacitance, and a capacitance value of the current sub-pixel, comprising:
and determining a parasitic capacitance value between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel according to the interval distance between the current sub-pixel and the second sub-pixel of the second pixel adjacent to the current sub-pixel, the resistance-capacitance parameter of the current sub-pixel and the resistance-capacitance parameter of the second sub-pixel of the second pixel adjacent to the current sub-pixel.
4. The method for driving a display panel according to claim 1, wherein the calculation formula for determining the vertical area where the third data line electrically connected to the current sub-pixel is located according to the serial number of the third data line electrically connected to the current sub-pixel is:
；
Wherein V represents the serial number of the vertical area where the third data line electrically connected with the current sub-pixel is located,a serial number indicating a third data line electrically connected to the current sub-pixel, m indicating the number of vertical regions,the representation will->Dividing the result by m to be rounded upwards; />；
According to the serial number of the first scanning line electrically connected with the current sub-pixel, determining a calculation formula of a horizontal area where the first scanning line electrically connected with the current sub-pixel is located is as follows:
；
wherein H represents the serial number of the horizontal area where the first scanning line electrically connected with the current sub-pixel is located,a serial number indicating a first scan line electrically connected to the current sub-pixel, n indicating the number of horizontal regions, +.>The representation will->The result divided by n is rounded up; />。
5. A display panel comprising a memory, a processor, a computer program stored in the memory and executable on the processor;
the memory is connected to the processor, which when executing the computer program, implements the steps of the method for driving a display panel according to any one of claims 1 to 4.
6. The display panel according to claim 5, wherein the display panel includes i scan lines, u scan lines, i x u/6 first pixels and i x u/6 second pixels, the first pixels and the second pixels are arranged in an array, and are arranged at intervals in a row direction, each of the first pixels includes a first subpixel, a second subpixel and a third subpixel sequentially arranged in the row direction, each of the second pixels includes a first subpixel, a second subpixel and a third subpixel sequentially arranged in the row direction, a first subpixel and a second subpixel located in any one of the first pixels and the second pixels arranged at intervals are electrically connected to the first scan line, a third subpixel and the second scan line are electrically connected to the second scan line, a third subpixel and the third subpixel are electrically connected to the first scan line, a first subpixel and the second data line are electrically connected to the second data line, and a third subpixel and the third data line are electrically connected to the third data line, and a positive data line are electrically connected to the third subpixel.
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