CN113568231B - Array substrate, display panel and electronic equipment - Google Patents
Array substrate, display panel and electronic equipment Download PDFInfo
- Publication number
- CN113568231B CN113568231B CN202111096466.2A CN202111096466A CN113568231B CN 113568231 B CN113568231 B CN 113568231B CN 202111096466 A CN202111096466 A CN 202111096466A CN 113568231 B CN113568231 B CN 113568231B
- Authority
- CN
- China
- Prior art keywords
- hole area
- camera
- line
- lines
- array substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 100
- 230000003247 decreasing effect Effects 0.000 claims description 17
- 239000004973 liquid crystal related substance Substances 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- 238000003384 imaging method Methods 0.000 description 41
- 230000002829 reductive effect Effects 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 230000007423 decrease Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000036961 partial effect Effects 0.000 description 8
- 239000010408 film Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The application discloses array substrate, display panel and electronic equipment. The array substrate comprises a substrate, scanning lines and data lines, wherein the scanning lines and the data lines are vertically arranged in a staggered manner, the substrate is provided with a camera hole area, the scanning lines partially surrounding the camera hole area are set as first scanning lines, the scanning lines not surrounding the camera hole area are set as second scanning lines, the data lines surrounding the camera hole area are set as first data lines, and the scanning lines not surrounding the camera hole area are set as second data lines; in the direction from the edge of the camera shooting hole area to the center of the camera shooting hole area, the width of the part of the first data line and/or the first scanning line surrounding the camera shooting hole area is increased. The array substrate of the technical scheme of the application is through widening the district section of scanning line and data line at the camera shooting hole region to the compensation is because of the line length of walking that the camera shooting hole region occupied and increase and the pixel quantity that reduces, and then guarantees that the resistance and the capacitive load of each position are the same, solves and shows uneven problem.
Description
Technical Field
The present application relates to the field of display device technologies, and in particular, to an array substrate, a display panel, and an electronic device.
Background
Nowadays, mobile electronic devices have become an indispensable part of people's daily life, such as smart phones, tablet computers, and the like. Generally, these electronic devices have a photographing function, including a front camera and a rear camera. And along with the popularity of extremely narrow frame design, some products have accomplished inside the display screen with leading Camera, dig the hole screen promptly or the design of drop screen, to the mobile electronic device who uses Liquid Crystal Display (LCD), in order to guarantee the function of shooing not influenced, can not have the metal to walk the line around the glass Camera hole (Camera hole) of the array base plate side of liquid crystal display, the hole of making a video recording need be avoided to the metal wiring promptly.
At present, in mobile electronic devices using liquid crystal display screens in the market, metal wires at the positions of camera holes are all equal in line width, and the metal wires at the periphery of the camera holes are longer than those at the positions of non-camera holes, so that the load of capacitance resistors is not uniform, and the problem of uneven display is easy to occur.
Disclosure of Invention
The main purpose of this application is to provide an array substrate, through the metal of camera hole department and incision department to array substrate walk the line and design, make the metal of camera hole position walk the line and walk the line with other metals and have unanimous load value to solve the different uneven problem that leads to showing of load.
In order to achieve the above purpose, the array substrate provided by the present application includes a substrate, and a plurality of scan lines and a plurality of data lines arranged in parallel and arranged on the substrate, wherein each scan line and each data line are vertically staggered, and the substrate is provided with a camera hole region;
at least two parts of the data lines are arranged around the camera hole area, at least two parts of the scanning lines are arranged around the camera hole area, the scanning lines partially surrounding the camera hole area are set as first scanning lines, the scanning lines not surrounding the camera hole area are set as second scanning lines, the data lines surrounding the camera hole area are set as first data lines, and the scanning lines not surrounding the camera hole area are set as second data lines;
in the direction from the edge of the camera shooting hole area to the center of the camera shooting hole area, the width of the part of the first data line and/or the first scanning line surrounding the camera shooting hole area is increased gradually.
In an embodiment of the present application, when the shape of the camera hole area is a circle;
in the direction from the second scanning line to the center of the camera shooting hole area, the number of pixel units formed by two adjacent data lines and scanning lines is decreased progressively with a first tolerance and other tolerances;
and in the direction from the second data line to the center of the camera shooting hole area, the number of pixel units formed by two adjacent scanning lines and data lines is decreased progressively by a tolerance such as a second tolerance.
In an embodiment of the present application, in a direction from an edge of the camera hole area to a center thereof, a width of a portion of the first scan line surrounding the camera hole area is increased by a third tolerance, which is equal to the first tolerance.
In an embodiment of the present application, in a direction from an edge of the camera hole area to a center thereof, a width of the first data line is increased by a tolerance such as a fourth tolerance, wherein the fourth tolerance is equal to the second tolerance.
In an embodiment of the present application, when the shape of the camera hole region is a water drop type or a bang type;
in the extending direction of the data line from one end far away from the camera shooting hole area to the camera shooting hole area, the number of pixel units formed by two adjacent first scanning lines and the data line is decreased in a first unequal difference series;
and in the direction from the second scanning line to the center of the camera shooting hole area, the number of pixel units formed by two adjacent first data lines and scanning lines is decreased progressively by a second unequal difference number sequence.
In an embodiment of the present application, in a direction from the second data line to the camera hole area, a width of a portion of the first scan line surrounding the camera hole area is increased in a first unequal series.
In an embodiment of the present application, in a direction from an edge of the imaging aperture region to a center thereof, a width of a portion of the first data line surrounding the imaging aperture region is increased in a second unequal series.
In an embodiment of the application, each of the first scan lines includes two first straight line segments and a first arc line segment, two ends of the first arc line segment are respectively connected to the two first straight line segments, and the first arc line segment closest to the camera hole area and the edge of the camera hole area are arranged at intervals;
and/or each first data line comprises two second straight line segments and a second arc line segment, two ends of each second arc line segment are respectively connected with the two second straight line segments, and the second arc line segment closest to the camera hole area and the edge of the camera hole area are arranged at intervals.
The application further provides a display panel, which comprises a color film substrate, an array substrate and a liquid crystal layer, wherein the color film substrate and the array substrate are arranged in a box-to-box mode, and the array substrate is any one of the array substrates.
The application also provides an electronic device, the electronic device comprises a shell and a display panel arranged on the shell, and the display panel is the display panel.
In the technical scheme of the application, the array substrate comprises a substrate, and a data line and a scan line which are arranged on the substrate, wherein an image pick-up hole area is further arranged on the substrate, the data line and the scan line are arranged in a staggered manner in sequence, when the data line and the scan line pass through the image pick-up hole area, a part of a section of a first data line surrounds the image pick-up hole area, so that a section which normally forms pixels is reduced, a second data line is not affected by the image pick-up hole area and has a normal length, a part of a section of the first scan line surrounds the image pick-up hole area, so that a section which normally forms pixels is reduced, the length of the second scan line is normal, the surrounding length of the first scan line and the first data line which are closer to the image pick-up hole area is longer, the number of correspondingly formed pixel units is smaller, the corresponding resistance load is increased, the capacitance load is reduced, and thus, the width of the part of the first data line and/or the first scan line surrounding the image pick-up hole area is increased in the direction from the edge to the center of the image pick-up hole area, that is, the resistive load of the first data line and/or the first scan line is reduced, and the capacitive load of the first data line and/or the first scan line is increased, so that the lost pixel load is compensated, the load difference of different areas of the array substrate is effectively reduced, and the display quality is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present disclosure;
FIG. 2 is a layout diagram of pixel cells in the array substrate shown in FIG. 1;
FIG. 3 is a partially enlarged schematic view of a scan line in the array substrate shown in FIG. 1;
fig. 4 is a partially enlarged schematic structural diagram of a data line in the array substrate shown in fig. 1;
fig. 5 is a schematic top view of an array substrate according to a second embodiment of the present application;
FIG. 6 is a layout diagram of a pixel unit of the array substrate shown in FIG. 5;
FIG. 7 is an enlarged view of a portion of a scan line corresponding to the array substrate shown in FIG. 5;
fig. 8 is a partially enlarged schematic structural diagram of a data line corresponding to the array substrate shown in fig. 5;
fig. 9 is a schematic top view of an array substrate according to a third embodiment of the present application;
FIG. 10 is a layout diagram of a pixel cell of the array substrate shown in FIG. 9;
fig. 11 is a schematic structural view of a scan line corresponding to the array substrate shown in fig. 9;
fig. 12 is a cross-sectional view of a display panel according to a fourth embodiment of the present application;
fig. 13 is a schematic partial structure diagram of a first electronic device according to a fifth embodiment of the present application;
fig. 14 is a schematic partial structure diagram of a second electronic device in a fifth embodiment of the present application;
fig. 15 is a schematic partial structure diagram of a third electronic device in the fifth embodiment of the present application.
The reference numbers illustrate:
100: an array substrate; 10: a substrate; 10 a: a camera hole area; 10 b: a pixel unit; 30: a data line; 31: a first data line; 311: a second straight line segment; 313: a second arc segment; 33: a second data line; 50: scanning a line; 51: a first scanning line; 511: a first straight line segment; 513: a first arc segment; 53: a second scanning line; 300: a display panel; 400: a color film substrate; 500: a liquid crystal layer; 600: an electronic device; 601: a housing.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
Example one
The present application provides an array substrate 100.
Referring to fig. 1 to 4, the array substrate 100 includes a substrate 10, and a plurality of scan lines 50 and a plurality of data lines 30 arranged in parallel on the substrate 10, wherein each scan line 50 is vertically staggered with each data line 30, and the substrate 10 is provided with a camera hole area 10 a;
at least two of the data lines 30 are partially disposed around the camera hole area 10a, at least two of the scan lines 50 are partially disposed around the camera hole area 10a, a scan line 50 partially surrounding the camera hole area 10a is set as a first scan line 51, a scan line 50 not surrounding the camera hole area 10a is set as a second scan line 53, a data line 30 surrounding the camera hole area 10a is set as a first data line 31, and a scan line 50 not surrounding the camera hole area 10a is set as a second data line 33;
in a direction from the edge of the camera hole area 10a to the center thereof, the width of the first data line 31 and/or the first scan line 51 surrounding the camera hole area 10a increases.
It can be understood that the array substrate 100 is a multi-layer structure, and each layer of structure is formed by laminating coating, exposing, developing and etching processes. Specifically, the array substrate 100 includes a substrate 10, the substrate 10 provides a basic carrier, and the substrate 10 is transparent, and the material of the substrate may be a transparent glass plate or a quartz plate, which is not limited herein, and does not affect the penetration of the backlight source. Since the substrate 10 is not conductive, a medium for displaying, such as liquid crystal, needs to be driven by electrons for movement and arrangement, the array substrate 100 further includes conductive Data lines 30 (DL), scan lines 50 (SL), thin film transistors (TFT switches), Pixel Electrodes (PE), and the like. Looking down the array substrate 100, the data lines 30 and the scan lines 50 are arranged in a crossed manner to divide the array substrate 100 into a plurality of pixel regions, each of the regions is provided with a corresponding pixel electrode and a corresponding TFT, the data lines 30 and the scan lines 50 are opaque, so that the portions of the data lines and the scan lines form non-display regions of the pixel regions, the TFTs are also arranged in the non-display regions, and the pixel electrodes form display regions of the pixel regions.
It is understood that a camera hole area 10a is further provided on the substrate 10 for corresponding to a camera, so that the camera can perform a camera shooting or photographing function. Here, in order to avoid the imaging aperture area 10a, the scan line 50 and the data line 30, which are arranged in a straight line, are partially curved so as to fit the edge of the imaging aperture area 10 a. Here, the scan line 50 partially surrounding the camera hole area 10a is set as a first scan line 51, the data line 30 partially surrounding the camera hole area 10a is set as a first data line 31, the scan line 50 normally arranged is set as a second scan line 53, and the data line 30 normally arranged is set as a second data line 33. Meanwhile, each of the first scanning lines 51 is set to include two first straight line segments 511 and a first arc segment 513, two ends of the first arc segment 513 are respectively connected to the two first straight line segments 511, the first arc segment 513 is arranged around the camera hole area 10a, each of the first data lines 31 includes two second straight line segments 311 and a second arc segment 313, two ends of the second arc segment 313 are respectively connected to the two second straight line segments 311, and the second arc segment 313 is arranged around the camera hole area 10 a.
It can be known that the length of the first scan line 51 is greater than that of the second scan line 53, and the length of the first straight line segment 511 is shorter as the length of the first arc line segment 513 closer to the camera hole area 10a is longer; the length of the first data line 31 is greater than that of the second data line 33, and the length of the second arc line segment 313 closer to the camera hole area 10a is longer, the straight line of the second straight line segment 311 is shorter, and the pixel unit 10b of the array substrate 100 is formed by interleaving at least two of the second data line 33, the second scan line 53, the first straight line segment 511 and the second straight line segment 311, so that the pixel unit 10b formed in the camera hole area 10a is smaller than the pixel unit 10b in the non-camera hole area along the extending direction of the first scan line 51, and therefore, in order to compensate for the capacitance and resistance load, the widths of the first arc line segment 513 and the second arc line segment 313 are increased, thereby reducing the load difference of different areas. Here, the width of each first arc segment 513 and/or each second arc segment 313 may increase uniformly in the extending direction thereof, or may increase in a partial section, which is not limited herein. The camera hole region 10a is generally a circular hole, a drop, or a bang type, and may be a square or polygon in other embodiments, which are not limited herein.
In the technical solution of the present application, the array substrate 100 includes a substrate 10, and a data line 30 and a scan line 50 which are disposed on the substrate 10, wherein an image pick-up aperture region 10a is further disposed on the substrate 10, the data line 30 and the scan line 50 are sequentially arranged and staggered, when the image pick-up aperture region 10a is passed through, a partial section of the first data line 31 surrounds the image pick-up aperture region 10a, a section where pixels are normally formed is reduced, the second data line 33 is not affected by the image pick-up aperture region 10a and has a normal length, a partial section of the first scan line 51 surrounds the image pick-up aperture region 10a, the section where pixels are normally formed is reduced, the length of the second scan line 53 is normal, the longer the surrounding lengths of the first scan line 51 and the first data line 31 which are closer to the image pick-up aperture region 10a are, the smaller the number of pixel units 10b which are correspondingly formed is, the corresponding resistance load is increased and the capacitance load is reduced, in this way, in the direction from the edge to the center of the camera hole area 10a, the width of the portion of the first data line 31 and/or the first scan line 51 surrounding the camera hole area 10a increases gradually, that is, the resistive load of the first data line 31 and/or the first scan line 51 is reduced, and the capacitive load of the first data line 31 and/or the first scan line 51 is increased, so as to compensate the lost pixel load, effectively reduce the load difference of different areas of the array substrate 100, and improve the display quality.
In the manufacturing process, a metal layer is first deposited on the substrate 10, and the metal layer is patterned through a mask to form the data line 30 on the substrate 10, so that the thin film transistor can be provided with a voltage for turning on and off, and a gate electrode is formed simultaneously with the data line 30. Here, the patterning process by the photo mask is to deposit a photoresist on the metal layer, to expose and develop the photoresist after masking by the photo mask, and to etch the photoresist. The material of the metal layer is an opaque conductive metal material, such as one or a combination of molybdenum, titanium, chromium, and aluminum, which is not limited herein.
Secondly, forming a gate insulating layer on the gate and data line 30, and sequentially forming an active layer, a source electrode and a drain electrode on the gate insulating layer, the source electrode and the drain electrode contacting both ends of the active layer and being arranged at an interval, thereby completing the processing of the thin film transistor; furthermore, a passivation layer is deposited on the source electrode, the drain electrode and the grid electrode insulating layer, the passivation layer is patterned through a photomask process, a through hole penetrating through the passivation layer is formed, and part of the drain electrode can be exposed through the through hole; finally, a transparent conductive layer is formed on the passivation layer, and the transparent conductive layer is patterned through a photomask process to form a pixel electrode with a specific shape, and the pixel electrode is electrically contacted with the drain electrode through the via hole, so that a voltage for liquid crystal movement is provided for the display area corresponding to the display area of the pixel unit 10b, and the manufacturing of the array substrate 100 is completed.
Referring to fig. 1 to 4, in a first embodiment of the present application, when the shape of the camera hole area 10a is a circle;
in the direction from the second scanning line 53 to the center of the camera hole area 10a, the number of pixel units 10b formed by two adjacent data lines 30 and scanning lines 50 is decreased by a first tolerance d 1;
in addition, in the direction from the second data line 33 to the center of the imaging aperture area 10a, the number of pixel units 10b formed by two adjacent scan lines 50 and data lines 30 decreases by a second tolerance, such as d 2.
Here, the extending direction of the scan line 50 is set to be the horizontal direction, and the extending direction of the second data line 33 is set to be the vertical direction, in this embodiment, when the shape of the imaging aperture region 10a is a circle, since the circle is a centrosymmetric and axisymmetric figure, the first arc line segment 513 of the first scan line 51 is also axisymmetrically disposed with the diameter in the horizontal direction of the imaging aperture region 10a as an axis, the second arc line segment 313 of the first data line 31 is axisymmetrically disposed with the diameter in the vertical direction of the imaging aperture region 10a as an axis, and the first straight line segment 511 and the second straight line segment 311 are also axisymmetrically disposed with the diameter of the imaging aperture region 10a as an axis.
Therefore, in the direction from the second scan line 53 to the center of the imaging aperture area 10a, the tolerance such as the number of pixel cells 10b composed of at least two of the first straight line segment 511, the second straight line segment 311, the second scan line 53, and the second data line 33 decreases, and the first tolerance is d1, for example, the number of pixel cells 10b normally formed on a second scan line 53 is N1, the number of pixel cells 10b formed on the first scan line 51 immediately adjacent to the second scan line 53 is N1-d1, and the number of pixel cells 10b formed on the first scan line 51 is N1-2d1, N1-3d1 … …, and the number of pixel cells 10b formed on a line where the first scan line 51 located on the diameter of the imaging aperture area 10a is located is the smallest in the direction toward the center of the imaging aperture area 10 a. Similarly, in the direction from the second data line 33 to the center of the camera hole area 10a, the number of the pixel units 10b formed by two adjacent scan lines 50 and data lines 30 decreases by a tolerance such as a second tolerance d2, for example, the second data line 33 forms N2 pixel units 10b, and the number of the pixel units 10b formed by the first data line 31 is N2-d2, N2-2d2, N2-3d2 … …, which facilitates the processing of the data lines 30 and scan lines 50, so that the pixel distribution at the edge of the camera hole area 10a is uniform, and the display effect is not affected.
Here, the values of N1 and N2 may be the same, for example, the pixel cell 10b is formed to be square; of course, the two may be different, for example, the formed pixel cell 10b is rectangular, and similarly, the first tolerance d1 and the second tolerance d2 may be the same or different, and may be set according to actual situations.
Referring to fig. 3, in an embodiment of the present application, in a direction from an edge of the camera hole area 10a to a center thereof, a width of a portion of the first scan line 51 surrounding the camera hole area 10a is increased by a third tolerance, which is tolerance d3, wherein d3 is equal to d 1.
In order to make the loads of the respective regions substantially the same, in the present embodiment, in the direction from the edge of the imaging aperture region 10a to the center thereof, the width of the first arc line segment 513 of the first scan line 51 is set as D1, which is increased by an equal tolerance with a third tolerance D3, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width of the first arc line segment 513 of the first scan line 51 is increased by an equal tolerance first, and then decreased by an equal tolerance. Here, by setting d3 to be the same as d1, the load value of the missing pixel can be compensated for, and the difference in the capacitive-resistive load between the non-imaging aperture region and the imaging aperture region 10a can be minimized to make the display screen uniform at each position. Of course, in other embodiments, d3 and d1 may be different, or within a fluctuation range of d 1.
Here, the width of the first arc segment 513 may be uniformly set, or may be increased in a certain segment.
Referring to fig. 4, in an embodiment of the present disclosure, in a direction from an edge of the camera hole region 10a to a center thereof, a width of the first data line 31 increases by a fourth tolerance, which is d4, wherein d4 is equal to d 2.
Similarly, in the present embodiment, the width of the second arc segment 313 of the first data line 31 is set to be D2 in the horizontal direction and in the direction from the edge of the imaging aperture region 10a to the center thereof, and the width is increased by a tolerance such as the fourth tolerance D4. That is, in the horizontal direction, in the direction from one end to the other end of the scan line 50, the width of the second arc segment 313 of the first data line 31 is increased with equal tolerance, and then decreased with equal tolerance. Here, by setting d4 to be the same as d2, the load value of the missing pixel can be compensated for, and the difference in the capacitive-resistive load between the non-imaging aperture region and the imaging aperture region 10a can be minimized to make the display screen uniform at each position. Of course, in other embodiments, d4 and d2 may be different, or within a fluctuation range of d 2.
Here, the width of the second arc segment 313 is uniformly set in the extending direction thereof, which improves the convenience of processing. Of course, in other embodiments, the partial section may be widened such that the width is not uniform in the extending direction thereof.
Example two
Referring to fig. 5 and fig. 6, when the shape of the camera hole area 10a is a water drop shape;
in the extending direction of the data line 30 from one end far away from the camera hole area 10a to the camera hole area 10a, the number of the pixel units 10b formed by two adjacent first scan lines 51 and data lines 30 is decreased progressively by a first unequal difference sequence;
in addition, in the direction from the second scan line 53 to the center of the imaging aperture region 10a, the number of pixel units 10b formed by two adjacent first data lines 31 and scan lines 50 decreases in a second unequal difference sequence.
In this embodiment, the imaging hole area 10a is a water drop type, where the water drop type is an inverted shape of a water drop falling normally, that is, in the vertical direction, the upper side of the imaging hole area 10a is large in size, and the lower side thereof is small in size. Therefore, the scanning lines 50 and the data lines 30 around the imaging aperture region 10a are not disposed in axial symmetry nor in central symmetry in the vertical direction. In the horizontal direction, the scan lines 50 and the data lines 30 on the periphery of the imaging aperture area 10a may be arranged axially symmetrically with respect to the center line of the imaging aperture area 10 a. When the data line 30 extends from one end far away from the camera hole area 10a to the camera hole area 10a, the number of the pixel units 10b formed on the periphery of the camera hole area 10a of the substrate 10 is decreased by a first unequal difference array, for example, the number of the pixel units 10b on each horizontal line formed normally is N3, the number of the pixel units 10b formed on the horizontal line of the first scanning line 51 adjacent to the second scanning line 53 is N3-a1, and the number of the pixel units 10b formed when extending to the direction of the camera hole area 10a is N3-b1 and N3-c1 … … in sequence.
At this time, in the direction from the second scan line 53 to the center of the imaging hole area 10a, the number of the pixel cells 10b formed by the two adjacent first data lines 31 and the scan line 50 is decreased by a second unequal difference array, for example, the number of the pixel cells 10b on each vertical line formed normally is N4, the number of the pixel cells 10b formed on the horizontal line of the first scan line 51 adjacent to the second scan line 53 is N4-a2, and when extending in the direction of the imaging hole area 10a, the number of the pixel cells 10b formed is N4-b2 and N4-c2 … … in sequence. That is, in the horizontal direction, the number of the pixel units 10b formed by the first data line 31 decreases with unequal differences, and then increases with unequal differences, and the first data line 31 is arranged in an axisymmetric manner with the central axis of the camera hole region 10a, so that the array substrate 100 is more convenient to process, and the processing efficiency is improved.
Referring to fig. 7, in an embodiment of the present application, in a direction from the second data line 33 to the camera hole area 10a, a width of a portion of the first scan line 51 surrounding the camera hole area 10a is increased by a first unequal difference sequence.
In this embodiment, in order to make the loads of the respective regions substantially the same, the width of the first arc segment 513 of the first scan line 51 increases in a first unequal series in the direction from the second data line 33 to the imaging aperture region 10a, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width D3 of the first arc segment 513 of the first scan line 51 increases in a first unequal series, that is, D3-a1, D3-b1, and D3-c1 … …. Here, setting the width of the first arc segment 513 to be consistent with the reduced number of pixel units 10b enables compensation of the load value by the missing pixels, thereby minimizing the difference in the capacitive-resistive load of the non-imaging aperture area and the imaging aperture area 10a to make the display screen uniform at each position. Of course, in other embodiments, the width of the first arc line segment 513 may be different from the reduced number of the pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of the pixel units 10b at the corresponding position.
Here, the width of the first arc line 513 may be uniformly set, or the width intervals of the plurality of segments may be increased.
Referring to fig. 8, in an embodiment of the present application, in a direction from an edge of the camera hole area 10a in the horizontal direction to a center thereof, widths of portions of the first data lines 31 surrounding the camera hole area 10a are increased in a second unequal series.
In the present embodiment, the width of the second arc segment 313 of the first data line 31 increases in a second unequal-difference sequence in the horizontal direction and in the direction from the edge of the imaging aperture region 10a to the center thereof. That is, in the horizontal direction, from one end of the scan line 50 to the other end, the width D4 of the second arc segment 313 of the first data line 31 increases in the second unequal difference series and then decreases in the opposite second unequal difference series, i.e., D4-a2, D4-b2, and D4-c2 … …. Here, by setting the width of the second arc segment 313 to be the same as the number of the pixel cells 10b to be decreased at the corresponding position, it is possible to compensate for the load value of the missing pixel cell 10b, thereby minimizing the difference in the capacitive resistance load between the non-imaging aperture area and the imaging aperture area 10a to make the display screen uniform at each position. Of course, in other embodiments, the width of the second arc segment 313 may be different from the reduced number of the pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of the pixel units 10b at the corresponding position.
Here, the width of the second arc segment 313 is uniformly set in the extending direction thereof, which improves the convenience of processing. Of course, in other embodiments, the partial section may be widened such that the width is not uniform in the extending direction thereof.
EXAMPLE III
Referring to fig. 9 and fig. 10 in combination, when the camera hole area 10a is of the bang-bang type, in an extending direction of the data line 30 from one end far away from the camera hole area 10a to the camera hole area 10a, the number of pixel units 10b formed by two adjacent first scan lines 51 and the data line 30 is decreased by a first unequal-difference sequence;
in addition, in the direction from the second scan line 53 to the center of the imaging aperture region 10a, the number of pixel units 10b formed by two adjacent first data lines 31 and scan lines 50 decreases in a second unequal difference sequence.
In this embodiment, when the image capturing hole region 10a is of the bang type, the bang type is substantially trapezoidal, and has a slightly wider upper end and a slightly narrower lower end, and therefore, the scanning lines 50 and the data lines 30 on the periphery of the image capturing hole region 10a are not axisymmetrically or centrosymmetrically arranged in the vertical direction. In the horizontal direction, the scan lines 50 and the data lines 30 on the periphery of the imaging aperture area 10a are disposed in axial symmetry with the center line of the imaging aperture area 10a as an axis. When the data line 30 extends from one end far away from the camera hole area 10a to the camera hole area 10a, the number of the pixel units 10b formed on the periphery of the camera hole area 10a of the substrate 10 is decreased by a first unequal difference array, for example, the number of the pixel units 10b on each horizontal line formed normally is N5, the number of the pixel units 10b formed on the horizontal line of the first scanning line 51 adjacent to the second scanning line 53 is N5-a1, and the number of the pixel units 10b formed when extending to the direction of the camera hole area 10a is N5-b1 and N5-c1 … … in sequence. Of course, the number of the liu type pixel cells 10b may alternatively be arranged in a different value from the first unequal-difference sequence, for example, in the second unequal-difference sequence.
Similarly, the number of the pixel units 10b formed by the two adjacent first data lines 31 and the scanning line 50 decreases in a second unequal difference sequence in the direction from the second scanning line 53 to the center of the imaging aperture region 10a, as in the case of the bang-type imaging aperture region, as in the case of the water drop-type imaging aperture region. For example, the number of pixel cells 10b per each vertical line that is normally formed is N6, the number of pixel cells 10b formed on the horizontal line on which the first scan line 51 next to the second scan line 53 is located is N6-a2, and the number of pixel cells 10b formed when extending in the direction of the imaging aperture area 10a is N6-b2, N6-c2 … … in this order.
Referring to fig. 11, in order to make the loads of the respective regions substantially the same, in the direction from the second data line 33 to the camera hole region 10a, the width of the first arc segment 513 of the first scan line 51 increases in a first unequal series, that is, in the vertical direction, in the direction from one end of the data line 30 to the other end, the width D5 of the first arc segment 513 of the first scan line 51 increases in a first unequal series, that is, D5-a1, D5-b1, and D5-c1 … …. Here, setting the width of the first arc segment 513 to be consistent with the reduced number of pixel units 10b enables compensation of the load value by the missing pixels, thereby minimizing the difference in the capacitive-resistive load of the non-imaging aperture area and the imaging aperture area 10a to make the display screen uniform at each position. Of course, in other embodiments, the width of the first arc line segment 513 may be different from the reduced number of the pixel units 10b at the corresponding position, or within a fluctuation range of the reduced number of the pixel units 10b at the corresponding position.
With continued reference to fig. 1, fig. 3 and fig. 4, in an embodiment of the present application, a first arc segment 513 closest to the camera hole area 10a is disposed at an interval from an edge of the camera hole area 10 a;
and/or the second arc segment 313 closest to the camera hole area 10a is arranged at a distance from the edge of the camera hole area 10 a.
In this embodiment, for convenience of processing, the first arc segment 513 closest to the camera shooting hole region 10a and the edge of the camera shooting hole region 10a are arranged at intervals, so that the metal routing can be prevented from being affected when the camera shooting hole region 10a is cut, meanwhile, the stability of the metal routing can be ensured, and the performance stability of the array substrate 100 is improved.
Similarly, on the basis of whether the first arc segment 513 closest to the camera hole area 10a and the edge of the camera hole area 10a are arranged at intervals, the second arc segment 313 closest to the camera hole area 10a and the edge of the camera hole area 10a are arranged at intervals, so that the manufacturing efficiency of the array substrate 100 is further improved, and the structural stability of the array substrate is ensured.
Example four
Referring to fig. 12, the present application further provides a display panel 300, where the display panel 300 includes a color film substrate 400, an array substrate 100 and a liquid crystal layer 500, the color film substrate 400 and the array substrate 100 are arranged in a box-to-box manner, and the array substrate 100 is the array substrate 100 according to any of the above embodiments. Since the array substrate 100 of the display panel 300 includes all the technical solutions of all the embodiments, at least all the advantages brought by the technical solutions of the embodiments are achieved, and no further description is given here.
The color film substrate 400 of the display panel 300 is also provided with a structure avoiding the camera hole region 10a, so that the installation and the function of the camera are not affected.
EXAMPLE five
Referring to fig. 13 to 15, the present application further provides an electronic device 600, where the electronic device 600 includes a housing 601 and a display panel 300 disposed on the housing 601, and the display panel 300 is the display panel 300 as described above. Since the display panel 300 of the electronic device 600 includes all technical solutions of all the embodiments described above, at least all the advantages brought by the technical solutions of the embodiments described above are achieved, and no further description is given here.
The electronic device 600 may be a mobile terminal, such as a mobile phone, a notebook computer, a tablet computer, a wrist-worn device, and the like, and the electronic device 600 may also be a home-use electronic device 600 with a display screen, such as a television, an air conditioner, and the like, or any other electronic device 600 with a camera, which is not limited herein.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the subject matter of the present application, which is conceived to be equivalent to the above description and the accompanying drawings, or to be directly/indirectly applied to other related arts, are intended to be included within the scope of the present application.
Claims (9)
1. The array substrate comprises a substrate, a plurality of scanning lines arranged on the substrate in parallel and a plurality of data lines arranged on the substrate in parallel, wherein each scanning line and each data line are vertically staggered, and the substrate is provided with a camera shooting hole area, and is characterized in that:
at least two parts of the data lines are arranged around the camera hole area, at least two parts of the scanning lines are arranged around the camera hole area, the scanning lines partially surrounding the camera hole area are set as first scanning lines, the scanning lines not surrounding the camera hole area are set as second scanning lines, the data lines surrounding the camera hole area are set as first data lines, and the data lines not surrounding the camera hole area are set as second data lines;
in the direction from the edge of the camera shooting hole area to the center of the camera shooting hole area, the width of the part of the first data line and/or the first scanning line surrounding the camera shooting hole area is increased;
when the shape of the camera shooting hole area is a circle;
in the direction from the second scanning line to the center of the camera shooting hole area, the number of pixel units formed by two adjacent data lines and scanning lines is decreased progressively with a first tolerance and other tolerances;
and in the direction from the second data line to the center of the camera shooting hole area, the number of pixel units formed by two adjacent scanning lines and data lines is decreased progressively by a tolerance such as a second tolerance.
2. The array substrate of claim 1, wherein a width of the portion of the first scan line surrounding the camera aperture region in a direction from an edge of the camera aperture region to a center of the camera aperture region increases by a tolerance equal to a third tolerance, wherein the third tolerance is equal to the first tolerance.
3. The array substrate of claim 1, wherein a width of the first data line increases by a fourth tolerance equal to the second tolerance in a direction from an edge of the camera aperture region to a center thereof.
4. The array substrate is characterized by comprising a substrate, a plurality of scanning lines arranged on the substrate in parallel and a plurality of data lines arranged on the substrate in parallel, wherein each scanning line and each data line are vertically staggered, and the substrate is provided with a camera shooting hole area, and the array substrate is characterized in that:
at least two parts of the data lines are arranged around the camera hole area, at least two parts of the scanning lines are arranged around the camera hole area, the scanning lines partially surrounding the camera hole area are set as first scanning lines, the scanning lines not surrounding the camera hole area are set as second scanning lines, the data lines surrounding the camera hole area are set as first data lines, and the data lines not surrounding the camera hole area are set as second data lines;
in the direction from the edge of the camera shooting hole area to the center of the camera shooting hole area, the width of the part of the first data line and/or the first scanning line surrounding the camera shooting hole area is increased;
when the shape of the camera shooting hole area is a water drop type or a Liuhai type;
in the extending direction of the data line from one end far away from the camera shooting hole area to the camera shooting hole area, the number of pixel units formed by two adjacent first scanning lines and the data line is decreased in a first unequal difference series;
and in the direction from the second scanning line to the center of the camera shooting hole area, the number of pixel units formed by two adjacent first data lines and scanning lines is decreased progressively by a second unequal difference number sequence.
5. The array substrate of claim 4, wherein a width of a portion of the first scan line surrounding the camera aperture region increases in a first unequal series of differences in a direction from the second data line to the camera aperture region.
6. The array substrate of claim 4, wherein the width of the portion of the first data line surrounding the camera aperture region increases in a second unequal series of differences in a direction from a horizontally oriented edge of the camera aperture region to a center thereof.
7. The array substrate according to claim 1 or 4, wherein each of the first scan lines comprises two first straight line segments and a first arc line segment, two ends of the first arc line segment are respectively connected with the two first straight line segments, and the first arc line segment closest to the camera hole area is spaced from the edge of the camera hole area;
and/or each first data line comprises two second straight line segments and a second arc line segment, two ends of each second arc line segment are respectively connected with the two second straight line segments, and the second arc line segment closest to the camera hole area and the edge of the camera hole area are arranged at intervals.
8. A display panel, comprising a color film substrate, an array substrate and a liquid crystal layer, wherein the color film substrate and the array substrate are arranged in a box-to-box manner, and the array substrate is the array substrate according to any one of claims 1 to 7.
9. An electronic device, comprising a housing and a display panel provided in the housing, wherein the display panel is the display panel according to claim 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111096466.2A CN113568231B (en) | 2021-09-18 | 2021-09-18 | Array substrate, display panel and electronic equipment |
| PCT/CN2021/142289 WO2023040117A1 (en) | 2021-09-18 | 2021-12-29 | Array substrate, display panel, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111096466.2A CN113568231B (en) | 2021-09-18 | 2021-09-18 | Array substrate, display panel and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113568231A CN113568231A (en) | 2021-10-29 |
| CN113568231B true CN113568231B (en) | 2022-01-25 |
Family
ID=78173776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111096466.2A Active CN113568231B (en) | 2021-09-18 | 2021-09-18 | Array substrate, display panel and electronic equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113568231B (en) |
| WO (1) | WO2023040117A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113568231B (en) * | 2021-09-18 | 2022-01-25 | 惠科股份有限公司 | Array substrate, display panel and electronic equipment |
| KR20240094342A (en) * | 2022-12-16 | 2024-06-25 | 엘지디스플레이 주식회사 | Display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003167271A (en) * | 2001-11-30 | 2003-06-13 | Optrex Corp | Liquid crystal display element |
| CN108957890A (en) * | 2018-07-27 | 2018-12-07 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108957888A (en) * | 2018-07-27 | 2018-12-07 | 厦门天马微电子有限公司 | Display panel and display device |
| CN109283726A (en) * | 2018-11-06 | 2019-01-29 | 厦门天马微电子有限公司 | A kind of array substrate and display panel |
| CN109585519A (en) * | 2018-12-19 | 2019-04-05 | 上海天马微电子有限公司 | Display panel and display device |
| CN110780501A (en) * | 2019-11-29 | 2020-02-11 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111816071A (en) * | 2020-07-03 | 2020-10-23 | 武汉华星光电半导体显示技术有限公司 | Display panel |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010032760A (en) * | 2008-07-29 | 2010-02-12 | Hitachi Displays Ltd | Display device |
| KR102490891B1 (en) * | 2015-12-04 | 2023-01-25 | 삼성디스플레이 주식회사 | Display device |
| CN108919581B (en) * | 2018-06-29 | 2021-06-08 | 厦门天马微电子有限公司 | Display panel, preparation method thereof and electronic equipment |
| CN109119447B (en) * | 2018-08-29 | 2020-11-13 | 武汉天马微电子有限公司 | Display panel and display device |
| CN110896089A (en) * | 2018-09-12 | 2020-03-20 | 三星显示有限公司 | Display device |
| US20200301220A1 (en) * | 2019-03-20 | 2020-09-24 | Sharp Kabushiki Kaisha | Display device |
| KR102637057B1 (en) * | 2019-09-24 | 2024-02-14 | 엘지디스플레이 주식회사 | Display device |
| CN112599580B (en) * | 2020-12-14 | 2023-11-24 | 合肥维信诺科技有限公司 | Display panel and display device |
| CN113568231B (en) * | 2021-09-18 | 2022-01-25 | 惠科股份有限公司 | Array substrate, display panel and electronic equipment |
-
2021
- 2021-09-18 CN CN202111096466.2A patent/CN113568231B/en active Active
- 2021-12-29 WO PCT/CN2021/142289 patent/WO2023040117A1/en unknown
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003167271A (en) * | 2001-11-30 | 2003-06-13 | Optrex Corp | Liquid crystal display element |
| CN108957890A (en) * | 2018-07-27 | 2018-12-07 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108957888A (en) * | 2018-07-27 | 2018-12-07 | 厦门天马微电子有限公司 | Display panel and display device |
| CN109283726A (en) * | 2018-11-06 | 2019-01-29 | 厦门天马微电子有限公司 | A kind of array substrate and display panel |
| CN109585519A (en) * | 2018-12-19 | 2019-04-05 | 上海天马微电子有限公司 | Display panel and display device |
| CN110780501A (en) * | 2019-11-29 | 2020-02-11 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111816071A (en) * | 2020-07-03 | 2020-10-23 | 武汉华星光电半导体显示技术有限公司 | Display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023040117A1 (en) | 2023-03-23 |
| CN113568231A (en) | 2021-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10254876B2 (en) | Array substrate, fabricating method thereof and display device | |
| US7221425B2 (en) | Substrate for a display device, liquid crystal display device comprising overlapping connecting lines of the scan lines and method of manufacturing the same | |
| US11934060B2 (en) | Array substrate and display device | |
| CN113568231B (en) | Array substrate, display panel and electronic equipment | |
| US10163938B2 (en) | Array substrate and manufacturing method thereof, and display device | |
| CN106019751B (en) | Array substrate, manufacturing method thereof and display device | |
| US20200350388A1 (en) | Display panel, display screen, and display terminal | |
| CN111338142B (en) | Array substrate, manufacturing method thereof and display device | |
| US20210157207A1 (en) | Array substrate, display panel and display apparatus | |
| US12100703B2 (en) | Electrostatic protection circuit and manufacturing method thereof, array substrate and display device | |
| US20210373704A1 (en) | Touch control substrate and method for manufacturing the same and display device | |
| CN113345929A (en) | Display substrate, preparation method thereof and display device | |
| CN113629115B (en) | Display panel, display device and manufacturing method of display panel | |
| US11177295B2 (en) | Array substrate, manufacturing method thereof and display device | |
| KR20040040682A (en) | array circuit board of LCD and fabrication method of thereof | |
| JP2004085720A (en) | Active matrix substrate, reflection/transmission type liquid crystal display panel, and reflection/transmission type liquid crystal display device | |
| US10175546B2 (en) | Array substrate and manufacturing method thereof, and display device | |
| US20240120348A1 (en) | Display panel and display device | |
| WO2021092752A1 (en) | Display substrate and manufacturing method thereof, and display device | |
| US20220283673A1 (en) | Array Substrate and Preparation Method thereof, and Touch Display Apparatus | |
| JP2021504952A (en) | Manufacturing method of TFT substrate, ESD protection circuit and TFT substrate | |
| CN112670302A (en) | Array substrate, manufacturing method thereof, display panel and display device | |
| CN113064306B (en) | Manufacturing method of substrate structure, substrate structure and display panel | |
| US20240379655A1 (en) | Electrostatic protection circuit and manufacturing method thereof, array substrate and display device | |
| US10747048B2 (en) | Color filter substrate and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |