CN113283212A - Method and device for analyzing winding quality of integrated circuit, electronic equipment and storage medium - Google Patents
Method and device for analyzing winding quality of integrated circuit, electronic equipment and storage medium Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
A winding quality analysis method and apparatus for an integrated circuit, an electronic device, and a computer-readable storage medium. The winding quality analysis method comprises the following steps: acquiring at least one target wiring area from a layout of an integrated circuit; determining a winding group passing through each target wiring area in at least one target wiring area, wherein the winding group comprises at least one winding; and calculating the circuitous degree characterization parameters of the winding groups aiming at each target wiring area so as to determine the winding quality of the integrated circuit according to the circuitous degree characterization parameters. The method can reduce the time cost and the labor cost consumed by analyzing the winding quality of the integrated circuit, improve the quantization degree of the winding quality analysis, and improve the accuracy of the winding quality analysis.
Description
Technical Field
The embodiment of the disclosure relates to a winding quality analysis method and device for an integrated circuit, an electronic device and a storage medium.
Background
In the field of integrated circuit design, back-end design covers all circuit generation steps after logic design and before integrated circuit processing, including module partitioning, placement, routing, etc. The layout quality of the back-end design is critical to circuit performance, area, yield (yield), and reliability.
When the layout design of the integrated circuit is carried out, the winding wires for connecting different devices need to be reasonably designed and arranged, and the requirement on the design of the winding wires is higher and higher due to the power consumption requirement and the like.
Disclosure of Invention
At least one embodiment of the present disclosure provides a winding quality analysis method of an integrated circuit, including: acquiring at least one target wiring area from a layout of an integrated circuit; determining a winding group passing through each target wiring area in at least one target wiring area, wherein the winding group comprises at least one winding; and calculating the circuitous degree characterization parameters of the winding groups aiming at each target wiring area so as to determine the winding quality of the integrated circuit according to the circuitous degree characterization parameters.
For example, in a winding quality analysis method provided in an embodiment of the present disclosure, for each target routing area, a detour degree characterizing parameter of a winding group is calculated, so as to determine a winding quality of an integrated circuit according to the detour degree characterizing parameter, including: calculating a circuitous characteristic value of each winding in the winding group aiming at each target wiring area; calculating the circuitous characteristic value of each winding in the winding group to obtain a characteristic value calculation result of the winding group; and determining a detour degree characterization parameter of the winding group based on the feature value calculation result so as to determine the winding quality of the integrated circuit according to the detour degree characterization parameter.
For example, in the winding quality analysis method provided in an embodiment of the present disclosure, calculating the detour characteristic value of each winding in the winding group to obtain the characteristic value calculation result of the winding group includes: and arithmetically adding the circuitous characteristic values of each winding in the winding group to obtain a characteristic value sum, and taking the characteristic value sum as a characteristic value calculation result.
For example, in a winding quality analysis method provided in an embodiment of the present disclosure, determining a detour degree characterizing parameter of a winding group based on a feature value calculation result, so as to determine a winding quality of an integrated circuit according to the detour degree characterizing parameter, the method includes: taking the feature value calculation result as a roundabout degree characterization parameter; or calculating the ratio of the calculation result of the characteristic value to the number of the winding in the winding group, and taking the ratio as a detour degree characterization parameter so as to determine the winding quality of the integrated circuit according to the detour degree characterization parameter.
For example, in the winding quality analysis method provided in an embodiment of the present disclosure, for each target routing area, calculating a detour characteristic value of each winding in a winding group includes: calculating the length of the winding and the distance between the starting point and the end point of the winding; calculating the ratio of the length to the distance; and calculating a difference between the ratio and 1, and taking the difference as a detour characteristic value.
For example, in the winding quality analysis method provided in an embodiment of the present disclosure, the distance includes a euclidean distance or a manhattan distance.
For example, in a winding quality analysis method provided in an embodiment of the present disclosure, the method further includes: determining display image elements corresponding to a target wiring area through which the winding group passes according to the roundabout degree characterization parameter of the winding group; and displaying the display image elements in the target wiring area.
For example, in the winding quality analysis method provided in an embodiment of the present disclosure, determining the display image element corresponding to the target routing area through which the winding group passes according to the detour degree characterization parameter of the winding group includes: determining a parameter interval to which the roundabout degree characterization parameter of the winding group belongs according to the roundabout degree characterization parameter of the winding group; and taking the display image elements corresponding to the parameter intervals as display image elements corresponding to the target wiring area through which the winding group passes.
For example, in the winding quality analysis method provided by an embodiment of the present disclosure, the display image element is a single color or pattern.
For example, in the winding quality analysis method provided by an embodiment of the present disclosure, the display image elements corresponding to different parameter intervals are different.
For example, in a winding quality analysis method provided in an embodiment of the present disclosure, acquiring at least one target routing area from a layout of an integrated circuit includes: determining a standard window; and dividing an initial wiring area in the layout of the integrated circuit according to the standard window to determine at least one target wiring area, wherein the shape and the size of the target wiring area are the same as those of the standard window.
For example, in the winding quality analysis method provided in an embodiment of the present disclosure, the standard window has a rectangular shape.
For example, in a winding quality analysis method provided in an embodiment of the present disclosure, determining a standard window includes: acquiring the line width of a winding; and determining the size of the standard window according to the line width of the winding.
For example, in a winding quality analysis method provided in an embodiment of the present disclosure, determining a size of the standard window according to a line width of the winding includes: determining the preset number of the windings contained in the standard window; and determining the size of the standard window according to the line width and the preset number of the winding.
For example, in the winding quality analysis method provided by an embodiment of the present disclosure, the predetermined number is N, where N is greater than or equal to 10 and less than or equal to 30, and N is an integer.
For example, in the routing quality analysis method provided in an embodiment of the present disclosure, dividing an initial routing area in a layout of an integrated circuit according to a standard window to determine at least one target routing area includes: according to the shape and size of the standard window, an initial wiring area in a layout of the integrated circuit is divided into a plurality of target windows, an area in the integrated circuit corresponding to each target window is used as a target wiring area, and the target windows are adjacent to each other.
For example, in a winding quality analysis method provided in an embodiment of the present disclosure, the method further includes: and adjusting the layout of the integrated circuit based on the roundabout degree characterization parameters.
At least one embodiment of the present disclosure provides a winding quality analyzing apparatus of an integrated circuit, including: the acquisition unit is configured to acquire at least one target wiring area from a layout of the integrated circuit; the determining unit is configured to determine a winding group passing through each target wiring area in at least one target wiring area, and the winding group comprises at least one winding; and the calculating unit is configured to calculate a detour degree representation parameter of the winding group aiming at each target wiring area so as to determine the winding quality of the integrated circuit according to the detour degree representation parameter.
At least one embodiment of the present disclosure provides an electronic device comprising a processor; a memory including one or more computer program modules; one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for implementing a winding quality analysis method for an integrated circuit provided by any of the embodiments of the present disclosure.
At least one embodiment of the present disclosure provides a computer-readable storage medium for storing non-transitory computer-readable instructions, which when executed by a computer, can implement a winding quality analysis method for an integrated circuit provided in any one of the embodiments of the present disclosure.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
FIGS. 1A and 1B schematically illustrate an application scenario of a winding quality analysis method for an integrated circuit;
fig. 2A is a flow chart illustrating a method for analyzing winding quality of an integrated circuit according to at least one embodiment of the present disclosure;
fig. 2B is a schematic diagram illustrating a target routing area in an integrated circuit layout according to at least one embodiment of the present disclosure;
fig. 2C illustrates a flowchart of a method of step S10 in fig. 2A according to at least one embodiment of the present disclosure;
fig. 3A illustrates a flowchart of a method of step S30 in fig. 2A according to at least one embodiment of the present disclosure;
fig. 3B illustrates a flowchart of a method of step S31 in fig. 3A according to at least one embodiment of the present disclosure;
FIG. 4 is a flow chart illustrating another method for analyzing routing quality of an integrated circuit according to at least one embodiment of the present disclosure;
fig. 5A illustrates a flowchart of a method of step S40 in fig. 4 according to at least one embodiment of the present disclosure;
fig. 5B is a schematic diagram illustrating a display image element displayed in a target routing area according to at least one embodiment of the disclosure;
FIG. 6A is a flow chart illustrating another method for analyzing routing quality of an integrated circuit according to at least one embodiment of the present disclosure;
fig. 6B is a schematic diagram illustrating a layout for adjusting a layout of an integrated circuit according to at least one embodiment of the present disclosure;
FIG. 7 is a flow chart illustrating another method for analyzing routing quality of an integrated circuit according to at least one embodiment of the present disclosure;
fig. 8 is a schematic block diagram of a winding quality analysis apparatus for an integrated circuit according to at least one embodiment of the present disclosure;
fig. 9 illustrates a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;
fig. 10 illustrates a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and
fig. 11 illustrates a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
When the layout design of the integrated circuit is performed, due to the fact that the layout mode of the device is diversified, the algorithm of the integrated circuit design tool on the signal path is limited, and the like, the winding between the devices may generate a roundabout phenomenon in distance, so that the length of the winding is long, and the power consumption is large or the timing requirement cannot be met. Here, "routing" refers to connecting traces of different devices to achieve electrical connection between the devices.
Fig. 1A and 1B schematically show an application scenario of a winding quality analysis method of an integrated circuit. It should be noted that fig. 1A and 1B are only examples of application scenarios to which the embodiments of the present disclosure may be applied to help those skilled in the art understand the technical content of the present disclosure, but do not mean that the embodiments of the present disclosure may not be applied to other scenarios.
As shown in fig. 1A and 1B, the application scenario includes an integrated circuit layout 100 of an integrated circuit. As can be seen from the layout of the integrated circuit in the design, the integrated circuit at least comprises a device A to a device D, and the device A and the device D are connected through a winding so that signals are transmitted from the device A to the device D through the winding. The signal may be, for example, a clock signal or may be a data signal, but may also be any other type of electrical signal.
It should be noted that the integrated circuit layout 100 shown in fig. 1A and 1B is only a schematic representation, and in practice, the integrated circuit layout is far more complex than the integrated circuit layout 100 shown in fig. 1A and 1B.
In a preferred embodiment, the wire connecting device a and device D may be a straight line. As shown in fig. 1A, for example, in a more desirable case, in the integrated circuit, the wiring connecting the device a and the device D may be a wiring 110 (a wiring shown by a dotted line in fig. 1A). However, the wiring connecting the device a and the device D is not a straight line due to the influence of other devices in the integrated circuit and the like. For example, as shown in fig. 1B, the routing connecting device a and device D needs to bypass device B and device C due to the obstruction of device B and device C, and thus, in the integrated circuit layout 100, the routing connecting device a and device D is the routing 120 (the routing shown as a solid line in fig. 1B).
As can be seen from fig. 1A and 1B, the winding 120 is longer than the winding 110, that is, the winding 120 has a greater degree of detour with respect to the winding 110. A large degree of detour easily leads to large power consumption and large signal delay, resulting in timing requirements not being met (for example, requirements of clock setup time, clock hold time, etc. cannot be met), and therefore it is necessary to reduce the degree of detour of the winding as much as possible.
In the related art, whether the detour degree of the routing in the layout of the integrated circuit is too large can be judged by observation. However, the determination of the detour degree of the routing in the layout of the integrated circuit through observation is not only time-consuming and labor-consuming, but also has low accuracy.
Therefore, at least one embodiment of the present disclosure provides a winding quality analysis method and apparatus for an integrated circuit, an electronic device, and a computer-readable storage medium, which can reduce time cost and labor cost consumed for analyzing a layout of the integrated circuit, improve a quantization degree of winding quality analysis of the integrated circuit, and improve accuracy of determining a detour degree of a winding.
The method for analyzing the winding quality of the integrated circuit comprises the following steps: acquiring at least one target wiring area from a layout of an integrated circuit; determining a winding group passing through each target wiring area in at least one target wiring area, wherein the winding group comprises at least one winding; and calculating the circuitous degree characterization parameters of the winding groups aiming at each target wiring area so as to determine the winding quality of the integrated circuit according to the circuitous degree characterization parameters. The method can intuitively embody the circuitous degree of the winding in the integrated circuit, thereby reducing the time cost and the labor cost consumed by analyzing the winding quality of the integrated circuit, improving the quantization degree of the winding quality analysis of the integrated circuit and improving the accuracy of analyzing the winding quality of the integrated circuit.
It should be noted that the devices described in this disclosure may be any devices used in integrated circuits, such as standard cells, functional blocks, macro blocks, and the like.
Fig. 2A is a flowchart illustrating a winding quality analysis method of an integrated circuit according to at least one embodiment of the disclosure.
As shown in FIG. 2A, the method may be used for designing an integrated circuit and may include steps S10-S30.
In step S10, at least one target routing region is obtained from the layout of the integrated circuit.
In step S20, a winding group passing through each of the at least one target routing area is determined, the winding group including at least one winding.
In step S30, for each target routing area, a detour degree characterizing parameter of the routing group is calculated, so as to determine the routing quality of the integrated circuit according to the detour degree characterizing parameter.
By the method, the detour degree characterization parameter of the winding group in the target wiring area can be calculated, so that the winding quality of the integrated circuit is evaluated through the detour degree characterization parameter, the detour degree of the winding in the target wiring area in the integrated circuit can be visually embodied through the detour degree characterization parameter, the winding quality is not required to be estimated only by observation, the time cost and the labor cost consumed by analyzing the winding quality of the integrated circuit are reduced, the quantification degree of the winding quality analysis of the integrated circuit is improved, and the accuracy of analyzing the winding quality of the integrated circuit is improved.
For step S10, the other regions in the integrated circuit layout except the placement region of the device may be used as the initial routing region. That is, the initial routing area is an area in the integrated circuit layout where routing can be arranged. The wire is a connection line for connecting two devices. And the target routing area may be a selected one of the sub-areas from the initial routing area of the integrated circuit. For example, in the integrated circuit layout 100 shown in fig. 1A and 1B, the other areas are the initial routing areas except the areas occupied by the devices a to D, and the target routing area may be a partial area in the initial routing area.
Fig. 2B is a schematic diagram illustrating a target routing area in an integrated circuit layout according to at least one embodiment of the disclosure.
As shown in fig. 2B, for example, the initial trace area of the integrated circuit layout 100 may be divided into a plurality of target windows. As shown in fig. 2B, these target windows may include at least a target window 210 and a target window 220. The area in the integrated circuit layout 100 corresponding to each target window is a target routing area.
In some embodiments of the present disclosure, the shape and size of each target window is the same. For example, the target window 210 and the target window 220 are the same shape and size.
It should be understood that the target window shown in fig. 2B is only a part of the target window obtained by dividing the initial trace area. The plurality of target windows obtained by dividing the initial routing area may further include other target windows, which are not shown in fig. 2B. For example, the left side of device B may also be scribed into multiple target windows.
Fig. 2C illustrates a flowchart of a method of step S10 in fig. 2A according to at least one embodiment of the present disclosure.
As shown in fig. 2C, step S10 may include step S11 and step S12.
In step S11, a criterion window is determined.
In some embodiments of the present disclosure, determining the standard window may include determining a shape and a size of the standard window.
In some embodiments of the present disclosure, the shape of the standard window may be a shape that can be generated by an integrated circuit design tool. For example, an integrated circuit design tool (EDA) can generate a rectangle, and thus, the standard window may be rectangular in shape. For example, in some examples, the standard window may be square in shape.
In some embodiments of the present disclosure, in step S11, determining the criterion window may include: and acquiring the line width of the winding, and determining the size of the standard window according to the line width of the winding.
For example, a mapping table between the line width and the size of the standard window may be queried to determine the size of the standard window.
In some embodiments of the present disclosure, determining the size of the standard window according to the line width of the routing may include: the method includes the steps of determining a preset number of windings accommodated by a standard window, and determining the size of the standard window according to the line width and the preset number of the windings.
In some embodiments of the present disclosure, the predetermined number is N, 10 ≦ N ≦ 30 and N is an integer. For example, the preset number is 20.
For example, if the standard window has a size capable of accommodating 20 windings and the width of the windings is P, the standard window may be a square with a side length equal to 20 × P.
Selecting the appropriate standard window may further improve the accuracy of the analysis of the winding quality. If the standard window is too large, each target wiring area is too large, so that the granularity of the winding quality analysis is coarse, and the result of the winding quality analysis is not accurate enough. If the standard window is too small, each target wiring area is too small, the granularity of the wiring quality analysis is too small, and whether more windings are intensively circuitous at a certain position in the initial wiring area is difficult to reflect, so that the result of the wiring quality analysis is not accurate enough.
In step S12, according to the standard window, the initial routing area in the layout of the integrated circuit is divided to determine at least one target routing area, and the shape and size of the target routing area are the same as those of the standard window.
In some embodiments of the present disclosure, for example, the standard windows may be uniformly distributed in the initial routing area, so that the initial routing area is divided into a plurality of target windows having the same shape and size as the standard windows, and thus, an area corresponding to part or all of the target windows is used as the target routing area.
In some embodiments of the present disclosure, step S12 includes: according to the shape and size of the standard window, an initial wiring area in a layout of the integrated circuit is divided into a plurality of target windows, an area in the integrated circuit corresponding to each target window is used as a target wiring area, and the target windows are adjacent to each other.
In some embodiments of the present disclosure, the plurality of target windows being adjacent to each other means that two adjacent target windows are immediately adjacent, that is, there is no gap between the two adjacent target windows. For example, two target windows adjacent to each other in the left-right direction, the right side of the left target window coincides with the left side of the right target window. For another example, in two target windows adjacent to each other, the lower side of the upper target window and the upper side of the lower target window are overlapped. The fact that the target windows are adjacent to each other can guarantee that each position in the initial routing area can be divided, so that the routing at each position in the initial routing area can be analyzed, and the accuracy of routing quality analysis is further improved.
It should be understood that the plurality of target windows obtained by dividing the initial trace area shown in fig. 2B may be void-free, and fig. 2B is only a few voids are drawn for the convenience of showing the target windows in the figure.
In some embodiments of the present disclosure, the shape of the standard window is rectangular, so that the initial routing area is uniformly divided, and it is avoided as much as possible that some positions in the initial routing area are not covered by the standard window, thereby further improving the accuracy of analyzing the winding quality. Other irregular shapes such as circles tend to cause some of the initial routing area (e.g., the area between two circles) to be uncovered resulting in a reduced accuracy in analyzing the quality of the windings.
Referring back to fig. 2A, for step S20, for example, for each target routing area, at least one winding included in the target routing area is a winding group, that is, at least one winding passing through the target routing area is a winding group. For example, all of the windings passing through the target routing area are treated as a winding group.
In some embodiments of the present disclosure, routing may refer to routing connecting two different devices.
For example, an integrated circuit design tool may be used to extract at least one routing line contained in the target routing area. For example, in the scenario shown in fig. 2B, an integrated circuit design tool is used to extract at least one routing line included in the target routing area corresponding to the target window 210.
For step S30, for each target routing area, a detour degree characterizing parameter of the winding group of the target routing area is calculated.
In some embodiments of the disclosure, the detour degree characterizing parameter of the winding group may be calculated according to the detour degree of each winding in the winding group.
In some embodiments of the present disclosure, the degree of detour characterizing parameter is indicative of a winding quality of the integrated circuit. For example, a higher detour characterizing parameter indicates a higher detour of the windings of the integrated circuit.
Fig. 3A illustrates a flowchart of a method of step S30 in fig. 2A according to at least one embodiment of the present disclosure.
As shown in fig. 3A, step S30 includes steps S31 to S33.
In step S31, for each target routing area, a detour characteristic value of each winding in the winding group is calculated.
In some embodiments of the present disclosure, for each winding, a distance between a start point and an end point of the winding may be compared with a length of the winding to obtain a comparison result, so as to determine a detour characteristic value of the winding according to the comparison result.
Fig. 3B illustrates a flowchart of a method of step S31 in fig. 3A according to at least one embodiment of the present disclosure.
As shown in fig. 3B, step S31 may include steps S311 to S313.
In step S311, the length of the winding and the distance between the start point and the end point of the winding are calculated.
In some embodiments of the present disclosure, the start of the routing may be one of the two devices to which the routing is connected and the end of the routing may be the other of the two devices to which the routing is connected.
In some embodiments of the present disclosure, the distance between the start and end points of the winding may be a manhattan distance between the start and end points of the winding. The Manhattan distance dis1 between two points is calculated as:
dis1＝|x2-x1|+|y2-y1|，
wherein (x)1，y1) Is the coordinate of one of two points, (x)2，y2) The coordinates of the other of the two points.
For example, in the scenario shown in fig. 1A, 1B, and 2B, where the starting point of the winding is device a and the ending point of the winding is device D, (x)1，y1) May be the coordinates of device A, (x)2，y2) May be the coordinates of the device D. For example, the coordinates of the center point of the device a are the coordinates of the device a, and the coordinates of the center point of the device D are the coordinates of the device D.
In other embodiments of the present disclosure, the distance between the starting point and the ending point may be a euclidean distance between the starting point and the ending point. The Euclidean distance dis2 between two points is calculated by the formula:
wherein (x)1，y1) Is the coordinate of one of two points, (x)2，y2) Is divided into twoCoordinates of another one of the points. For example, in the scenarios shown in fig. 1A, 1B, and 2B, (x)1，y1) May be the coordinates of device A, (x)2，y2) May be the coordinates of the device D.
In some embodiments of the present disclosure, the length of the windings refers to the length of the windings that actually need to be used. For example, in the scenario shown in FIG. 2B, the routing connecting the device A and the device D passes through the path 510 and the path 520 and the path 540 and the path 550 and the path 560, the length of the routing connecting the device A and the device D can be the arithmetic sum of the length of the routing at the path 510 and the path 520, the length of the routing at the path 520 and the path 540, the length of the routing at the path 530 and the path 550 and the length of the routing at the path 550 and the path 560, respectively.
In some embodiments of the present disclosure, the length of the routing may be obtained by an integrated circuit design tool (e.g., EDA), for example. For example, in the scenario shown in FIG. 1B, EDA may be used to obtain the length of the routing 120 that routes devices A and D.
In step S312, the ratio of the length to the distance is calculated.
For example, if the length of the wire 120 obtained by the EDA tool is S1 and the Manhattan distance between device A and device D is S2, the ratio S1/S2 is calculated.
In step S313, the difference between the ratio and 1 is calculated, and the difference is taken as a detour feature value.
For example, in the scenario described in step S312, the detour characteristic value V of the winding 1201The calculation formula of (2) is as follows:
V1＝(S1/S2)-1
in step S32, the detour feature value of each winding in the winding group is calculated to obtain a feature value calculation result of the winding group.
For example, the detour eigenvalues of each winding in the winding group are arithmetically added to obtain an eigenvalue sum, and the eigenvalue sum is used as an eigenvalue calculation result. For example, the winding group of the target routing area 210 includes 10 windings (not all windings are shown in fig. 2B), and the detour characteristic values of the 10 windings are calculated as V according to step S311、V2、……V10Then V is calculated in step S321、V2、……V10Is arithmetically added, V is1、V2、……V10Is added as a result of the calculation of the characteristic values of the winding groups of the target routing area 210.
In other embodiments of the present disclosure, for example, an average value of the detour characteristic values of each winding in the winding group may be calculated, and the average value may be used as the characteristic value calculation result.
In step S33, based on the result of the feature value calculation, a detour degree characterizing parameter of the winding group is determined to determine the winding quality of the integrated circuit according to the detour degree characterizing parameter.
In some embodiments of the present disclosure, the feature value calculation result is used as a detour degree characterizing parameter. For example, the feature value calculation result is the feature value sum SsumThen, in step S33, the calculation formula of the winding degree characterization parameter C of the winding group is as follows:
C＝Ssum
in this embodiment, for example, in the scenario of the above step S32, the detour degree characterizing parameter C of the winding group of the target routing area 210 is equal to (V)1+V2+……+V10)。
In other embodiments of the disclosure, a ratio of the characteristic value calculation result to the number of windings in the winding group is calculated, and the ratio is used as a detour degree characterization parameter to determine the winding quality of the integrated circuit according to the detour degree characterization parameter.
For example, the feature value calculation result is the feature value sum SsumAnd if the number of the winding wires in the winding group is M, the calculation formula of the roundabout degree characterization parameter C is as follows:
C＝Ssum/M
wherein M is an integer greater than 0.
In this embodiment, for example, in the scenario of the above step S32, the detour degree characterizing parameter C of the winding group of the target routing area 210 is equal to (V)1+V2+……+V10)/10。
In at least one embodiment of the present disclosure, it can be determined whether more windings are intensively detoured in the target routing area by calculating the detouring characteristic value of each winding of the winding group in each target routing area, and if more windings are intensively detoured in the target routing area, it indicates that the winding quality of the integrated circuit is low, so that the layout of the integrated circuit needs to be adjusted and optimized.
Fig. 4 is a flowchart illustrating another winding quality analysis method for an integrated circuit according to at least one embodiment of the disclosure.
As shown in fig. 4, the method further includes steps S40 and S50 in addition to steps S10 to S30 shown in fig. 2A.
In step S40, a display image element corresponding to the target routing area through which the winding group passes is determined according to the detouring degree characterizing parameter of the winding group.
In some embodiments of the present disclosure, the display image element may be a single color. For example, each detouring degree characterizing parameter corresponds to a color, and a single color image formed by the color corresponding to the detouring degree characterizing parameter is a display image element corresponding to the target routing area. In other embodiments of the present disclosure, the display image elements may be patterns. Different detour degree characterizing parameters may correspond to different patterns. The correspondence between the detour degree characterizing parameter and the pattern may be predetermined.
In some embodiments of the present disclosure, the degree of detour characterizing parameter is positively correlated with the degree of saliency of the displayed image elements. For example, the higher the grayscale value of the display image element, the more conspicuous the degree of saliency is, and thus the detour degree characterizing parameter may be positively correlated with the grayscale value of the display image element.
In step S50, a display image element is displayed in the target trace area.
For example, the target trace area (i.e., the area corresponding to the target window) is filled with a color corresponding to the detour degree characterization parameter.
The embodiment described in fig. 4 can not only intuitively reflect the detouring degree characterizing parameters of each target routing region through the display image elements, but also simultaneously display the display image elements of each of the plurality of target routing regions in the integrated circuit layout, so that the detouring degree characterizing parameters of all the target routing regions can be displayed on the whole or on the whole, and a designer of the integrated circuit can quickly determine the winding quality of the integrated circuit according to the display image elements, so that the winding quality is visualized and visualized.
Fig. 5A illustrates a flowchart of a method of step S40 in fig. 4 according to at least one embodiment of the present disclosure.
As shown in fig. 5A, step S40 includes step S41 and step S42.
In step S41, a parameter interval to which the detour degree characterizing parameter of the winding group belongs is determined according to the detour degree characterizing parameter of the winding group.
In step S42, the display image element corresponding to the parameter interval is used as the display image element corresponding to the target routing area through which the winding group passes.
In some embodiments of the present disclosure, the display image elements corresponding to different parameter intervals are different. The parameter interval may be a range of values. In some embodiments of the present disclosure, a center value of the parameter interval is positively correlated with a degree of saliency of the display image element. For example, generally, the larger the grayscale value, the more conspicuous the display image element, and the center value of the parameter interval may be positively correlated with the grayscale value of the display image element. That is, the larger the center value of the parameter interval is, the larger the gradation value of the display image element corresponding to the parameter interval is. For another example, as the normal tone is warmer and the display image element is more conspicuous, the warmer tone may be used to correspond to the center value of the larger parameter interval.
In this embodiment, the larger detouring degree characterizing parameter corresponds to a more striking display image element, which is convenient for a user to conveniently observe which target routing areas have a larger detouring degree, thereby improving user experience.
Fig. 5B is a schematic diagram illustrating displaying a display image element in a target trace area according to at least one embodiment of the disclosure.
As shown in fig. 5B, the central value of the parameter interval to which the detour degree characterization parameter of the winding group of the target routing area between the paths 510-520-530 belongs is smaller than the central value of the parameter interval to which the detour degree characterization parameter of the winding group of the target routing area between the paths 530-540 belongs, and the gray value of the display image element displayed in the target routing area between the paths 510-520-530 is smaller than the gray value of the display image element displayed in the target routing area between the paths 530-540.
The detouring degree characterizing parameter of the winding group of the target routing area between the path 540 and the path 550 and the path 530 belongs to the same parameter region, and the display image elements displayed in the target routing area between the path 540 and the path 550 and the path 510 and the path 520 and the path 530 are the same.
For example, a corresponding relationship between the parameter interval and the display image element may be established in advance, and then the parameter interval to which the detour degree characterization parameter belongs may be determined, so as to determine the display image element corresponding to the detour degree characterization parameter according to the corresponding relationship.
In some embodiments of the present disclosure, the width of the parameter interval may be determined, for example, according to a maximum value of the detour degree characterizing parameter. For example, the detour degree characterizing parameters of each winding group can be compared with each other to obtain the maximum value of the detour degree characterizing parameters. For example, the maximum value of the detour degree characterizing parameter is directly related to the width of the parameter interval, i.e. the width of the parameter interval is larger when the maximum value of the detour degree characterizing parameter is larger. For example, if the maximum value of the detour degree characterizing parameter is 20, the width of the parameter interval may be set to 2. For another example, if the maximum value of the detour degree characterizing parameter is 10, the width of the parameter interval may be set to 1.
Of course, those skilled in the art can set the width of the parameter interval according to the actual situation, and the disclosure is not limited thereto.
Fig. 6A is a flow chart illustrating another winding quality analysis method for an integrated circuit according to at least one embodiment of the present disclosure.
As shown in fig. 6A, the method further includes a step S60 in addition to the steps S10 to S30 shown in fig. 2A.
In step S60, the layout of the integrated circuit is adjusted based on the detour degree characterization parameter.
For example, the layout of the devices in the layout of the integrated circuit is adjusted according to the detour degree characterization parameter.
Fig. 6B illustrates a schematic diagram of adjusting a layout of an integrated circuit according to at least one embodiment of the present disclosure.
As shown in FIG. 6B, since device B causes the routing connecting device A and device D to detour at the initial location 610, the length of the routing connecting device A and device D can be changed by adjusting the location of device B in the integrated circuit layout 100.
As shown in fig. 6B, the position of the device B in the integrated circuit layout 100 may be adjusted from the initial position 610 to the target position 620, such that the routing lines connecting the device a and the device D are a straight line, and thus the detour degree characterizing parameter of at least one target routing area where the path 530 and the path 540 are located is reduced, so as to reduce the detour degree of the routing lines connecting the device a and the device D.
In some embodiments of the disclosure, after the layout of the integrated circuit is adjusted according to the detour degree characterization parameter, the integrated circuit may be re-wired according to the adjusted layout of the integrated circuit to obtain a new layout of the integrated circuit, the new layout of the integrated circuit may be analyzed again according to the method described in fig. 2A, and the layout of the devices in the layout of the integrated circuit may be adjusted again according to the analysis result of the routing quality until the routing quality meets the requirements of the designer of the integrated circuit.
Fig. 7 is a flowchart illustrating another winding quality analysis method for an integrated circuit according to at least one embodiment of the disclosure.
As shown in fig. 7, the method includes steps S701 to S707.
Step S701: and finishing the layout of the integrated circuit and carrying out physical winding.
For example, an integrated circuit may be laid out using an integrated circuit design tool (e.g., EDA), and after the layout of the integrated circuit is completed, physical routing may be performed using the integrated circuit design tool.
Step S702: and determining the size of a standard window of the square, and dividing the initial wiring area into a plurality of standard windows.
For example, the size of the standard window may be determined according to step S11 described in fig. 2C, and the initial trace area is divided according to step S12, so that the initial trace area is divided into a plurality of standard windows. One standard window is a target routing area.
Step S703: and extracting the winding passing through each standard window according to the standard windows.
For example, the routing through each standard window may be extracted using an integrated circuit design tool (e.g., EDA). At least one wire passing through each standard window (i.e., the target routing area) is treated as a wire winding group. For example, for each standard window, all of the windings passing through the standard window are treated as a winding group.
The operation performed in step S703 may be similar to the operation performed in step S20 described in fig. 2A, and is not described herein again.
Step S704: and calculating the ratio of the length of each winding to the Manhattan distance, calculating the difference between the ratio and 1, and taking the difference as the roundabout characteristic value of the winding.
The operations performed in step S704 may be similar to the operations performed in steps S311 to S313 described in fig. 3B, and are not described herein again.
Step S705: and calculating the sum of the detour characteristic values of all the winding wires in the area corresponding to each standard window (namely, the target routing area), wherein the sum is used as a detour degree characterization parameter.
The operations performed in step S705 may be similar to the operations performed in steps S31-S33 described in fig. 3A, and are not described herein again.
Step S706: and determining a parameter interval to which each detour degree characterization parameter belongs, and determining a display image element corresponding to the standard window. The standard windows of the same parameter interval are marked as the same display image element.
The operations performed in step S706 may be similar to the operations performed in steps S41-S42 described in fig. 5A, and are not described herein again.
Step S707: and displaying the determined display image elements in the area corresponding to the standard window (namely, the target wiring area) so as to observe the winding circuitous condition of different target wiring areas.
The operation performed in step S707 may be similar to the operation performed in step S50 described in fig. 4, and is not described herein again.
In some embodiments of the present disclosure, since the integrated circuit tends to be a multi-layer structure, the routing quality of the integrated circuit may be analyzed layer by layer according to the above-described method.
Fig. 8 is a schematic block diagram of a winding quality analysis apparatus 800 for an integrated circuit according to at least one embodiment of the present disclosure.
For example, as shown in fig. 8, the winding quality analyzing apparatus 800 of the integrated circuit includes an acquiring unit 810, a determining unit 820, and a calculating unit 830. The winding quality analyzing apparatus 800 can be used for designing an integrated circuit.
The obtaining unit 810 is configured to obtain at least one target routing area from a layout of the integrated circuit. The acquisition unit 810 may perform step S10 described in fig. 2A, for example.
The determining unit 820 is configured to determine a winding group passing through each of the at least one target routing area, the winding group including at least one winding. The determination unit 820 may perform step S20 described in fig. 2A, for example.
The calculating unit 830 is configured to calculate, for each target routing area, a detour degree characterizing parameter of the routing group, so as to determine the routing quality of the integrated circuit according to the detour degree characterizing parameter. The calculation unit 830 may, for example, perform step S30 described in fig. 2A.
In some embodiments of the present disclosure, the computing unit comprises: the first calculating subunit is configured to calculate a roundabout characteristic value of each winding in the winding group for each target wiring area; the second calculating subunit is configured to calculate the detour characteristic value of each winding in the winding group to obtain a characteristic value calculating result of the winding group; and a quality determination subunit configured to determine a detour degree characterization parameter of the winding group based on the feature value calculation result to determine the winding quality of the integrated circuit according to the detour degree characterization parameter.
In some embodiments of the present disclosure, the second calculation subunit includes: and the arithmetic subunit is configured to perform arithmetic addition on the detour characteristic value of each winding in the winding group to obtain a characteristic value sum, and the characteristic value sum is used as a characteristic value calculation result.
In some embodiments of the present disclosure, the mass-determining subunit comprises: the first parameter determining subunit is configured to take the feature value calculation result as a roundabout degree characterization parameter; or the second parameter determining subunit is configured to calculate a ratio of the characteristic value calculation result to the number of the windings in the winding group, and use the ratio as a detour degree characterization parameter so as to determine the winding quality of the integrated circuit according to the detour degree characterization parameter.
In some embodiments of the present disclosure, the first computing subunit includes: a distance calculating subunit configured to calculate the length of the winding and the distance between the start point and the end point of the winding; the characteristic value determining subunit is configured to calculate a ratio of the length to the distance; and calculating a difference between the ratio and 1, and taking the difference as a detour characteristic value.
In some embodiments of the present disclosure, the distance comprises a euclidean distance or a manhattan distance.
In some embodiments of the present disclosure, the winding quality analyzing apparatus of an integrated circuit further includes an element determining unit and a display unit on the basis of the foregoing embodiments.
The element determining unit is configured to determine display image elements corresponding to a target wiring area through which the winding group passes according to the roundabout degree characterization parameter of the winding group; and
the display unit is configured to display the display image elements in the target routing area.
In some embodiments of the present disclosure, the element determination unit includes: the interval determining subunit is configured to determine a parameter interval to which the detour degree characterization parameter of the winding group belongs according to the detour degree characterization parameter of the winding group; and the element determining subunit is configured to take the display image element corresponding to the parameter interval as the display image element corresponding to the target wiring area through which the winding group passes.
In some embodiments of the present disclosure, the display image elements are a single color or pattern.
In some embodiments of the present disclosure, the display image elements corresponding to different parameter intervals are different.
In some embodiments of the present disclosure, the obtaining unit 810 includes: a window determining subunit configured to determine a standard window; and the dividing subunit is configured to divide an initial wiring region in the layout of the integrated circuit according to the standard window so as to determine at least one target wiring region, and the shape and the size of the target wiring region are the same as those of the standard window.
In some embodiments of the present disclosure, the window determining subunit includes: a line width acquisition subunit configured to acquire a line width of the winding line; and a size determining subunit configured to determine the size of the standard window according to the line width of the winding.
In some embodiments of the present disclosure, the sizing subunit includes: a number determining subunit configured to determine a preset number of windings accommodated by the standard window; and a window size determining subunit configured to determine the size of the standard window according to the line width and the preset number of the windings.
In some embodiments of the present disclosure, dividing the sub-unit includes: and the dividing window subunit is configured to divide an initial wiring area in the layout of the integrated circuit into a plurality of target windows according to the shape and the size of the standard window, and take an area in the integrated circuit corresponding to each target window as a target wiring area, wherein the plurality of target windows are adjacent to each other.
In some embodiments of the present disclosure, the winding quality analyzing apparatus of an integrated circuit further includes an adjusting unit configured to adjust a layout of the integrated circuit based on the detour degree characterizing parameter, based on the foregoing embodiments.
For example, the obtaining unit 810, the determining unit 820, and the calculating unit 830 may be hardware, software, firmware, and any feasible combination thereof. For example, the obtaining unit 810, the determining unit 820 and the calculating unit 830 may be special or general circuits, chips or devices, and may also be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.
It should be noted that, in the embodiment of the present disclosure, each unit of the winding quality analyzing apparatus 800 of the integrated circuit corresponds to each step of the aforementioned winding quality analyzing method, and for specific functions of the winding quality analyzing apparatus 800 of the integrated circuit, reference may be made to the related description of the winding quality analyzing method of the integrated circuit, which is not repeated herein. The components and structure of the winding quality analyzing apparatus 800 of the integrated circuit shown in fig. 8 are exemplary only, not limiting, and the winding quality analyzing apparatus 800 of the integrated circuit may further include other components and structures as necessary.
At least one embodiment of the present disclosure also provides an electronic device comprising a processor and a memory, the memory including one or more computer program modules. One or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for implementing the winding quality analysis method for an integrated circuit as described above. The electronic equipment can intuitively embody the winding circuitous degree in the target wiring area in the integrated circuit through the circuitous degree representation parameters and estimate the winding quality no longer only by observation, thereby reducing the time cost and the labor cost consumed by analyzing the winding quality of the integrated circuit, improving the quantitative degree of the winding quality analysis of the integrated circuit and improving the accuracy of analyzing the winding quality of the integrated circuit.
Fig. 9 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 9, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 910 is configured to execute non-transitory computer readable instructions, which when executed by the processor 910 may perform one or more of the steps of the method for routing quality analysis of an integrated circuit as described above. The memory 920 and the processor 910 may be interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, the processor 910 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 910 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 900 to perform desired functions.
For example, memory 920 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 910 to implement various functions of electronic device 900. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.
It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the winding quality analysis method of the integrated circuit for specific functions and technical effects of the electronic device 900, and details are not described herein again.
Fig. 10 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 1000 is suitable for implementing a winding quality analysis method of an integrated circuit provided by the embodiment of the disclosure. The electronic device 1000 may be a terminal device or the like. It should be noted that the electronic device 1000 shown in fig. 10 is only one example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
As shown in fig. 10, electronic device 1000 may include a processing means (e.g., central processing unit, graphics processor, etc.) 1010 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)1020 or a program loaded from storage device 1080 into a Random Access Memory (RAM) 1030. In the RAM 1030, various programs and data necessary for the operation of the electronic apparatus 1000 are also stored. The processing device 1010, the ROM 1020, and the RAM 1030 are connected to each other by a bus 1040. An input/output (I/O) interface 1050 is also connected to bus 1040.
Generally, the following devices may be connected to the I/O interface 1050: input devices 1060 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, or the like; an output device 1070 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, or the like; storage 1080 including, for example, tape, hard disk, etc.; and a communication device 1090. The communication means 1090 may allow the electronic device 1000 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 10 illustrates an electronic device 1000 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 1000 may alternatively be implemented or provided with more or less means.
For example, according to an embodiment of the present disclosure, the winding quality analysis method of the integrated circuit described above may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the winding quality analysis method of the integrated circuit described above. In such embodiments, the computer program may be downloaded and installed from a network through communication device 1090, or from storage device 1080, or from ROM 1020. When executed by the processing device 1010, the computer program may implement the functions defined in the winding quality analysis method for an integrated circuit provided by the embodiments of the present disclosure.
At least one embodiment of the present disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, may implement the winding quality analysis method of an integrated circuit described above. By utilizing the computer readable storage medium, the winding quality of the integrated circuit can be evaluated through the roundabout degree characterization parameter, the roundabout degree of winding in a target wiring area in the integrated circuit can be visually embodied through the roundabout degree characterization parameter, and the winding quality does not need to be estimated only by observation, so that the time cost and the labor cost consumed by analyzing the winding quality of the integrated circuit are reduced, the quantification degree of the winding quality analysis of the integrated circuit is improved, and the accuracy of analyzing the winding quality of the integrated circuit is improved.
Fig. 11 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in fig. 11, storage medium 1100 is used to store non-transitory computer readable instructions 1110. For example, the non-transitory computer readable instructions 1110, when executed by a computer, may perform one or more steps of a method of wire quality analysis according to an integrated circuit as described above.
The storage medium 1100 may be applied to the electronic apparatus 900 described above, for example. For example, the storage medium 1100 may be the memory 920 in the electronic device 900 shown in fig. 9. For example, the related description about the storage medium 1100 may refer to the corresponding description of the memory 920 in the electronic device 900 shown in fig. 9, and is not repeated here.
The following points need to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.
Claims (18)
1. A winding quality analysis method of an integrated circuit comprises the following steps:
acquiring at least one target wiring area from the layout of the integrated circuit;
determining a winding group passing through each target routing area in the at least one target routing area, wherein the winding group comprises at least one winding; and
and calculating a detouring degree characterization parameter of the winding group aiming at each target wiring area so as to determine the winding quality of the integrated circuit according to the detouring degree characterization parameter.
2. The method of claim 1, wherein calculating, for each target routing area, a detour level characterizing parameter of the routing group to determine a routing quality of the integrated circuit according to the detour level characterizing parameter comprises:
calculating a circuitous characteristic value of each winding in the winding group aiming at each target wiring area;
calculating the circuitous characteristic value of each winding in the winding group to obtain a characteristic value calculation result of the winding group; and
and determining a detour degree characterization parameter of the winding group based on the characteristic value calculation result so as to determine the winding quality of the integrated circuit according to the detour degree characterization parameter.
3. The method of claim 2, wherein calculating the detour characteristic value of each winding in the winding group to obtain the characteristic value calculation result of the winding group comprises:
and arithmetically adding the circuitous characteristic values of each winding in the winding group to obtain a characteristic value sum, and taking the characteristic value sum as a characteristic value calculation result.
4. The method of claim 2, wherein determining a detour level characterizing parameter of the winding group based on the characteristic value calculation to determine a winding quality of the integrated circuit based on the detour level characterizing parameter comprises:
taking the feature value calculation result as the roundabout degree characterization parameter; or
And calculating the ratio of the characteristic value calculation result to the number of the winding in the winding group, and taking the ratio as the detour degree characterization parameter so as to determine the winding quality of the integrated circuit according to the detour degree characterization parameter.
5. The method of claim 2, wherein calculating, for each target routing area, a detour characteristic value for each winding in the winding group comprises:
calculating the length of the winding and the distance between the starting point and the end point of the winding;
calculating a ratio of said length to said distance; and
calculating a difference between the ratio and 1, and taking the difference as the detour characteristic value.
6. The method of claim 5, wherein the distance comprises a Euclidean distance or a Manhattan distance.
7. The method of claim 1, further comprising:
determining display image elements corresponding to a target wiring area through which the winding group passes according to the roundabout degree characterization parameter of the winding group; and
and displaying the display image elements in the target wiring area.
8. The method of claim 7, wherein determining, according to the detouring degree characterization parameter of the winding group, a display image element corresponding to a target routing area through which the winding group passes includes:
determining a parameter interval to which the detouring degree representation parameter of the winding group belongs according to the detouring degree representation parameter of the winding group; and
and taking the display image element corresponding to the parameter interval as a display image element corresponding to a target wiring area through which the winding group passes.
9. The method of claim 7, wherein the display image element is a single color or pattern.
10. The method of claim 8, wherein the display image elements for different parameter intervals are different.
11. The method of claim 1, wherein obtaining the at least one target routing area from a layout of the integrated circuit comprises:
determining a standard window; and
according to the standard window, dividing an initial wiring area in the layout of the integrated circuit to determine at least one target wiring area, wherein the shape and the size of the target wiring area are the same as those of the standard window.
12. The method of claim 11, determining the criteria window comprises:
obtaining the line width of the winding; and
and determining the size of the standard window according to the line width of the winding.
13. The method of claim 12, wherein determining the size of the standard window based on the linewidth of the routing comprises:
determining a preset number of windings accommodated by the standard window; and
and determining the size of the standard window according to the line width of the winding and the preset number.
14. The method of claim 11, wherein dividing an initial routing region in a layout of the integrated circuit according to the standard window to determine the at least one target routing region comprises:
according to the shape and the size of the standard window, dividing an initial wiring area in the layout of the integrated circuit into a plurality of target windows, and taking an area in the integrated circuit corresponding to each target window as one target wiring area, wherein the target windows are adjacent to each other.
15. The method of any of claims 1-14, further comprising:
and adjusting the layout of the integrated circuit based on the roundabout degree characterization parameter.
16. A winding quality analyzing apparatus for an integrated circuit, comprising:
the acquisition unit is configured to acquire at least one target routing area from the layout of the integrated circuit;
the determining unit is configured to determine a winding group passing through each target routing area in the at least one target routing area, wherein the winding group comprises at least one winding; and
and the calculating unit is configured to calculate a detouring degree characterization parameter of the winding group aiming at each target wiring area so as to determine the winding quality of the integrated circuit according to the detouring degree characterization parameter.
17. An electronic device, comprising:
a processor;
a memory including one or more computer program modules;
wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for implementing the winding quality analysis method of the integrated circuit of any of claims 1-15.
18. A computer readable storage medium storing non-transitory computer readable instructions which, when executed by a computer, implement the method of wire quality analysis of an integrated circuit of any of claims 1-15.
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