CN112531031A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN112531031A
CN112531031A CN202010542982.2A CN202010542982A CN112531031A CN 112531031 A CN112531031 A CN 112531031A CN 202010542982 A CN202010542982 A CN 202010542982A CN 112531031 A CN112531031 A CN 112531031A
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fin
strain
implant
type
finfet
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CN202010542982.2A
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Chinese (zh)
Inventor
林育樟
张添舜
聂俊峰
张惠政
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112531031A publication Critical patent/CN112531031A/en
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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Abstract

The present disclosure relates to semiconductor devices. The fin-shaped field effect transistor device comprises a channel region including a component element belonging to a group of the periodic table and an excess atom, wherein the excess atom is nitrogen or belongs to the group of the periodic table, and a concentration of the excess atom in the channel region is between about 1019cm‑3To about 1020cm‑3In the meantime.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
Embodiments of the present invention relate generally to semiconductor manufacturing and, more particularly, to an apparatus and method for manufacturing the same using ion implantation.
Background
In recent developments in the semiconductor industry, fin field effect transistors are employed instead of planar transistors. In a finfet, the transistor channel is formed substantially in a high aspect ratio structure, commonly referred to as a fin. The gate of the finfet covers not only the top of the fin but also the sides of the fin. This arrangement has several advantages over planar transistors, including greater reliability at the same performance and greater control over channel inversion.
Disclosure of Invention
In one embodiment, a semiconductor device includes a transistor and an isolation region adjacent to the transistor. The transistor has a channel region containing a constituent element and an excess atom, and the constituent element belongs to a group of the periodic table of elements, wherein the excess atom is nitrogen or belongs to the group of the periodic table of elements. The concentration of excess atoms in the channel region is between about 1019cm-3To about 1021cm-3In the meantime. The isolation region also contains excess atoms, and the concentration of the excess atoms in the isolation region is between about 1020cm-3To about 1021cm-3In the meantime.
In one embodiment, a semiconductor device includes a gate, wherein a width of an upper side of the gate is greater than a width of a lower side of the gate by more than 1nm, a channel region including a constituent element belonging to a group of the periodic table and an excess atom being nitrogen or belonging to the group of the periodic table, and a concentration of the excess atom in the channel region is between about 1019cm-3To about 1021cm-3In the meantime.
In one embodiment, the finfet includes a channel region including a constituent element belonging to one of the periodic table of elements, and the method of fabricating the finfet includes: placing a channel mask structure on a first portion of the fin to cover the first portion of the fin, the channel mask structure not covering a second portion of the fin, and the first portion of the fin including at least a portion of the channel region, performing a first ion implantation of nitrogen or an element belonging to the group of the periodic table of elements, and annealing the first ion implantation.
Drawings
Fig. 1 is a simplified perspective view of a selected cell of a structure including two finfet transistors at a stage in the fabrication process of the finfet transistors.
Fig. 2A, 2B, 3A, 3B, 4A, and 4B are simplified cross-sectional views of selected finfet structures at various stages of a finfet fabrication process.
Figures 5A and 5B are simplified cross-sectional views of selected structures prior to a lightly doped drain process sequence of a finfet fabrication process.
Fig. 6A and 6B are simplified cross-sectional views of a selected p-type finfet structure after a strain implantation in a p-type lightly doped drain process sequence.
Figure 7 is a plan view of stress components in a p-type fin field effect transistor structure after a strain implant in a p-type lightly doped drain process sequence.
Fig. 8A and 8B are simplified cross-sectional views of a selected p-type finfet structure after source/drain recessing in the finfet fabrication process, including a strain implant in a p-type lightly doped drain process sequence.
Fig. 9A and 9B are simplified cross-sectional views of a selected p-type finfet structure after a first interlayer dielectric layer is deposited in a finfet fabrication process that includes a strain implant in a p-type lightly doped drain process sequence.
Fig. 10A and 10B are simplified cross-sectional views of a selected p-type finfet structure after removal of the gate stack in a finfet fabrication process that includes a strain implant in a p-type lightly doped drain process sequence.
Fig. 11A and 11B are simplified cross-sectional views of a selected p-type finfet structure after formation of a replacement gate in a finfet fabrication process that includes a strain implant in a p-type lightly doped drain process sequence.
Fig. 12A and 12B are simplified cross-sectional views of a selected p-type finfet structure after contacts are formed in a finfet fabrication process that includes a strain implant in a p-type lightly doped drain process sequence.
Figure 13 is a table of implantation parameters for strain implantation in a finfet in some embodiments.
FIG. 14 is a flow chart of a method of strain implantation in one embodiment.
Figure 15 is a flowchart of a method for performing a strain implant at the stage of lightly doped drain in one embodiment.
Description of reference numerals:
A-A, B-B, C-C: cutting line
110: fin
120: substrate
130: isolation region
140: dummy gate stack
510: virtual grid
520: silicon nitride layer
530: oxide layer
540: first spacer
550: channel region
560: length direction of channel
565. 575: inclination angle
570: fin width direction
610: upper fin region
625: compressive strain
630: upper side isolation region
633. 635 and 638: component of strain
640: upper side stacking region
655: lower fin portion
710: corner
810: region(s)
820: level of depression
830: second spacer
840: free full fin region
850: side wall
910: source/drain structure
920: air gap
930: contact etch stop layer
940: first interlayer dielectric layer
1010: hollow spaces
1020: width of top
1030: width of bottom
1110: second gate dielectric layer
1120: replacement gate
1210: second interlayer dielectric layer
1220: source/drain contact
1230: gate contact
1240: width of upper side
1250: width of lower side
1400. 1500: method of producing a composite material
1410. 1420, 1430, 1510, 1520, 1530, 1540, 1550: step (ii) of
Detailed Description
The different embodiments or examples provided below may implement different configurations of the present invention. The following embodiments of specific components, and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the description of forming a first element on a second element includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by additional elements other than direct contact. Moreover, various examples of the invention may be repeated using the same reference numerals for brevity, but elements having the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same correspondence.
Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.
The term "group IV semiconductor element" herein is essentially any semiconductor element consisting of a single element of group IVB of the periodic table, such as silicon or germanium. Likewise, the term "group IV semiconductor compound" is essentially any semiconductor compound of the group IVA elemental composition of the periodic table of elements, including silicon germanium, silicon germanium carbide, or silicon carbide, regardless of whether the composition of the compound is fixed or varies with position. Furthermore, the term "group III-V semiconductor compound" is essentially any semiconductor compound consisting of elements of groups IIIA and VA of the periodic Table of the elements, including gallium arsenide, indium gallium arsenide, or the like. In addition, the chemical formula Si1- xGexPure or substantially pure silicon, pure or substantially pure germanium, or silicon germanium of any composition, whether fixed in composition or varying with position, is meant. In the case of zero germanium content x, Si1-xGexIs pure silicon or substantially pure silicon. Si at a germanium content x of 1 or 100%1-xGexIs pure germanium or substantially pure germanium.
The terms "p-FinFET" and "n-FinFET" are used herein to refer to n-type and p-type fin field effect transistors, respectively. Furthermore, the term "source-drain" is intended to mean either a source or a drain. For example, the source-drain regions are regions that are, or are intended to be, sources or drains of transistors. The term "implant species" refers to an implant species, and the term "implant gas" refers to a gas used to implant a species in an ion implanter. For example, the implant gas silicon tetrafluoride may be used to implant the implant species Si. The strain or stress may be represented by arrows in the figures. However, the length or width of the arrows is not intended to indicate absolute or relative strength of stress or strain unless explicitly stated otherwise in the specification.
In a semiconductor manufacturing process, one or more annealing steps may be performed after the ion implantation step. Here an annealing step that occurs earlier than any other annealing step after the ion implantation step may be considered as annealing the ion implantation.
Some embodiments disclosed herein illustrate fabrication processes for finfet transistors, but the disclosed processes may also be applied to other structures. Figure 1 is a simplified perspective view of a selected cell of a structure containing two finfet channel channels at a stage in the fabrication process of a finfet. In the stage of the fabrication process shown in fig. 1, fins 110 are formed on substrate 120, and isolation regions 130 separate fins 110 from each other and from other fins (not shown). Furthermore, dummy gate stack 140 is along sidewalls of fin 110 and on an upper surface of fin 110. Two transistor channel regions may be formed in the portion of fin 110 covered by dummy gate stack 140. As shown in fig. 1, the cross-sectional line a-a at any stage of the fabrication process is along a plane perpendicular to the substrate 120. Similarly, the cross-section line B-B at any stage of the fabrication process is along a plane perpendicular to the substrate 120. Similarly, the cross-sectional line C-C at any stage of the fabrication process is along a plane perpendicular to the substrate 120. FIGS. 2A to 6A and 8A to 12A refer to section line A-A shown in FIG. 1, and FIGS. 2B to 6B and 8B to 12B refer to section line B-B shown in FIG. 1.
Fig. 2A-4B are simplified cross-sectional views of selected finfet structures at various stages of a finfet fabrication process. As shown in fig. 2A and 2B, an example of a fabrication process begins with substrate 120. The substrate 120 may be a bulk semiconductor substrate, a semiconductor-on-insulator substrate, an insulating substrate, or the like. The bulk semiconductor substrate may be silicon or a semiconductor compound, which may be doped or undoped. The semiconductor-on-insulator substrate may include a layer of semiconductor material formed on an insulating layer, which may be a buried oxide layer, a silicon oxide layer, or the like, and which may be located on an underlying substrate such as a silicon substrate or a glass substrate.
In the fabrication process shown in fig. 2A and 2B, the material layer for fin 110 may be located on substrate 120. In various examples, the material used for fin 110 may include one or more semiconductor layers deposited on substrate 120, and the deposition method may be epitaxy. Fin 110 may be formed from a material that is different than the underlying base material, and may be undoped or doped during or after growth. For example, the material used for fins 110 may be or include silicon, silicon germanium, pure or substantially pure germanium, silicon carbide, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like.
It is contemplated herein that in other fabrication processes, no material is specifically deposited for fin 110, and fin 110 may be produced from substrate 120. In these processes, the lines between the materials used for fin 110 and substrate 120 in the various figures do not represent changes in material properties, but rather represent the approximate bottom of fin 110 after fabrication of the fin is complete.
In fig. 3A and 3B, fin 110 is located on substrate 120. The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-aligned processes that produce a pattern pitch that is smaller than that obtained using a single direct lithography process. For example, a sacrificial layer may be formed on a substrate and patterned using a photolithography process. Spacers may be formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer may then be removed and the remaining spacers may be used to pattern the fins.
The fins may be created by a variety of methods, including etching regions of layers on a substrate, or depositing fin material into narrow trenches. Regions of the layer may be etched in the process to create fins, and the fin pattern may be transferred to one or more underlying masking layers. These masking layers may be or include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof. An anisotropic etch may then be used to remove material outside the fin regions.
In fig. 4A and 4B, isolation region 130 is located between fins 110. The isolation region 130 may comprise or may be an insulating material such as silicon oxide, silicon nitride, the like, or combinations thereof, and may be formed by a suitable deposition process. For example, the isolation region 130 may comprise silicon oxide formed by a flowable chemical vapor deposition process. Other insulating materials formed by any acceptable process may also be used. A planarization process, such as chemical mechanical polishing, may be used to remove excess material such that the insulative material is coplanar with the upper surface of fin 110. The insulating material may then be recessed to form isolation regions 130, such that fins 110 protrude from between isolation regions 130. The recessing of the insulating material may be performed using any acceptable etching process, such as an etching process that is selective to the insulating material. The upper surface of the isolation region 130 may be flat as shown, convex, concave, or present a more complex shape depending on process details.
In other fabrication processes, the fin is formed by depositing fin material into narrow trenches, which is more complex than the above process and involves additional structures not shown. In one example of a process, a dielectric layer may be formed on a top surface of a semiconductor substrate 120, a trench may be etched through the dielectric layer to form a trench, a fin material may be epitaxially grown in the trench, and the dielectric layer may be recessed to allow the fin material to protrude from the dielectric layer and form a fin. The epitaxial material, which may be the same or different from the substrate, may be undoped or doped as grown or after growth. In these processes, it is particularly advantageous to grow different materials for the n-type and p-type finfet transistors, respectively, such as to maximize carrier mobility in each device type. For example, the composition of the fin or portion thereof may be silicon germanium, silicon carbide, pure or substantially pure germanium, a group III-V semiconductor compound, a group II-VI semiconductor compound, or the like. Possible materials for forming the III-V semiconductor compound include, but are not limited to, gallium arsenide, indium gallium arsenide, aluminum arsenide, indium phosphide, gallium nitride, gallium antimonide, aluminum phosphide, gallium phosphide, or the like.
An appropriate well region (not shown) may be formed in fin 110 and/or substrate 120. For example, a p-type well may be formed where the n-type finfet is to be formed, an n-type well may be formed where the p-type finfet is to be formed, or both a p-type well and an n-type well may be formed. The doping for the p-type well and the n-type well may be provided by ion implantation. In summary, fin 110, isolation region 130, substrate 120, and any other structures present on the substrate may contain dopants from the well implant when the well implant. The dopant used to form the n-type well may be phosphorus, arsenic, antimony, or the like. The dopant used to form the p-type well may be boron, boron difluoride, indium, or the like. One or more annealing steps may be performed to activate the implanted dopants. In some processes, the substrate and/or fin material may be doped during crystal growth or deposition, and a well implant may not be necessary.
Fig. 5A and 5B are simplified cross-sectional views of selected structures prior to a lightly doped drain process sequence of a finfet fabrication process, as described below. The dummy gate stack 140 of fig. 1 may include a dummy gate 510 and one or more additional layers, such as a silicon nitride layer 520 and an oxide layer 530. Furthermore, a first gate dielectric layer (not shown) may be located between fin 110 and dummy gate 510. The first gate dielectric layer may comprise or may be silicon oxide, silicon nitride, a high-k dielectric layer, the like, or multiple layers thereof, and may be thermally grown and/or chemically or conformally deposited (by suitable deposition techniques). Once the fabrication process is complete, channel region 550 of fin 110 may serve as a channel for a fin field effect transistor. In some examples of the manufacturing process, first spacers 540 may be located on the sides of fin 110 and dummy gate stack 140. The first spacers 540 may be or include silicon nitride, silicon oxide, silicon oxynitride, or the like. In one embodiment, the first spacers 540 are silicon nitride.
In fig. 5A, the finfet has a channel length direction 560. Further, the tilt angle 565 refers to a tilt angle in a channel length direction of the finfet. Figure 5B also shows fin width direction 570. The inclination angle 575 refers to an inclination angle in the fin width direction. The ion implantation may be performed obliquely and result in a symmetric implantation profile on both sides of the symmetric structure, and is typically performed in two steps. Two halves of the total dose are implanted at an oblique angle of positive and negative values with respect to a plane perpendicular to the substrate. In the tilt-angle-free ion implantation, the total dose is implanted in a single step.
The lightly doped drain process may include an n-type lightly doped drain process sequence and/or a p-type lightly doped drain process sequence. In the case of an n-type lightly doped drain process sequence, a masking layer, such as a photoresist layer, may be deposited and patterned according to an n-type lightly doped drain pattern to cover the p-type finfet structure and expose the n-type finfet structure. Then, n-type dopant is implanted to form n-type lightly doped drain region for n-type fin field effect transistor, which can be used as donor. For example, one or more of phosphorus, arsenic, antimony, or other n-type dopants may be implanted as n-type lightly doped drain dopants to form an n-type lightly doped drain region. This implant can be considered as an n-type lightly doped drain implant. After the n-type lightly doped drain implant, the patterned photoresist layer may be removed and an n-type lightly doped drain anneal performed to activate the dopants. In the p-type lightly doped drain process sequence, a patterned masking layer (e.g., a photoresist layer deposited and patterned according to the p-type lightly doped drain pattern) may cover the n-type finfet structure and expose the p-type finfet structure. P-type dopants are then implanted to form p-type lightly doped drain regions for the p-type fin-shaped field effect transistors, which may serve as receptors. For example, one or more of boron, boron difluoride, indium, or other p-type dopants can be implanted as a p-type lightly doped drain dopant to form a p-type lightly doped drain region. This implant can be considered a p-type lightly doped drain implant. After the p-type lightly doped drain implant, the patterned photoresist layer may be removed and a p-type lightly doped drain anneal performed to activate the dopants. Without the lightly doped drain implant, the doping concentration between the channel and source/drain regions of the transistor varies dramatically, producing harmful hot electrons. A lightly doped drain implant is typically used to make the dopant concentration change between the channel and source/drain regions more gradual. The n-type lightly doped drain process sequence may be performed before or after the p-type lightly doped drain process sequence. In addition, other process steps may be performed between the process sequence of the n-type lightly doped drain and the p-type lightly doped drain. For example, after an n-type lightly doped drain process sequence and before a p-type lightly doped drain process sequence, sidewalls may be formed to advantageously affect the location of the p-type lightly doped drain doping value. In addition, in order to replace the annealing steps of the separated n-type lightly doped drain and the p-type lightly doped drain, a single lightly doped drain annealing step can be adopted to activate the dopants of the p-type lightly doped drain and the n-type lightly doped drain. In various examples of processes, the one or more annealing steps may be a rapid thermal anneal, a spike anneal, a laser anneal, or the like. The terms medium doped drain, n-type medium doped drain, and p-type medium doped drain may sometimes be used in place of the terms lightly doped drain, n-type lightly doped drain, and p-type lightly doped drain to indicate that the doping concentration used in a given process is slightly higher than the historically lower level used in the past technology generations. Other terms such as drain extension may also be used.
In the embodiments described herein, ion implantation may be advantageously performed to affect the strain in the channel region of the finfet. This implant may be referred to herein as a strain implant.
Fig. 6A and 6B are simplified cross-sectional views of a selected p-type finfet structure after a strain implant in a p-type lightly doped drain process sequence. In this embodiment, the strain implant is performed in the presence of a p-type lightly doped drain photoresist pattern. Therefore, the embodiment has the advantage of no need of additional patterning steps, thereby reducing the cost and the process complexity. In addition, the combination of the dummy gate stack 140 and the first spacers 540 may serve as a mask structure for implantation. In various embodiments, the strain implant may be performed before or after any of the one or more p-type lightly doped drain implants performed in the p-type lightly doped drain process sequence. In one embodiment, the material used for fin 110 is silicon, and the implant species used for the strain implant is also silicon. For example, silicon tetrafluoride may be employed as an injection gas to inject silicon. The implant species enter some of upper fin region 610 of fin 110, some of upper isolation region 630 of isolation region 130, and upper stack region 640 of dummy gate stack 140. Any implant species that enter the sidewalls of dummy gate stack 140 and the portion of first spacers 540 on the sidewalls of fin 110 are not shown to simplify the drawing.
In one embodiment, a single annealing step is used to anneal the p-type lightly doped drain and strain implant. This embodiment has an advantage in that no additional annealing step is required for the strain implantation. In one embodiment, a single spike rapid thermal anneal at 850 ℃ may be used as a general anneal for the p-type lightly doped drain and strain implant. The annealing step has many effects. First, the implant species during annealing diffuse outward from the implanted region into the adjacent region. If the strain implantation is performed without tilting the vertical arrows as shown in fig. 6A and 6B, the implanted species will be blocked from entering the channel region 550 by the dummy gate stack 140 and the portion of the first spacers 540 located on the sidewalls of the dummy gate stack 140, unless laterally diffused. Upon annealing, the implant species may diffuse toward and into the channel region 550. If the strain implant is angled in the direction of the channel length, a greater amount of the implant species may enter the deeper channel region 550 prior to annealing and may then further diffuse into the channel region during annealing. The amount of implant species that enters the channel region 550 depends on parameters such as the implant tilt angle and the time and temperature of the anneal. Similarly, silicon atoms implanted into upper portions of isolation regions 130 diffuse therein toward lower fin portion 655 of fin 110. In addition, silicon atoms implanted into the upper portion of the isolation region 130 may diffuse into the non-implanted regions of the isolation region 130 under the gate stack (not shown in the cross-sectional views of fig. 6A and 6B). Furthermore, many implant species occupy interstitial sites prior to annealing to bond to adjacent atoms, and thus may be incorporated into the crystalline structure during annealing, thereby increasing the level of strain in the implanted region and, thus, the level of stress applied to adjacent regions. Three, the annealing step may partially repair the significant crystalline damage caused by the strain implant.
The strain implantation of silicon creates a compressive strain in the channel region 550 of the p-type finfet. This compressive strain 625 results in a reduced strength in the cross-section of fig. 6A below the upper fin region 610 and substantially in the direction of the channel length. One advantage of this strain is that it improves the performance of p-type finfets because the compressive stress along the channel length increases hole mobility. The strain implantation in the upper isolation region 630 also creates strain, but this strain occurs primarily in regions below the channel region 550. The strain injection in the upper isolation region 630 has less impact on transistor performance since the main current flow occurs in the channel region. However, the strain component caused by the strain implantation in the upper isolation region 630 will be briefly described herein. In a simplified two-dimensional illustration, these two strain components can be resolved. The first compressive strain component occurs in a direction substantially along the fin width and reduces hole mobility in the region where it is present. The strain components (such as strain component 633 shown in fig. 6B and strain component 635 shown in fig. 6A) are present in the cross-section of fig. 6B, and are present before and after the cross-section of fig. 6A. In addition, the fin material is compressed in the inward and outward directions in figure 6A from the upper isolation regions 630 after the cross-section of figure 6A and the upper isolation regions 630 before the cross-section of figure 6A. The second compressive strain component is generated in a direction substantially along the channel length and increases hole mobility in the region where it is present to offset the first component. The strain component 638 shown in fig. 6A exists before and after the cross-section of fig. 6A.
The above-described stress components will be further illustrated in plan view. Figure 7 is a plan view of stress components in a p-type fin field effect transistor structure after a strain implant in a p-type lightly doped drain process sequence. Isolation region 130 isolates fins 110, which are sequentially covered by dummy gate stack 140. The cross-sections A-A and C-C of FIG. 7 correspond to the cross-sections A-A and C-C, respectively, of FIG. 1. Compressive strain 625 of the fin field into the transistor channel results from strain injection in the upper region of fin 110, which may increase hole mobility and improve transistor performance. It is noted that compressive strain 625 in figure 7 is shown in phantom in plan view, with the understanding that the strain occurs in the channel region of fin 110, rather than on the top of dummy gate stack 140. Compressive strain components 633 and 638 occur in regions below the channel 550 but have less of an impact on transistor performance. It should be appreciated that the component directions of the total strain, such as strain components 633 and 638, at the corners 710 of the implanted regions near the isolation region 130 reflect the simplified nature of the bi-direction described herein.
Another advantage of the strain implant of one embodiment is the enlargement of the upper stack region 640, as shown in figure 6A. For example, the top width of the gate stack of some embodiments may be increased by about 6% to about 10%. The portion of the first spacers 540 on the sidewalls of the dummy gate stacks 140 is tapered outward under the stress applied by the strain implant in the upper stack region 640. Although fig. 6A shows that the inclination of the first spacers 540 is substantially linear, it may be a non-linear shape. Enlarging the upper side stack region 640 may provide a number of advantages. These advantages will be described below in conjunction with fig. 11A and 12A.
Fig. 8A and 8B are simplified cross-sectional views of a selected p-type finfet structure after source/drain recessing in the finfet fabrication process, including a strain implant in a p-type lightly doped drain process sequence. Second spacers 830 may be placed over first spacers 540 on the sidewalls of dummy gate stack 140 and over the fins prior to this stage of the fabrication process. Since the second spacers 830 are located on the first spacers 540, the portions of the second spacers 830 located on the sidewalls of the dummy gate stacks 140 in this strain-implanted embodiment may be tapered outward.
As the mask sequence covers the n-type finfet and exposes the p-type finfet, region 810 of fin 110 is removed down to a recessed level 820. Portions of the first spacers 540 and the second spacers 830 may also be removed. After subsequent processing steps, the region 810 may serve as a source or a drain for a p-type finfet. An advantage of this embodiment is that the step of recessing the source/drains removes crystalline damage in the regions 810 that results from the strain implant and remains after annealing.
During the implantation and annealing processes, the implant species enter channel region 550 while the implant species in any portion of fin 110 remain between region 810 and the channel region. The source/drain recess process does not remove the implant species. The implanted species may provide a compressive strain, thereby enhancing mobility in the channel region. In some fabrication processes, the gate stack does not cover free full fin regions 840 of fin 110, and the step of recessing the source/drains does not remove free full fin regions 840. This region is considered to be a free full fin region that contains substantially all of the implanted species during the strain implantation step. By this manufacturing process, portions of the upper side isolation region 630 may have been removed, resulting in a reduced strain component in the region below the channel region 550. In some embodiments, the upper isolation region 630 may be substantially or completely removed.
Fig. 9A and 9B are simplified cross-sectional views of a selected p-type finfet structure after a first interlayer dielectric layer is deposited in a finfet fabrication process that includes a strain implant in a p-type lightly doped drain process sequence. A source/drain structure 910 of a p-type finfet is formed in the region 810 of fig. 8A by epitaxial growth. As shown in fig. 9B, epitaxial source/drain structures grown over adjacent fins 110 may merge to form a contiguous structure, with air gaps 920 formed below the contiguous structure. During or after growth, the source/drain regions may be doped to a dopant concentration of about 1019cm-3To about 1021cm-3In the meantime. The dopant used to form the source/drain regions of the n-type fin field effect transistor may be phosphorus, arsenic, antimony, or the like, while the dopant used to form the source/drain regions of the p-type fin field effect transistor may be boron, boron difluoride, indium, or the like.
In some embodiments, source/drain structure 910 may be formed of substantially the same material as fin 110. In other embodiments, different materials may be selected to apply a compressive stress on the channel region 550. As discussed above, if fin 110 is silicon, source/drain structure 910 may comprise silicon, silicon germanium, silicon germanium boride, germanium tin, or the like. In these embodiments, the total strain in the channel region 550 may come from the strain implantation and the source/drain structure 910. Strain implantation may enhance mobility due to stress applied by the source/drain regions.
Similar methods may be employed to create source/drain structures for n-type finfet transistors. In some embodiments, the source/drain structures may be formed from substantially the same material as the fin. In other embodiments, different materials may be selected to apply a tensile stress on the channel region of the n-type finfet. As noted above, if the fin is silicon, the source/drain regions may comprise silicon, silicon carbide, silicon phosphide, silicon carbon phosphide, or the like. In embodiments containing strain implants for n-type finfets, the total strain in the channel region of the n-type finfets may come from the strain implants and the source/drain regions of the n-type finfets. Strain implantation may enhance mobility due to stress applied by the source/drain regions.
After the source/drain regions are fabricated, a first interlayer dielectric 940 may be deposited over the finfet structure. The first interlayer dielectric 940 may be or include phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and the deposition method thereof may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. Some embodiments deposit a contact etch stop layer 930 on the finfet structure prior to depositing the first interlayer dielectric layer. The contact etch stop layer 930 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a different etch rate than the material of the overlying first interlayer dielectric 940. In an embodiment of strain implantation, the portion of the contact etch stop layer 930 located on the sidewalls of the dummy gate stack 140 may be tapered outward.
Fig. 10A and 10B are simplified cross-sectional views of a selected p-type finfet structure after removal of the gate stack in a finfet fabrication process that includes a strain implant in a p-type lightly doped drain process sequence. A planarization process, such as chemical mechanical polishing, may be performed to planarize the upper surface of the wafer in preparation for removing the dummy gate stack 140. The planarization process may stop at the top surface of the dummy gate stack 140 to leave the dummy gate stack 140 substantially intact, or may remove the upper portion of the dummy gate stack 140 and the upper portions of the first and second spacers 540, 830 along the sidewalls of the dummy gate stack 140. Any material of the dummy gate stack 140 remaining after the planarization step may then be removed to leave a void 1010 defined by the first spacers 540 on its sides, and the removal method may be a selective etch. A first gate dielectric layer (not shown) on fin 110 may be retained or removed, either completely or partially, from void 1010 for all transistors or for transistors intended to operate at a particular voltage range. In one embodiment of strain implantation, the top width 1020 of the void 1010 is greater than the bottom width 1030.
Fig. 11A and 11B are simplified cross-sectional views of a selected p-type finfet structure after formation of a replacement gate in a finfet fabrication process that includes a strain implant in a p-type lightly doped drain process sequence. The second gate dielectric layer 110 may be located in the void 1010. The second gate dielectric layer 1110 may be conformally deposited on the wafer and may comprise silicon oxide, silicon nitride, or multiple layers thereof. In some manufacturing processes, the second gate dielectric layer 1110 may comprise a high-k dielectric material having a dielectric constant greater than about 7.0, and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or combinations thereof. The deposition method of the second gate dielectric layer 1110 may be molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or the like. An advantage of the strain implant of this embodiment is the sloped profile of the first spacers 540, which facilitates the conformal deposition of the second gate dielectric 1110. The second gate dielectric layer 1110 also slopes outward.
In a fill process, a replacement gate 1120, which may comprise a metal-containing material such as tin, titania, tan, co, ru, al, w, combinations thereof, or multilayers thereof, may be deposited on the second gate dielectric 1110. Although details of the replacement gate 1120 are not shown in fig. 11A, the replacement gate 1120 may include any number of liner layers and work function adjustment layers. Another advantage of the strain implant in the p-type lightly doped drain process sequence is that the top width 1020 of the void 1010 is increased, which increases the overall volume of the replacement gate 1120 at the same depth, thereby advantageously reducing the resistance of the replacement gate, as shown in fig. 10A. Reducing the gate resistance may increase circuit speed. In another advantage, the increased top width 1020 facilitates the fill process, reducing the likelihood of any size voids forming in the replacement gate. Voids are detrimental because they increase gate resistance and degrade circuit speed.
After depositing the material for the replacement gate 1120, the portions of the second gate dielectric 1110 and the replacement gate 1120 deposited on the upper surface of the first interlayer dielectric 940 may be removed by a planarization step to obtain the structure shown in fig. 11A and 11B. It is contemplated herein that in some manufacturing processes, the replacement gates and associated dielectric layers for n-type and p-type finfets may be different. In these processes, appropriate masking methods may be employed to deposit different materials for the n-type and p-type finfets.
Fig. 12A and 12B are simplified cross-sectional views of a selected p-type finfet structure after contacts are formed in a finfet fabrication process that includes a strain implant in a p-type lightly doped drain process sequence. The second interlayer dielectric 1210 is deposited on the first interlayer dielectric 940. The second interlayer dielectric layer 1210 may be a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, which may be flowable, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The openings for the source/drain contacts 1220 may pass through the second ild 1210, the first ild 940, and the contact etch stop 930. In some fabrication processes, a gate cap (not shown) may be present on the replacement gate 1120. An opening for a gate contact 1230 is through the second interlayer dielectric 1210 and through the gate cap (if present). The openings may be formed using acceptable photolithography and etching techniques. One or more liner layers (not shown) such as diffusion barrier layers, adhesion layers, or the like may be formed in the openings. The liner layer may comprise titanium, titanium nitride, tantalum nitride, or the like. Conductive material for the source/drain contacts 1220 and the gate contact 1230 may be located in respective openings. The conductive material used for the contacts may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, may then be performed to remove excess material from the surface of the second ild 1210. An annealing process may be performed to form silicide at the interface between the source/drain structure 910 and the source/drain contacts 1220. The source/drain contacts 1220 and the gate contact 1230 may be formed in separate process sequences or the source/drain contacts 1220 and the gate contact 1230 may be formed in the same process sequence.
Although both source/drain contacts 1220 and gate contacts 1230 are present in the cross-section shown in fig. 12A, it should be understood that some or all of the contacts in some fabrication processes are not present in the cross-section of fig. 12A, but rather are present before or after the cross-section of fig. 12A. In addition, the sloped sidewalls of the source/drain contacts 1220 and the gate contact 1230 shown in fig. 12A and 12B do not represent any equivalent or unequal relationships to the sloped sidewalls of other structures in the figures, such as the sidewalls of the replacement gate 1120.
The strain implantation of this embodiment may have two additional advantages, which will be described in conjunction with FIG. 12A. First, the replacement gate 1120 has an upper width 1240 that is greater than a lower width 1250. The larger upper width 1240 may be used to replace the electrical connection between the gate 1120 and the gate contact 1230, which may be advantageous to reduce the connection resistance if the gate contact 1230 is also correspondingly sized. Furthermore, an interconnect layer (not shown) is typically deposited over the second ILD 1210 to allow various end interconnections to be formed into circuits. This embodiment facilitates the fill process used for the replacement gate 1120, which results in a taller gate and thus an increased vertical distance between the interconnect layer on one side and the substrate and finfet structure on the other side. A larger vertical distance may reduce the capacitance between structures. In some cases, reducing capacitance with this opportunity may increase circuit speed net.
Since the process steps after forming the contacts are primarily related to forming the structure on the second ild 1210, fig. 12A and 12B are cross-sectional views of a selected p-finfet structure after completion of the circuit fabrication process. As shown in fig. 12B, the stress-implanted atoms may be located in channel region 550, in free full fin region 840, and remain between source/drain structure 910 and channel region 550In any portion of the fin (not shown). As shown in fig. 12B, the stress-implanted atoms may be located in the upper isolation region 630. In which the constituent element atoms of the region are located. A constituent element of a material is defined herein as any element present in the material that has an atomic concentration of greater than about 20%. Atoms of a material component may be considered herein as constituent atoms. For example, if channel region 550 is Si0.8Ge0.2The silicon and germanium atoms of the composition are located in the channel in a ratio of about 4: 1. If the composition of the channel region is not constant in the vertical direction, the vertical concentration profile of the composition silicon and germanium atoms will reflect the vertical profile of the composition. Similarly, in an isolation region of substantially stoichiometric silicon dioxide, the composition of the silicon to oxygen atoms in the isolation region is about 1: 2. In addition, donors or acceptors may be located in these regions. For example, in the channel region of a p-type finfet, dopants such as boron or indium may be located therein. As highlighted above, in embodiments of strain implantation, the atoms from the strain implantation may also be located in various regions. These atoms enter the region during strain implantation or diffuse into the region during subsequent annealing, and are considered as excess atoms herein. The excess atoms may be interstitial or bonded to other atoms. In embodiments where the strain implant species and the constituent element are different, such as nitrogen stress implant and Si0.8Ge0.2The channel, the unwanted atoms can be resolved by chemical species, concentration profile, or the presence of any interstitial atoms. The concentration profile of the implant profile depends on the implant species, the material implanted by the implant species, the implant energy, the implant dose, and the tilt angle of the implant. These concentration profiles typically have peaks (seen as ranges) at specific depths, and sometimes approximate a gaussian function in the case of lateral coincidence. The annealing step may alter the concentration profile of the implant via diffusion, depending on the temperature-time profile of the anneal and the diffusion coefficient of the diffused species in the host material. Numerical modeling and simulation are typically used to calculate implant profiles and annealed profiles for a variety of implants. These profiles can generally be measured using measurement techniques such as secondary ion mass spectrometry and nano-secondary ion mass spectrometry. The implanted atoms are typically interstitial, although annealing assumes the implantThe implanted atoms are located in lattice sites, but some of the implanted atoms remain in interstitial spaces. The presence of any interstitial atoms may therefore indicate the presence of excess atoms. In embodiments where the stress implant species is the same as the constituent element, such as silicon stress implant into silicon or Si0.8Ge0.2In the channel, unwanted atoms can be resolved by the concentration profile or the presence of any spurious atoms.
In various embodiments of the strain implant, the excess atom concentration in the channel region 550 is between about 1019cm-3To about 1020cm-3In the meantime. In other embodiments, the concentration of excess atoms in the upper isolation region 630 is between 1020cm-3To about 1021cm-3In the meantime. In other embodiments, the concentration per unit area of excess atoms in free full fin region 840 is approximately the strain implant dose. For example, one embodiment has a concentration per unit area between 10 for p-type finfet15cm-2To about 1017cm-2In the meantime.
Figure 13 is a table of implantation parameters for strain implantation in a finfet in some embodiments. The embodiment shown in fig. 13 may be applied to a fin field effect transistor, wherein the fin material is any group IV semiconductor element or group IV semiconductor compound, such as including Si1-xGex(the content x of germanium is between 0 and 100%, silicon and germanium are contained), Si1-x-yGexCyOr the like. In one implementation of a p-type finfet, silicon tetrafluoride gas is used to implant silicon into the p-type finfet at a dose of about 1015cm-2To 1017cm-2The tilt angle is between 0 degrees and 30 degrees, and the implantation energy is between about 5keV and about 30 keV. In another embodiment, silicon tetrafluoride is used for implanting silicon at a dose of between about 1015cm-2To about 1017cm-2The tilt angle is between 0 degrees and about 30 degrees, and the implantation energy causes the implantation range R to be between about 20nm and about 40 nm. In other embodiments of p-type finfet transistors, germanium tetrafluoride gas or nitrogen gas is used to implant germanium or nitrogen, respectively.
In other embodiments, strain injection is used to increase electron mobility in an n-type finfet transistor channel. In one embodiment, carbon dioxide is used as a carbon-containing gas to implant carbon into n-type finfet with a dopant amount in excess of 1017cm-2The tilt angle is between 0 degrees and 30 degrees, and the implantation energy is less than about 15 keV. In another embodiment, carbon dioxide is used as the carbon-containing gas to implant carbon into the n-type finfet in a dosage exceeding about 1017cm-2The tilt angle is between 0 degrees to about 30 degrees, and the implantation energy causes the implantation range R to be between about 20nm to about 40 nm. In other embodiments, nitrogen gas is used to inject nitrogen into the n-type finfet.
In the embodiment illustrated in fig. 6A, first spacers 540 during the strain implant are present on fin 110 and on sidewalls of dummy gate stack 140. Various embodiments first spacers 540, a plurality of spacers, or other layers may or may not each be present on fin 110 or on sidewalls of dummy gate stack 140 during the strain implant. In some embodiments, the strain implantation parameters, such as the dose, energy, and tilt angle described below, may be appropriately adjusted to ensure that the implanted species after the anneal step are in the channel region 550 and have the advantageous concentrations described above.
In some embodiments, the fin material is a group III-V semiconductor compound, and one or more elements of groups IIIA and VA of the periodic table may serve as the implant species. For example, the fin material may be gallium arsenide, and the implant species may be nitrogen, phosphorous, arsenic, aluminum, gallium, and/or indium. In some embodiments, approximately the same dose of group IIIA and group VA elements may be implanted to approximately the same implantation range to maintain the stoichiometry of the fin. For example, the fin material may be gallium arsenide, while group VA elements (e.g., nitrogen, phosphorus, or arsenic) and group IIIA elements (e.g., aluminum, gallium, or indium) may be implanted to approximately the same dose and implant range.
In various embodiments, the annealing step used to anneal the strain implant is any annealing process compatible with the finfet fabrication process, including rapid thermal annealing, spike annealing, laser annealing, or the like. In one embodiment, a single anneal step may be used to anneal the strain and p-type lightly doped drain implant. In other embodiments, a separate strain anneal step may be performed for the strain implant. For example, if a p-type lightly doped drain anneal is performed at a lower temperature, for a shorter time, or both (as compared to the anneal of the strain implant) in the finfet fabrication process, a strain anneal is performed. In one embodiment, the p-type lightly doped drain process may be performed after patterning the photoresist by strain implantation for the p-type finfet, removing the photoresist, strain annealing, applying and patterning the photoresist for the p-type lightly doped drain, p-type lightly doped drain implantation, removing the second photoresist, and p-type lightly doped drain annealing. In another embodiment, a hard mask is used to avoid the second patterning step: the photoresist for the p-type lightly doped drain is used to pattern the hard mask, and a strain implant is performed for the p-type finfet, strain anneal, p-type lightly doped drain implant, and p-type lightly doped drain anneal, followed by removal of the hard mask. Similar embodiments may be used for n-type finfet transistors. Other embodiments are possible. For example, the strain implants for one or both of the p-type and n-type fin field effect transistors may be performed prior to the lightly doped drain process sequence, and one or more strain anneal steps may be performed to separately or together anneal the strain implants for one or both of the p-type and n-type fin field effect transistors.
In some embodiments, the strain implants may be tilted in the direction of the fin width, and may or may not be tilted in the direction of the channel length. As shown in fig. 6B, without any angled implantation in the fin width direction, the implanted atoms cannot reach the region of fin 110 under upper fin region 610. If the implant is tilted in the direction of the fin width, however, the implanted atoms will reach the region of fin 110 under upper fin region 610 and help to relieve any strain reduction on the underside of channel region 550. In some embodiments, a portion of the total strain implant dose is implanted obliquely in the direction of the fin width. In some embodiments, the strain implants are not tilted in the direction of the channel length and are tilted in the direction of the fin width. In this embodiment, the strain implant is performed in three steps. In the first step, a portion of the total dose may be implanted without tilt. The remainder of the total dose is then split in half and divided into two implants with positive and negative tilt values in the direction of the fin width. In other embodiments, the strain implant may be performed in the direction of the channel length and fin width. In this embodiment, a portion of the total dose is divided into two implants in the channel length direction with positive and negative slope values, while the remainder of the total dose is divided into two implants in the fin width direction with additional positive and negative slope values. In some embodiments, the angle of inclination in the direction of the fin width is between 0 degrees to about 30 degrees.
In some embodiments, the strain implant for the p-type fin field effect transistor may be performed at a stage of the fabrication process of the fin field effect transistor, rather than at a stage of the p-type lightly doped drain or the n-type lightly doped drain. For example, one embodiment may perform a strain implant after recessing the source/drain and before source/drain epitaxy. As shown in fig. 8A, recessing the source/drain regions may directly expose sidewalls 850 of channel region 550. The strain implant is tilted in the direction of the channel length to implant the implant species into the channel region 550. In addition, a lower implant dose may be used compared to the strain implant in the lightly doped drain process sequence. An anneal step is then performed prior to source/drain epitaxy to enhance strain and repair implant damage. In other embodiments, the source/drain epitaxy may be followed by a strain implant.
FIG. 14 is a flow chart of a method 1400 of strain implantation in one embodiment. In step 1410, a channel mask structure is located on a first portion of the fin and not on a second portion of the fin, and the first portion is located on at least a portion of the channel region. The channel mask structure may or may not include gates such as dummy gates or replacement gates, and may or may not include one or more sidewalls. The channel mask structure may be or include photoresist, silicon nitride, silicon oxide, or the like. The width of the channel masking structure may be different from the width of the channel regions, such as the structure extending beyond the channel regions or not masking all of the channel regions. In step 1420, a strain implant is performed. The channel masking structure may block at least some of the implant species from entering the channel region. In step 1430, annealing is performed.
Figure 15 is a flow chart of a method 1500 of performing a strain implant at the stage of lightly doped drain, in accordance with one embodiment. The lightly doped drain stage can be an n-type lightly doped drain or a p-type lightly doped drain stage, and the method can be applied to the n-type lightly doped drain stage for an n-type fin field effect transistor, the p-type lightly doped drain stage for a p-type fin field effect transistor, or the lightly doped drain stages for n-type and p-type fin field effect transistors. In step 1510, a gate is located over the channel region of the fin. The gate may be a dummy gate or a replacement gate. At 1520, a patterned mask layer may be placed on the wafer according to the lightly doped drain pattern. The masking layer may be a photoresist. In step 1530, a strain implant is performed. One or more lightly doped drain implants are performed 1540 and an anneal is performed 1550. If the mask layer is a photoresist, the mask layer may be removed prior to the anneal step 1550.
In other method embodiments, the order of steps 1530 and 1540 may be reversed. More commonly, one or more lightly doped drain implants are followed by a strain implant. In other embodiments, an anti-reflective coating or planarization layer may be used with the photoresist. In other embodiments, one or more hard mask layers, such as an oxide or nitride layer, may be used for the mask implant, and the photoresist may or may not be removed after patterning the one or more mask layers. Any masking layer may be removed before or after the anneal step 1550.
In one embodiment, a semiconductor device includes a transistor and an isolation region adjacent to the transistor. The transistor has a channel region containing a constituent element and an excess atom, and the constituent element belongs to a group of the periodic table of elements, wherein the excess atom is nitrogen or belongs to the group of the periodic table of elements. The concentration of excess atoms in the channel region is between about 1019cm-3To about 1021cm-3In the meantime. Isolation regionAlso contains excess atoms, and the concentration of the excess atoms in the isolation region is between about 1020cm-3To about 1021cm-3In the meantime. In one embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is a p-type fin field effect transistor, and the excess atoms are silicon. In one embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is a p-type finfet, and the excess atoms are germanium. In one embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is a p-type finfet, and the excess atoms are nitrogen. In one embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is an n-type finfet, and the excess atoms are carbon. In one embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is an n-type finfet, and the excess atoms are nitrogen. In one embodiment, the channel region is a group III-V semiconductor compound and the excess atoms are nitrogen or belong to group III or group V of the periodic Table of the elements.
In one embodiment, a semiconductor device includes a gate, wherein a width of an upper side of the gate is greater than a width of a lower side of the gate by more than 1nm, a channel region including a constituent element belonging to a group of the periodic table and an excess atom being nitrogen or belonging to the group of the periodic table, and a concentration of the excess atom in the channel region is between about 1019cm-3To about 1021cm-3In the meantime. In one embodiment, the semiconductor device is a finfet and further includes an isolation region adjacent the finfet. The isolation region comprises excess atoms, and the concentration of the excess atoms in the isolation region is between about 1020cm-3To about 1021cm-3In the meantime. In one embodiment, the fins extend above a topmost surface of the isolation region. In one embodiment, the concentration per unit area of excess atoms in the free full fin region is at least 1015cm-2。
In one embodiment, the finfet includes a channel region including a constituent element belonging to the periodic tableA method for fabricating a FinFET comprises: placing a channel mask structure on a first portion of the fin to cover the first portion of the fin, the channel mask structure not covering a second portion of the fin, and the first portion of the fin including at least a portion of the channel region, performing a first ion implantation of nitrogen or an element belonging to the group of the periodic table of elements, and annealing the first ion implantation. In one embodiment, the finfet is p-type, the channel mask structure includes a gate, the fin is a group IV semiconductor element or a group IV semiconductor compound, the ion implantation is performed with a gas selected from the group consisting of silicon hexafluoride, germanium tetrafluoride, and nitrogen, and the ion implantation dosage is about 1015cm-2To about 1017cm-2The energy of the ion implantation is between about 5keV and about 30keV, and the angle of inclination of the ion implantation in the length direction of the channel region is between 0 degree and about 30 degrees. In one embodiment, the finfet is p-type, the channel mask structure includes a gate, the fin is a group IV semiconductor element or a group IV semiconductor compound, the ion implantation is performed with a gas selected from the group consisting of silicon hexafluoride, germanium tetrafluoride, and nitrogen, and the ion implantation dosage is about 1015cm-2To about 1017cm-2The energy of the ion implantation is between about 5keV and about 30keV, the angle of inclination of the ion implantation in the length direction of the channel region is between 0 degrees and about 30 degrees, and the angle of inclination of the ion implantation in the width direction of the fin is between 0 degrees and about 30 degrees. In one embodiment, the finfet is n-type, the channel mask structure includes a gate, the fin is a group IV semiconductor element or a group IV semiconductor compound, the ion implantation is performed with carbon dioxide or nitrogen, and the ion implantation dosage is greater than about 1017cm-2The energy of the ion implantation is less than about 15keV, and the angle of inclination of the ion implantation in the length direction of the channel region is between 0 degrees and about 30 degrees. In one embodiment, the finfet is n-type, the channel mask structure includes a gate, the fin is a group IV semiconductor element or a group IV semiconductor compound, the ion implantation is performed using carbon dioxide or nitrogen, and the ion implantation dosage is greater than about 1017cm-2The energy of the ion implantation is less than about 15keV, the angle of inclination of the ion implantation in the length direction of the channel region is between 0 degrees and about 30 degrees, and the angle of inclination of the ion implantation in the width direction of the fin is between 0 degrees and about 30 degrees. In one embodiment, the method further comprises performing a second ion implantation, wherein the second ion implantation is a lightly doped drain implantation for forming a lightly doped drain region, and the annealing step anneals the first ion implantation and the second ion implantation. In one embodiment, the finfet is a p-type finfet on a wafer, the channel mask structure comprises a gate, and the method further comprises: the method further includes placing a patterned masking layer on the wafer prior to the first ion implantation, the patterned masking layer covering the n-type finfet and not the p-type finfet, and performing a second ion implantation while the patterned masking layer is on the wafer, the second ion implantation being a p-type lightly doped drain implantation forming a p-type lightly doped drain region. In one embodiment, the finfet is an n-type finfet on a wafer, the channel mask structure comprises a gate, and the method further comprises: the method further includes placing a patterned masking layer on the wafer prior to the first ion implantation, the patterned masking layer covering the p-type finfet and not the n-type finfet, and performing a second ion implantation while the patterned masking layer is on the wafer, the second ion implantation being an n-type lightly doped drain implantation forming an n-type lightly doped drain region. In an embodiment, the method further includes forming an isolation region adjacent to the fin, and wherein the first ion implantation step of nitrogen or an element belonging to the group of the periodic table is performed, including implanting nitrogen or an element belonging to the group of the periodic table into the isolation region. In one embodiment, the channel region is a group III-V semiconductor compound and the implant species is nitrogen or belongs to group III or group V of the periodic Table of the elements.
Those of skill in the art will readily appreciate that variations in materials and methods may be made without departing from the scope of embodiments of the invention. It should also be appreciated that the embodiments of the present invention provide many applicable inventive concepts in addition to the specific contexts in which the embodiments are described. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (1)

1. A semiconductor device, comprising:
a transistor having a channel region, the channel region comprising a constituent element and a plurality of excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein:
the excess atoms being nitrogen or belonging to this group of the periodic Table of the elements, and
the concentration of the excess atoms in the channel region is between about 1019cm-3To about 1021cm-3To (c) to (d); and
an isolation region adjacent to the transistor, the isolation region also containing the excess atoms, and the concentration of the excess atoms in the isolation region being between about 1020cm-3To about 1021cm-3In the meantime.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11088249B2 (en) * 2019-09-17 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with implant and method of manufacturing same
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Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106512A (en) * 1993-10-04 1995-04-21 Sharp Corp Simox processing method based on molecule ion implantation
US5468657A (en) * 1994-06-17 1995-11-21 Sharp Microelectronics Technology, Inc. Nitridation of SIMOX buried oxide
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8592264B2 (en) * 2011-12-21 2013-11-26 International Business Machines Corporation Source-drain extension formation in replacement metal gate transistor device
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9570557B2 (en) * 2015-04-29 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Tilt implantation for STI formation in FinFET structures
US10418464B2 (en) 2015-06-12 2019-09-17 Intel Corporation Techniques for forming transistors on the same die with varied channel materials
US9418897B1 (en) 2015-06-15 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap around silicide for FinFETs
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9899382B2 (en) * 2016-06-01 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure with different gate profile and method for forming the same
US9812363B1 (en) 2016-11-29 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
US10115808B2 (en) * 2016-11-29 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. finFET device and methods of forming
US10680102B2 (en) * 2018-09-27 2020-06-09 International Business Machines Corporation Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors
US11610889B2 (en) * 2018-09-28 2023-03-21 Intel Corporation Arsenic-doped epitaxial, source/drain regions for NMOS
US11088249B2 (en) * 2019-09-17 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with implant and method of manufacturing same

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US11088249B2 (en) 2021-08-10
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