CN112187633A

CN112187633A - Link fault convergence method and device, electronic equipment and storage medium

Info

Publication number: CN112187633A
Application number: CN202010959074.3A
Authority: CN
Inventors: 郑宁
Original assignee: Ruijie Networks Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2021-01-05

Abstract

The embodiment of the invention provides a link fault convergence method and device, electronic equipment and a storage medium. The method comprises the following steps: if judging that the MLAG link fails, acquiring a first port corresponding to the failed link; acquiring a virtual port corresponding to the first port, wherein a next hop physical egress interface bound by the virtual port is the first port; and binding the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, wherein the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system. The link fault convergence method provided by the embodiment of the invention realizes the rapid switching of the address table items, the convergence performance of the rapid switching is only related to the physical output interface bound by the next hop applied by the virtual port and is not related to the capacity of the MAC address table items, the rapid switching of the MAC address table items is realized through the virtual port, and the design requirements of a switching chip are met.

Description

Link fault convergence method and device, electronic equipment and storage medium

Technical Field

The embodiment of the invention relates to the technical field of communication, in particular to a link fault convergence method, a link fault convergence device, electronic equipment and a storage medium.

Background

Multi-chassis Link Aggregation (MLAG) is a cross-device Link Aggregation of one device with another device, thereby improving the Link reliability from a single board level to a device level and forming a dual active system. Fig. 1 is a schematic diagram of a dual active system composed of MLAG devices in the prior art, and as shown in fig. 1, an MLAG is deployed between a DUT1 and a DUT2, so that the reliability of traffic carried by a downstream device is improved from a link level to a device level, and meanwhile, as a boundary of a two-layer network and a three-layer network, two devices of the MLAG simultaneously play a role of a gateway and share a forwarding role of three-layer traffic. As shown in FIG. 1, DUT1 and DUT2 constitute two devices of an MLAG, interconnected by a peer-link peer-to-peer link; the DUT3 and the DUT4 are two devices accessing the MLAG through Aggregation (AP) link aggregation as pure two-layer access devices, the network side of the MLAG (connected with the router R1) runs a Routing protocol, and meanwhile, the network side load balancing is realized through Equal-Cost Multipath Routing (ECMP); the TC1, the TC2 and the TC3 simulate a downlink user and a network side user to stream with each other.

Taking a two-layer Media Access Control (MAC) address table as an example, in an MLAG system, a MAC address learned by the DUT1 is synchronized to the DUT2 at the opposite end of the MLAG, and similarly, a MAC address learned by the DUT2 is also synchronized to the DUT1, so that in the MLAG system, the MAC address table as a whole can search for a local MAC address table for lookup and forwarding no matter whether a two-layer flow passes through the DUT1 or the DUT2 of the MLAG system.

MLAG system failures include: a link failure between DUT1 and DUT3, i.e., a VAP Port (Virtual Aggregate Port) failure, a link failure between DUT1 and DUT2, i.e., a peer-link Port failure, an MLAG single equipment failure, i.e., a DUT1 or DUT2 equipment failure, etc.

Taking the VAP port failure as an example, when the DUT1 senses VAP1 port DOWN, the exit of the layer two MAC address table entry needs to be switched to the peer-link port. When the VAP1 port UP, the exit of the layer two MAC address table entry needs to be switched back to the VAP1 port. Because when the port of the VAP1 goes DOWN, traffic hitting the exit of the layer two MAC address table entry pointing to the VAP port will be cut off, depending on the performance of switching the exit of the layer two MAC address table entry to the peer-link port. Normally, the performance of the MAC address switching is 2000 entries/second, and if the capacity of the two-layer MAC address table is 96K, the interruption time is at least more than 48 seconds, i.e. the fault convergence performance is strongly correlated with the capacity of the MAC address table, and the convergence performance is worse when the capacity is larger.

In view of the above problems, the general solution is: the ports interconnected between the DUT1, the DUT2, the DUT3, and the DUT4 device are all configured as Aggregate Ports (APs). When the VAP port is DOWN, the AP physical member port of the peer-link port is added into the AP member port of the VAP of the DOWN, so that even if the outlets of the table entries of the two-layer MAC addresses are not switched, the flow of the VAP port at the outlet of the two-layer MAC addresses is hit according to the load balancing principle of the AP aggregation port, and the flow is still forwarded to the VAP port when the VAP port is DOWN and is actually subjected to load balancing to the peer-link port of the member port of the VAP port.

When the VAP port is UP, the peer-link port needs to be exited from the AP member port of the VAP. Because the exit of the layer two MAC address table entry remains unchanged at the VAP port during VAP DOWN, the exit of the layer two MAC address table entry does not need to handle a switch-back operation during VAP UP.

However, the AP backup scheme itself has the following drawbacks: the AP physical member port of the peer-link needs to join the AP group of the peer-link and VAP ports at the same time, which behavior is not compliant with the protocol standards (IEEE 802.1D and 802.1Q), i.e., one physical port is not allowed to join two AP groups at the same time. In addition, the MLAG system devices need to be configured as AP aggregation ports to utilize the load balancing mechanism of the AP.

Disclosure of Invention

In order to overcome the defects in the prior art, embodiments of the present invention provide a link fault convergence method and apparatus, an electronic device, and a storage medium.

In a first aspect, an embodiment of the present invention provides a link failure convergence method, applied to a multi-chassis link aggregation MLAG system, including:

if judging that the MLAG link fails, acquiring a first port corresponding to the failed link;

acquiring a virtual port corresponding to the first port, wherein a next hop physical egress interface bound by the virtual port is the first port;

and binding the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, wherein the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system.

As above, optionally, before the determining and learning that the MLAG link fails, the method further includes:

when the first port is created, applying for a virtual port from the switching equipment where the first port is located by using the first port information;

if the application is successful, determining that a next hop physical outbound interface bound by the virtual port is the first port;

and setting the virtual port and the bound next hop physical egress interface into a switching chip of the switching equipment, so that when MAC address learning is carried out, the outlet of the corresponding MAC address table entry is the virtual port.

As above, optionally, the applying for the virtual port from the switching device where the first port is located by using the first port information includes:

acquiring a port index and a virtual local area network identifier of the first port;

and applying for a virtual port from the switching equipment where the first port is located according to the port index and the virtual local area network identifier.

As in the foregoing method, optionally, the binding the update of the next-hop physical egress interface of the virtual port to the second port corresponding to the first port includes:

applying for updating the next hop physical outgoing interface bound by the virtual port to the switching equipment where the first port is located;

if the application is successful, acquiring next hop physical outbound interface information bound by the virtual port, and determining the next hop physical outbound interface bound by the virtual port to be updated and bound as a second port according to the next hop physical outbound interface information;

and updating the next hop physical outgoing interface bound by the virtual port as the second port in the switching chip.

As in the foregoing method, optionally, after binding the update of the next-hop physical egress interface of the virtual port to the second port corresponding to the first port, the method further includes:

and if the first port is judged to be recovered to be normal, the next hop physical output interface of the virtual port is bound to the first port again.

In a second aspect, an embodiment of the present invention provides a link failure convergence device, applied in a multi-chassis link aggregation MLAG system, including:

the judging module is used for acquiring a first port corresponding to a fault link if judging that the MLAG link is in fault;

an obtaining module, configured to obtain a virtual port corresponding to the first port, where a next hop physical egress interface bound by the virtual port is the first port;

and a binding module, configured to bind a next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, where the first port is a port between an MLAG device and a downstream device in an MLAG system, and the second port is a port between MLAG devices in the MLAG system.

The above apparatus, optionally, further comprises:

the application module is used for applying for a virtual port to the switching equipment where the first port is located by the first port information when the first port is created;

a determining module, configured to determine, if the application is successful, that a next-hop physical egress interface bound by the virtual port is the first port;

and the setting module is used for setting the virtual port and the bound next hop physical egress interface into a switching chip of the switching equipment, so that when MAC address learning is carried out, the outlet of the corresponding MAC address table entry is the virtual port.

As with the apparatus described above, optionally, the application module is specifically configured to:

As with the apparatus described above, optionally, the binding module is specifically configured to:

As with the apparatus above, optionally, the binding module is further configured to:

In a third aspect, an embodiment of the present invention provides an electronic device, including:

the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform a method comprising: if judging that the MLAG link fails, acquiring a first port corresponding to the failed link; acquiring a virtual port corresponding to the first port, wherein a next hop physical egress interface bound by the virtual port is the first port; and binding the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, wherein the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system.

In a fourth aspect, an embodiment of the present invention provides a storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following method: if judging that the MLAG link fails, acquiring a first port corresponding to the failed link; acquiring a virtual port corresponding to the first port, wherein a next hop physical egress interface bound by the virtual port is the first port; and binding the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, wherein the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system.

The link failure convergence method provided by the embodiment of the invention modifies the next hop physical outgoing interface of the virtual port corresponding to the port of the failed link when the link failure occurs in the MLAG, modifies the next hop physical outgoing interface of the virtual port corresponding to the port of the recovered link as the original MLAG port when the link is recovered, and realizes the fast switching of the address table items by modifying the mapping relation of the actual physical outgoing interface bound by the next hop of the virtual port, the convergence performance of the fast switching is only related to the physical outgoing interface bound by the next hop applied by the virtual port and is unrelated to the capacity of the MAC address table items, and the fast switching of the MAC address table items is realized through the virtual port, thereby meeting the design requirements of the switch chip.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a dual active system composed of MLAG devices in the prior art;

fig. 2 is a schematic flow chart of a link fault convergence method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a link failure convergence apparatus according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 2 is a schematic flow chart of a link failure convergence method provided in an embodiment of the present invention, as shown in fig. 2, the method includes:

step S21, if judging that the MLAG link fails, acquiring a first port corresponding to the failed link;

specifically, in the MLAG system as shown in fig. 1, the MLAG apparatus includes: DUT1 and DUT2, the downstream equipment of the MLAG equipment including: DUT3 and DUT 4. The MLAG port includes ports between the MLAG device and a downstream device, such as a VAP port between DUT1 and DUT3, a VAP port between DUT2 and DUT4, and a port between the MLAG device, such as a peer-link port between DUT1 and DUT2, when the system creates an MLAG port, that is, when a creation notification of the VAP port or peer-link port is issued, the link failure convergence apparatus acquires a port index (ifindex) of the currently created MLAG port and a Virtual local area network identity (VLAN-ID) of the port, and then initiates a create session request to the switching device where the MLAG port is located, and applies for a corresponding Virtual port (Virtual port, VP) resource. And in the session creating request, carrying the ifindex and the VLAN-ID of the MLAG port, and applying for VP resources from a bottom hardware chip of the switching equipment in the form of the ifindex + the VLAN-ID.

After the VP resources are successfully created by the bottom hardware chip in the switching equipment, the available VP resources are returned to the applied service module. The VP resources include available next hop resource information, which includes information such as the bound next hop physical egress interface and VLAN-ID encapsulated by the interface. And the bound next hop physical egress interface is an MLAG port used in application. After receiving the returned VP resource, the link failure convergence device determines whether the next hop resource information is available, and besides the next hop resource information includes the above information, it also needs to determine whether the next hop information is reachable, and the link state of the bound next hop physical egress interface is UP.

After confirming that the next hop resource information is available, the link fault convergence device sets the VP and the bound next hop physical egress interface into a switching chip of the switching device, when the MLAG port performs address learning, the two-layer MAC address is learned on the VP on the chip, and the outlet of the corresponding MAC address table entry is the VP virtual port. When the two-layer message reaches the MLAG device, the address learning is carried out according to the source MAC address of the message, and the MAC address table is searched according to the destination MAC address of the message. And if the address table entry is found, forwarding the two-layer message according to the exit of the table entry. Because the outlet of the table entry is mapped to the VP virtual port, the next hop resource can be searched according to the VP virtual port in the actual message forwarding process, the physical output interface bound by the next hop is obtained, and the message is forwarded from the actual physical output interface. Because the MAC address needs to be displayed externally on the user layer, VP resource conversion can be carried out, the VP is converted into a bound next-hop physical output interface, the VP is not sensed on the user layer, and only the actual physical output interface is seen. The VP virtual port is set to be supported by the exchange chip, and the exchange chips of the current mainstream chip suppliers are supported, so that the design requirements of the exchange chip are met.

As shown in fig. 1, MLAG link failures include: a link failure between DUT1 and DUT3, i.e., a VAP port failure, a link failure between DUT1 and DUT2, i.e., a peer-link port failure, etc. The link failure convergence device installed in the MLAG system may detect whether the MLAG link fails in a ping packet form through a network diagnostic tool, or the link failure convergence device may detect a port state, and determine whether the MLAG link fails in a normal state (UP) or an abnormal state (DOWN), and if the MLAG link fails, obtain an MLAG port corresponding to the failed link, and record the MLAG port as a first port, where the first port may be a VAP port, that is, the first port is a port between an MLAG device and a downstream device in the MLAG system. .

Step S22, obtaining a virtual port corresponding to the first port, where a next hop physical egress interface bound by the virtual port is the first port;

specifically, after determining a first port corresponding to a failed link, the link failure convergence device acquires a virtual port corresponding to the first port, where a next-hop physical outgoing interface bound by the virtual port is the first port, for example, a next-hop bound by VP1 is VAP1, and when the VAP1 state is DOWN, determines that a virtual port corresponding to VAP1 is VP 1. It should be noted that the ifindex + VLAN-ID of the MLAG port used in applying for VP1 is not the actual ifindex + VLAN-ID of the virtual port VP1, but is only used in applying for VP1, and the actual VLAN ID of VP1 is consistent with the next-hop physical egress interface to which it is bound.

Step S23, binding the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, where the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system.

Specifically, after the link failure convergence apparatus determines a virtual port corresponding to a first port, the link failure convergence apparatus applies for updating a next-hop physical egress interface bound by the virtual port to the switching device where the first port is located, and at this time, the switching device updates the next-hop physical egress interface bound by the virtual port to a second port corresponding to the first port, where the first port is a port between an MLAG device and a downstream device in the MLAG system, the second port is a port between MLAG devices in the MLAG system, for example, the first port is a VAP port, and the second port is a peer-link port. If the application is successful, acquiring next hop physical outbound interface information bound by the virtual port, and determining the next hop physical outbound interface bound by the virtual port to be updated and bound as a second port corresponding to the first port according to the next hop physical outbound interface information;

and then, updating the next hop physical outgoing interface bound by the virtual port as the second port in the switching chip. It should be noted that the VAP port may be a plurality of ports, the corresponding relationship between the VAP port and the peer-link port may be a many-to-one relationship, and after the next-hop physical outbound interface bound to the virtual port is updated, the VAP port identifier corresponding to the next-hop physical outbound interface may also be recorded, so that after the VAP port is recovered to be normal, the next-hop physical outbound interface of the virtual port may be recovered to be the VAP port. For example, after the port of the VAP1 goes DOWN, the next hop physical out interface bound to the VP1 corresponding to the port of the VAP1 is updated from the original VAP1 to be bound to a peer-link port.

When the two-layer message reaches the MLAG device, the address learning is carried out according to the source MAC address of the message, and the MAC address table is searched according to the destination MAC address of the message. And if the address table entry is found, forwarding the two-layer message according to the exit of the table entry. Because the outlet of the table entry is mapped to the VP virtual port, the next hop resource can be searched according to the VP virtual port in the actual message forwarding process, the physical output interface bound by the next hop is obtained, and the message is forwarded from the actual physical output interface. Because the information of the next hop physical output interface of the virtual port VP is only changed, the VP does not change, and the outlet of the MAC address table entry is still installed on the original VP when the MLAG link fails, the batch switching of the address table entries is not involved when the MLAG link fails.

Further, if it is determined that the first port returns to normal, the next-hop physical egress interface of the virtual port is bound as the first port again.

Specifically, after the first port is determined to be recovered to normal, that is, when a link state UP notification message of the first port is received, the link failure recovery is performed, a request is made to the switching device to update the next-hop physical outbound interface corresponding to the virtual port, and the next-hop physical outbound interface of the virtual port is rebonded to be the first port.

Similarly, when the MAC address is searched and the target MAC is matched, the outlet of the MAC address table item still maintains the virtual port unchanged, and when the hardware forwards the MAC address, the virtual port is forwarded according to the physical output interface bound by the VP virtual port.

Based on the same inventive concept, an embodiment of the present invention further provides a link failure convergence device, which is applied in a multi-chassis link aggregation MLAG system, and as shown in fig. 3, the link failure convergence device includes: a judging module 31, an obtaining module 32 and a binding module 33, wherein:

the determining module 31 is configured to, if it is determined that the MLAG link fails, obtain a first port corresponding to the failed link;

the obtaining module 32 is configured to obtain a virtual port corresponding to the first port, where a next hop physical egress interface bound by the virtual port is the first port;

the binding module 33 is configured to bind the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, where the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system.

The above apparatus, optionally, further comprises:

The apparatus provided in the embodiment of the present invention is configured to implement the method, and its functions specifically refer to the method embodiment, which is not described herein again.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 4, the electronic device includes: a processor (processor)41, a memory (memory)42, and a bus 43;

wherein, the processor 41 and the memory 42 complete the communication with each other through the bus 43;

processor 41 is configured to call program instructions in memory 42 to perform the methods provided by the above-described method embodiments, including, for example: if judging that the MLAG link fails, acquiring a first port corresponding to the failed link; acquiring a virtual port corresponding to the first port, wherein a next hop physical egress interface bound by the virtual port is the first port; and binding the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, wherein the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system.

An embodiment of the present invention discloses a computer program product, which includes a computer program stored on a non-transitory computer readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer, the computer can execute the methods provided by the above method embodiments, for example, the method includes: if judging that the MLAG link fails, acquiring a first port corresponding to the failed link; acquiring a virtual port corresponding to the first port, wherein a next hop physical egress interface bound by the virtual port is the first port; and binding the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, wherein the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system.

Embodiments of the present invention provide a non-transitory computer-readable storage medium, which stores computer instructions, where the computer instructions cause the computer to perform the methods provided by the above method embodiments, for example, the methods include: if judging that the MLAG link fails, acquiring a first port corresponding to the failed link; acquiring a virtual port corresponding to the first port, wherein a next hop physical egress interface bound by the virtual port is the first port; and binding the next-hop physical egress interface update of the virtual port to a second port corresponding to the first port, wherein the first port is a port between an MLAG device and a downstream device in the MLAG system, and the second port is a port between MLAG devices in the MLAG system.

Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

The above-described embodiments of the apparatuses and the like are merely illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A link fault convergence method is applied to a multi-chassis link aggregation (MLAG) system and is characterized by comprising the following steps:

2. The method of claim 1, wherein before the determining learns that the MLAG link fails, further comprising:

when a first port is created, applying for a virtual port to switching equipment where the first port is located by using the first port information;

3. The method according to claim 2, wherein the applying for the virtual port from the switching device where the first port is located by using the first port information includes:

4. The method of claim 2, wherein binding the next hop physical egress interface update of the virtual port to a second port corresponding to the first port comprises:

5. The method of claim 1, wherein after binding the next hop physical egress interface update of the virtual port to the second port corresponding to the first port, further comprising:

6. A link failure convergence device is applied to a multi-chassis link aggregation (MLAG) system and is characterized by comprising the following components:

7. The apparatus of claim 6, further comprising:

8. The apparatus of claim 7, wherein the binding module is further configured to:

9. An electronic device, comprising:

the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any of claims 1 to 5.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of claims 1 to 5.